JPH10240704A - Multiprocessor system and instruction generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform processing without exceeding the heat generation permissible limit of a chip by rescheduling instructions by processors on a chip according to the predicted total heating value, and suppressing the heat generation of the whole chip. SOLUTION: When allocating instructions which are compiled to respective processors P1 to Pn , a 1st scheduling means 2 schedules execution order, etc., by the instructions allocated to the processors P1 to Pn , and a heating value predicting means 3 predicts the heating value of a single processor body by the instructions. Thus, a total heating value predicting means 4 predicts the heating value of the whole chip 10 from the heating values of the respective processors P1 to Pn and a 2nd scheduling means 5 reschedules the instructions by the processors P1 to Pn scheduled by the 1st scheduling means 2 according to the predicted total heating value, thereby suppressing the heating value of the whole chip 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiprocessor system in which a plurality of independently operable processors are mounted on a chip, and an instruction creating apparatus.

[0002]

2. Description of the Related Art In recent years, with the advance of LSI manufacturing technology, ultra-miniaturization and high integration have progressed, and it has become possible to arrange (mount) a plurality of processors on one chip. Therefore, the problem of heat generation in the chip has been newly considered as a performance limit of the chip. This is because when the activation rate in the chip increases, the amount of heat generated rises and exceeds the allowable value of heat generation of the chip, so that the operation limit of the chip is defined by heat generation (that is, processing cannot be performed efficiently) It also means that.

[0003]

As described above, in the conventional multiprocessor system, when the activation rate in the chip increases, the heat generation increases, exceeding the allowable heat generation value of the chip, and efficiently executing the processing. There is a problem that a situation occurs in which it cannot be performed.

According to the present invention, when a plurality of processors are mounted on a chip, each processor is controlled so as to suppress the heat generation of the entire chip, and the processing is efficiently executed while suppressing the heat generation of the entire chip. It is an object of the present invention to provide a multiprocessor system and an instruction creating device capable of performing the above.

[0005]

According to a first aspect of the present invention, there is provided a multiprocessor system in which a plurality of independently operable processors are mounted on a chip. Instruction allocating means for allocating a subsequent instruction to each processor; first scheduling means for scheduling instructions so as to synchronize instructions allocated to each processor; and a heat generation amount of the processor alone for each instruction step. Means for estimating the amount of heat generation, means for estimating the heat generation of the entire chip from the amount of heat generated by each processor, and instructions for each processor on the chip from the amount of heat generated by the total heat generation predicted by the means Second scheduling means for rescheduling the chip and suppressing the heat generation of the entire chip. It is characterized.

In the invention according to claim 2 or 5, the first scheduling means selects an instruction candidate to be executed next from a plurality of instructions in an execution waiting state. And the calorific value predicting means comprises:
For the instruction candidate selected by the first scheduling means, a predicted value of the heat value per instruction step of the processor alone is calculated, and the total heat value prediction means calculates the predicted value of the heat value per instruction step of each processor. From the predicted heat value of the entire chip in instruction step units, and further, cumulatively adds the predicted value of the heat value of the entire chip in instruction step units for each predetermined instruction step for a unit time,
The cumulative addition value during the unit time is calculated as a total heat value,
The second scheduling means, when the total calorific value calculated by the total calorific value prediction means exceeds the limit value,
The rescheduling of instructions for each processor scheduled by the first scheduling means is performed so as not to exceed the limit value.

According to the third and seventh aspects of the present invention, feedback is performed from the second scheduling means to the first scheduling means, and the instruction rescheduled by the second scheduling means is transmitted to the first scheduling means. The rescheduling process by the first scheduling means is repeated a predetermined number of times.

Further, in the invention according to claim 6, in the calculation of the total heat generation amount per unit time, the total heat generation amount prediction means calculates a predicted value of the heat generation amount of the entire chip in instruction step units by a predetermined command. It is characterized in that the total heat value is calculated by adding the heat value of the command for which the unit time has elapsed for the unit time and subtracting the heat value of the command after the unit time has elapsed from the cumulative value.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. The present invention provides a multiprocessor system in which a plurality of processors are implemented, because of the problem of dependency between processors when performing parallel processing (because it is necessary to synchronize between processors), There can be no situation where processors are always running (no situation where all processors are executing instructions at the same time).
This is done by paying attention to the fact that there is always a processor that is in a waiting state (a processing waiting state due to data waiting or the like). In other words, the present invention controls the processor while efficiently using the processor waiting for the processing and controlling the processor while minimizing the influence on the processing. It is intended to perform well.

FIG. 1 is a diagram showing a configuration example of a multiprocessor system according to the present invention. Referring to FIG. 1, the multiprocessor system, one processor P ₁ to P _n of the plurality of possible independent operation is implemented in the chip 10
When, and a command creation device 11 for allocating instruction codes to each processor P ₁ to P _n on the chip 10 based on the source list SL, incorporated.

Here, the instruction creating device 11 is realized by, for example, a workstation or the like, and functions as a development device of the multiprocessor system.
Compiler 9 for compiling source list SL, instruction allocating means 1 for allocating compiled instructions (object code (machine language instructions)) to each of processors P _{1 to} P _n on chip 10, and each of processors P _{1 to} P _n First scheduling means 2 for scheduling instructions so as to synchronize the instructions assigned to each of the instructions, heat generation amount prediction means 3 for predicting the heat generation amount of the processor alone for each instruction step, and each of the processors P ₁ to P ₁ . The total heat generation amount prediction means 4 for predicting the heat generation amount of the entire chip 10 from the heat generation amount of _Pn , and the first scheduling means 2 performs scheduling based on the total heat generation amount predicted by the total heat generation amount prediction means 4. Second scheduling means 5 for rescheduling instructions for each processor and suppressing the heat generation of the entire chip 10 And

Here, the first scheduling means 2
When the compiled instructions are allocated to the processors, scheduling such as the execution order is performed for each instruction allocated to each processor, and the heat generation amount prediction means 3 sequentially selects instruction candidates to be processed.

More specifically, the first scheduling means 2 includes a dependency analysis means 7 for analyzing data dependencies and control dependencies between instructions allocated to each processor. Based on the analysis result, the execution order of instructions is rearranged, a wait instruction is inserted, and the like.

Further, the heat generation amount prediction means 3 generates a heat generation amount of the instruction candidate selected by the first scheduling means 2 in a unit of an instruction step of a processor alone (a heat generation amount of each processor when the instruction candidate is executed on the processor). ) Is calculated.

Specifically, the heat generation amount prediction means 3 stores in advance a predicted value of the heat generation amount for one processor corresponding to one instruction as a table in a memory, for the instruction group of the processor, When the (object code) is allocated to each processor, these values are read for each instruction step, and a predicted value of the heat generation amount per instruction step of the processor alone is obtained for the instruction candidate selected by the first scheduling means 2. It has become. Note that the predicted value of the calorific value can be obtained by simulation, experiment, or the like.

The total heat generation amount predicting unit 4 predicts the heat generation amount of the entire chip in instruction step units from the predicted value of the heat generation amount in instruction step units of each processor. The predicted value of the calorific value is cumulatively added for a unit time for each predetermined instruction step, and the cumulative added value for the unit time is calculated as the total calorific value.

That is, the total calorific value predicting means 4 firstly
The heat value of each of the processors P _{1 to} P _n is obtained for each instruction step, and the heat value of the entire chip 10 is obtained by obtaining the sum of the N heat values. This is the total amount of heat generated per instruction execution time. Further, this value is cumulatively added only during the unit time to obtain the total heat generation per unit time.

FIG. 2 shows a heating value estimating means when only _two processors P ₁ and P ₂ among N processors P _{1 to} P _n are operating (executing instructions). 3, the processing outline of the total calorific value estimating means 4 is shown. Referring to FIG. 2, the processors P ₁ and P ₂ inside the chip
If There is a running instruction, firstly, the heat generation amount prediction means 3 reads the calorific value H1 of C1 from the predicted value table by the instruction code C1 of the instruction of the processor P _1,
Further, by reading the calorific value H2 by instruction code C2 of the instruction of the processor P _2, calculates a predicted value of the heating value of a single processor instruction step unit.

Next, the total heat generation amount prediction means 4 obtains the total heat generation amount S1 (total heat generation amount per instruction execution time) of the entire chip in the instruction step by obtaining the sum S1 of these heat generation amounts H1 and H2. Further, the calorific value S1 is cumulatively added during the unit time to obtain a total calorific value S2 per unit time.

Here, the unit time means the time until heat generated inside the chip is radiated to the outside. Actually, since it is affected by the heat transfer characteristics of a package or the like covering the chip, an appropriate value as a unit time can be obtained from a simulation or an experiment.

Further, the second scheduling means 5 comprises:
If the total calorific value calculated by the total calorific value predicting means 4 exceeds the limit value, the first heat value is set so as not to exceed the limit value.
The first scheduling means is configured to replace the next instruction candidate selected by the scheduling means 2 with the execution of another instruction, change the instruction execution order, or insert a wait instruction for suppressing heat generation. 2 for rescheduling instructions for each processor scheduled.

In other words, when focusing on instruction scheduling, the part that synchronizes with another processor is performed by the first scheduling means 2, and the part that limits the heat generation is performed by the second scheduling means 5. . That is, in the system of FIG.
The instruction scheduling is performed by the scheduling means 2 so as to synchronize with another processor, the instruction part for synchronizing is fixed, and the second scheduling means 5 further sets a predetermined instruction schedule section. The rescheduling is performed so that the calorific value at the time is within the limit.

FIG. 3 is a diagram for explaining the outline of the processing in the second scheduling means 5 when the processing shown in FIG. 2 is performed by the heat generation amount prediction means 3 and the total heat generation amount prediction means 4. . In the example of FIG. 3, for convenience of explanation,
The execution time interval of one instruction is one instruction step, and therefore,
One block (execution time of one instruction) on the horizontal axis in FIG. 3 is one instruction step.

In FIG. 3, the area in which the unit time is set is, as described above, the cumulative addition value S2 (the cumulative value of the predicted heating value (table read) corresponding to the instruction described in the target area). The second scheduling means 5 divides the cumulative addition value S2 in the above-mentioned area (unit time) by the number of instructions in the target area, and the averaged result is the limit value. Schedule instructions to stay within the range. Note that in the example of FIG. 3, the unit time is eight instruction steps.

FIG. 4 shows one processor, for example, P _m
An example of an instruction schedule for is shown. FIG.
In this example, the instruction schedule assigned to the processor P _m is determined as K instructions Schedule sections A ₁ to A _k. In this case, one of the K instruction schedule sections A _{1 to} A _k corresponds to the unit time (heat generation amount calculation range). In other words,
In the example of FIG. 4, the instruction schedule section has the same number of instruction steps as the unit time.

As described above, in the first configuration example, by dividing the target area into sections, the cumulative addition value S2 is obtained for each section. Therefore, S2 is obtained by cumulatively adding all the predicted values of the heat generation amount corresponding to the instructions described in the section. Referring to FIG. 3, the second scheduling means 5 indicates that the scheduling operation is performed such that the average value of the amount of heat generated within a unit time is equal to or less than the limit value TH. The heat generation above TH is averaged out, so that it is not a problem.

Next, an example of the processing operation of the multiprocessor system having such a configuration will be described with reference to the flowchart of FIG. Referring to FIG. 5, first, the created source list (program) SL is compiled by a compiler 9 or the like, and an object code executable by a single processor is obtained.
The instruction is converted into a machine language instruction at the time of execution (step S1). In this way, the instruction of the machine language level (object code) is given, the instruction in the allocation unit 1 allocates the instruction after the compile (object code) to each processor P ₁ to P _n (step S2). This processing is, specifically, the instruction converted to the machine language level
In order to adapt the (object code) to the multiprocessor system, instruction division is performed in consideration of data dependency when instructions are distributed to each processor, and assignment is performed to each processor.

Next, the dependency analysis means 7 analyzes the data dependency and the control dependency with other processors in the instructions divided for each processor (step S).
3). Thereafter, the first scheduling unit 2 synchronizes data between instructions assigned to each processor P ₁ to P _n, performs scheduling instruction (step S4). Specifically, in order to synchronize each processor based on the data dependency and the control dependency, the order of instruction execution is changed, and a wait instruction with a heat generation suppression function added thereto is inserted.

When the instruction is thus scheduled, the heat generation amount prediction means 3 predicts the heat generation amount of the processor alone for each instruction step (step S5). The heat value of each command step of the entire chip 10 is predicted from the heat value of each instruction step of _{1 to Pn} , and the heat value of each command step of the entire chip is summed per unit time to obtain the total heat value. Predict (step S6). At this stage, the second scheduling means 5 re-schedules the instruction based on the heat generation amount prediction result by the total heat generation amount prediction means 4 (step S7).

More specifically, when the total heat generation amount predicted by the total heat generation amount prediction means 4 exceeds the limit value, the second scheduling means 5 performs the first scheduling so as not to exceed the limit value. either replace next instruction candidate selected by the scheduling means 2 to perform other instructions, or to insert wait instruction to suppress heat generation, performs rescheduling of instructions for the processors P ₁ to P _n, re incorporating the scheduled instructions to each processor P ₁ to P _n on the chip 10. Each processor P ₁ to P _n on the chip 10 executes instructions that are rescheduled, in this case, the instruction is the re-scheduling is also total heat of the processors P ₁ to P _n when you do this The amount (the total amount of heat generated by the entire chip 10) is suppressed to the limit value or less, so that the processing can be executed efficiently.
That is, the instruction can be executed without making the heat generation amount in the chip 10 equal to or more than the allowable value.

In the above example, the processing shown in FIG. 2 is performed by the calorific value predicting means 3 and the total calorific value predicting means 4.
Instead of the processing as shown in FIG. 2, the processing as shown in FIG. 6 may be performed. That is, in the processing example of FIG. 6, the total heat generation amount prediction means 4 calculates the total heat generation amount per unit time by using the predicted value of the heat generation amount of the entire chip in instruction step units for each predetermined instruction step. During the time, the total heat value is calculated by adding the heat value of the command after the unit time has elapsed and subtracting the heat value of the instruction after the unit time has elapsed from the cumulative value.

[0032] Specifically, in the processing example of FIG. 6, when the processor P ₁ and processor P ₂ of the chip is to be executing instructions, first, similarly to the processing example in FIG. 2, the calorific value predicting means 3, the instruction code C1 of the instruction of the processor P ₁
Reading the heating value H1 of C1 from the predicted value table, the addition, the instruction code of the instruction of the processor P ₂ C2
To read out the heat generation amount H2, and calculate the predicted value of the heat generation amount for each instruction step of the processor alone.

Next, the total heat generation amount prediction means 4 obtains the total heat generation amount S1 (total heat generation amount per instruction execution time) of the entire chip in the instruction step by obtaining the sum S1 of these heat generation amounts H1 and H2. Further, the calorific value S1 is cumulatively added during the unit time, and the total calorific value per unit time is obtained from the cumulative added value. In this case, in the processing example of FIG. The calorific value of the command is subtracted from the cumulative addition value, and this is calculated as the total calorific value S2. That is, the calorific value of a new command is added for each command step, and the calorific value of a past command deviating from the target area is subtracted. Thereby, the unit time area (target area) can be moved. In other words, in the processing example of FIG. 6, the cumulative addition value S2 is obtained each time the section is moved in the unit time area (target area) for each instruction step (each instruction execution time).

FIG. 7 shows an example of a unit time section for which the calorific value is calculated in this case. In this example, the calorific value of the newly selected instruction is cumulatively added for each instruction step, and the calorific value of the instruction after a certain unit time has elapsed is subtracted from the cumulative addition value, so that the unit time for which the calorific value is calculated is calculated. The area can be moved.

As described above, the total calorific value estimating means 4 performs the processing shown in FIG.
In the processing example of, the total heat generation amount S2 can be calculated by moving the unit time area for each instruction step.

In general, there are two types of scheduling: dynamic scheduling and static scheduling.
In the above example, static scheduling is considered. That is, in the case of dynamic scheduling, a real-time measurement process is performed, and therefore, a heat management processor and a heat sensor are required. In the case of static scheduling, the heat management processor and the heat sensor are used. do not need. That is, in the static scheduling of the program data for operating the processors P _{1 to} P _n , the heat generation behavior of the chip assuming the program execution is prepared in advance by simulation or experiment, etc., and the heat generation data for each instruction is prepared. Thermal management processing can be performed.

As described above, the processing flow of the static scheduling is as follows. After the program source is compiled, the compiled (translated) machine instruction code is
The instruction code is subjected to heat management processing via the instruction allocating means 1, the first scheduling means 2, the heat generation amount prediction means 3, the total heat generation prediction means 4, and the second scheduling means 5. However, when the second scheduling means 5 inserts a wait instruction for suppressing heat generation,
Hardware for executing the wait instruction code is required. In this case, as a function when the wait instruction code for suppressing heat generation is executed, hardware (a function for suppressing heat generation due to switching) that realizes a function of shutting off a clock line for a resource and a function of reducing voltage is required. Therefore, in this case, the second scheduling means 5 is preferably provided as hardware on the chip 10.

FIG. 8 is a diagram showing another configuration example of the multiprocessor system according to the present invention. Referring to FIG. 8, the instruction creating device 5 of this multiprocessor system
1 basically has the same configuration as the instruction creating device 11 of the multiprocessor system of FIG. 1, but the instruction creating device 51 of FIG.
The feedback control to the first scheduling means 2 is performed.

FIG. 9 shows the multiprocessor system of FIG.
5 is a flowchart illustrating an example of a processing operation of the (command creation device 51). Referring to FIG. 9, the instruction creating device 51 of FIG.
1 basically performs the same processing operation as the processing operation of FIG. 5 of the instruction generation device 11 of FIG. 1, but the instruction generation device 51 of FIG. Again, in step S3,
Analysis of data dependence and control dependence is performed, and step S
In step 4, rearrangement of instructions for synchronization and insertion of wait instructions are performed.

By repeating such feedback a predetermined number of times, more efficient instruction scheduling becomes possible, and more efficient heat generation control becomes possible.

FIG. 10 is a diagram showing an example of a hardware configuration of the instruction creating apparatus shown in FIG. 1 or FIG. Referring to FIG. 10, this instruction creating apparatus is realized by, for example, a workstation or a personal computer, and is used as a CPU 21 for controlling the whole, a ROM 22 storing a control program of the CPU 21, and a work area of the CPU 21. RAM 23 and source list S
It has an input device 24 for inputting L and an output device 26 for supplying the created instruction code to each processor on the chip 10.

Here, the CPU 21 operates as shown in FIG.
, An instruction allocating unit 1, a first scheduling unit 2, a heat generation amount predicting unit 3, a total heat generation predicting unit 4, and a second scheduling unit 5.

The functions of the compiler 9, the instruction allocating means 1, the first scheduling means 2, the heat generation amount prediction means 3, the total heat generation prediction means 4, the second scheduling means 5, and the like in the CPU 21 are as follows. For example, it can be provided in the form of a software package (specifically, an information recording medium such as a CD-ROM). Therefore, in the example of FIG. A driving device 31 is provided.

In other words, the instruction creating apparatus of the present invention causes a general-purpose computer system to read a program recorded on an information recording medium such as a CD-ROM, and causes the microprocessor of the general-purpose computer system to execute the above-described processing. The present invention can also be implemented in a device configuration to be executed. In this case, a program for executing the instruction creation processing of the present invention (that is, a program used in the hardware system) is provided in a state recorded on a medium. As an information recording medium on which programs and the like are recorded, CD-
The invention is not limited to the ROM, and a ROM, a RAM, a flexible disk, a memory card, or the like may be used. The program recorded on the medium is installed in a storage device incorporated in the hardware system, for example, a hard disk device, so that the program is executed, and the compiler 9, instruction allocating means 1, first scheduling means 2 , The calorific value predicting means 3, the total heat generating predicting means 4, and the second scheduling means 5, which contribute to the construction of a multiprocessor system.

A program for realizing the functions of the compiler 9, instruction allocating means 1, first scheduling means 2, heat generation amount predicting means 3, total heat generation predicting means 4, and second scheduling means 5 of the present invention. May be provided not only in the form of a medium but also by communication (for example, by a server).

Further, in the example of FIG.
Although the chip 10 is configured as a device separate, instruction creation device, on the chip 10, may be implemented with the processor P ₁ to P _n. That is, in addition to the processors P _{1 to} P _n , for example, a CPU and a ROM that function as an instruction creating device are mounted on the chip 10,
The instruction itself is supplied from the ROM or generated by the CPU, and the instruction supplied from the ROM or the instruction generated by the CPU without the need for an external input / output interface such as the output device 26 in FIG. To the processor P ₁
~ _Pn . In other words, it is also possible to construct a multiprocessor system implemented on a single chip also include instructions creating device not only processor P ₁ to P _n, in this case, all the control in one chip Is made.

[0047]

As described above, according to the first, second, fourth, and fifth aspects of the present invention, a multiprocessor in which a plurality of independently operable processors are mounted on a chip. In a processor system, an instruction allocating means for allocating a compiled instruction to each processor on a chip, and a first method for scheduling instructions so as to synchronize data between instructions allocated to each processor.
Scheduling means, heat generation amount prediction means for predicting the heat generation amount of each processor for each instruction step, total heat generation amount prediction means for predicting the heat generation amount of the entire chip from the heat generation amount of each processor, and total heat generation amount prediction means A second method for rescheduling instructions for each processor on the chip from the predicted total heat generation to suppress the heat generation of the entire chip.
Scheduling means, taking into account the heat generation amount, and by suppressing the heat generation amount of the entire chip, it is possible to perform processing without exceeding the heat generation allowable limit of the chip, thereby achieving low power consumption. Can be achieved.

According to the third and seventh aspects of the present invention, feedback is performed from the second scheduling means to the first scheduling means, and the instruction rescheduled by the second scheduling means is provided. Is repeated a predetermined number of times by the first scheduling means, thereby enabling more efficient instruction scheduling and more efficient heat generation control.

According to the present invention, in the calculation of the total heat generation amount per unit time, the total heat generation amount prediction means determines a predicted value of the heat generation amount of the entire chip in instruction step units. The total heat value is calculated by subtracting the heat value of the command whose unit time has elapsed from the cumulative addition value while calculating the total heat value during the unit time for each command step. It is possible to move in a unit time section, and the calorific value can always be calculated in the latest execution step, so that fine power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a multiprocessor system according to the present invention.

FIG. 2 is a diagram illustrating an outline of a processing example of a heat generation amount prediction unit and a total heat generation amount prediction unit.

FIG. 3 is a diagram for explaining an outline of a process performed by a heat generation amount control unit when the process illustrated in FIG. 2 is performed by a heat generation amount prediction unit and a total heat generation amount prediction unit;

[4] One of the processors is a diagram showing an example of instruction scheduling for example for P _m.

FIG. 5 is a flowchart for explaining a processing operation example of the multiprocessor system of FIG. 1;

FIG. 6 is a diagram showing an outline of another processing example of the heat generation amount prediction means and the total heat generation amount prediction means.

FIG. 7 is a diagram illustrating an example of a unit time section to be subjected to calorific value calculation in the processing example of FIG. 6;

FIG. 8 is a diagram showing another configuration example of the multiprocessor system according to the present invention.

9 is a flowchart for explaining a processing operation example of the multiprocessor system of FIG. 8;

FIG. 10 is a diagram illustrating an example of a hardware configuration of the instruction creating device of FIG. 1 or FIG.

[Explanation of symbols]

1 instruction allocation unit 2 first scheduling unit 3 heat value predicting means 4 gross calorific value prediction means 5 second scheduling means 7 dependence analyzing means 9 compiler 10 chip 11 instruction creation device P ₁ to P _n processors SL Source List

Claims (7)

[Claims] In a multiprocessor system in which a plurality of independently operable processors are mounted on a chip, instruction allocating means for allocating compiled instructions to each processor on the chip, and instructions allocated to each processor Analyze data dependencies and control dependencies between
First to schedule instructions so as to synchronize
Scheduling means, heat generation amount prediction means for predicting the heat generation amount of each processor for each instruction step, total heat generation amount prediction means for predicting the heat generation amount of the entire chip from the heat generation amount of each processor, and total heat generation amount prediction means A second method for rescheduling instructions for each processor on the chip from the predicted total heat generation to suppress the heat generation of the entire chip.
And a scheduling means. 2. The multiprocessor system according to claim 1, wherein said first scheduling means selects an instruction candidate to be executed next from a plurality of instructions in an execution waiting state. The heating value predicting means calculates a predicted value of a heating value for each instruction step of the processor alone with respect to the instruction candidate selected by the first scheduling means; Predict the heat value of the entire chip in instruction steps from the predicted value of the heat value in step units, and further calculate the predicted value of the heat value of the entire chip in instruction steps for a unit time for each predetermined instruction step. The cumulative addition value during the unit time is calculated as a total heat value, and the second scheduling means calculates the total heat value by the total heat value prediction means. When the total amount of generated heat exceeds the limit value, rescheduling of instructions for each processor scheduled by the first scheduling means is performed so as not to exceed the limit value. And a multiprocessor system. 3. The multiprocessor system according to claim 1, wherein feedback is performed from said second scheduling means to said first scheduling means, and said instruction is rescheduled by said second scheduling means. A re-scheduling process is repeated a predetermined number of times by the first scheduling means. 4. In a multiprocessor system in which a plurality of independently operable processors are mounted on a chip, an instruction creating device for creating an instruction to be executed by each processor on the chip is provided. Instruction allocating means for allocating the compiled instruction to each processor on the chip; first scheduling means for scheduling the instructions so as to synchronize data between the instructions allocated to each processor; A calorific value predictor for predicting the calorific value of the processor alone, a total calorific value predictor for predicting the calorific value of the entire chip from the calorific value of each processor, and an on-chip based on the total calorific value predicted by the total calorific value predictor. The second schedule for rescheduling the instructions for each processor and suppressing the heat generation of the entire chip An instruction creating device comprising: ring means. 5. The instruction generating apparatus according to claim 4, wherein
The first scheduling means selects an instruction candidate to be executed next from a plurality of instructions in an execution waiting state, and the heat generation amount prediction means
For each of the instruction candidates selected by the scheduling means, the predicted value of the heat value per instruction step of the processor alone is calculated, and the total heat value prediction means calculates the instruction from the predicted value of the heat value per instruction step of each processor. Predict the heat value of the entire chip in steps,
The predicted value of the heat generation amount of the entire chip in instruction step units is cumulatively added for a unit time for each predetermined instruction step, and the cumulative addition value for the unit time is calculated as the total heat generation amount. When the total heat value calculated by the total heat value prediction means exceeds the limit value, the scheduling means re-executes the instruction for each processor scheduled by the first scheduling means so as not to exceed the limit value. An instruction creating device for performing scheduling. 6. The instruction generation device according to claim 4, wherein said total heat generation amount predicting means calculates the total heat generation amount per unit time by calculating the total heat generation amount per unit time. That the predicted value is cumulatively added during the unit time for each predetermined instruction step, and the heat generation amount of the instruction whose unit time has elapsed is subtracted from the cumulative addition value to calculate the total heat generation amount. Instruction creation device characterized by the following. 7. The instruction generating apparatus according to claim 4, wherein feedback from said second scheduling means to said first scheduling means is performed, and said instruction rescheduled by said second scheduling means. Wherein the first scheduling means repeats the re-scheduling process a predetermined number of times.