JPH10186401A - Thin film transistor array and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array that is suppressed in addition of a process and prevented in pressure resistance inferiority of an auxiliary capacitative element. SOLUTION: An amorphous silicon layer formed on an insulating layer 22, for example, ion a glass substrate 21 is irradiated with an excimer laser beam to crystalize the layer. Height of surface raggedness formed by crystallization is almost proportional to an average diameter of polycrystalline silicon crystals. By reducing the average diameter of the crystals in a lower electrode region 27 of the auxiliary capacitative element 45, raggedness in the lower electrode region 27 of the auxiliary capacitative element 45 becomes small and the pressure resistance inferiority of the auxiliary capacitive element 45 is rarely generated. As the polycrystalline silicon having the same average diameter as before is used for a channel region 24 of a thin film transistor 44, characteristics of the thin film transistor 44 such as mobility and threshold voltage are not influenced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor array having an auxiliary capacitance element and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, demands for downsizing and low power consumption of a display device using a liquid crystal have been increasing, and it has been required to integrate a driving circuit on a glass substrate. A method of manufacturing a thin film transistor which is a switching element using silicon is used.

Here, a conventional thin film transistor array having such a thin film transistor will be described with reference to FIGS.

[0004] First, as shown in FIG.
An insulating layer 2 of, for example, silicon oxide (SiO _x ) is formed thereon, and an amorphous silicon layer 3 having a thickness of 1000 Å is formed on the insulating layer 2.

Next, as shown in FIG. 11, the amorphous silicon layer 3 is irradiated with an excimer laser so that the average diameter of the amorphous silicon layer 3 is 0.3 mm.
A polycrystalline silicon layer 4 of about 5 μm is formed.

Further, as shown in FIG. 12, the polycrystalline silicon layer 4 is patterned to form a polycrystalline semiconductor layer 5.

Subsequently, as shown in FIG. 13, a gate insulating film 6 of silicon oxide is deposited and formed on the entire surface so as to cover the patterned polycrystalline semiconductor layer 5, and a metal gate electrode 7 and an auxiliary capacitance line 8 are formed. To form

[0008] Thereafter, as shown in FIG. 14, phosphorus (P) ions are doped from above the gate electrode 7 and the auxiliary capacitance wiring 8, and the channel layer 10 is formed below the gate electrode 7.
Is formed and polycrystallized adjacent to the channel layer 10 to form a source region 11 and a drain region 12.

Further, as shown in FIG. 15, an insulating layer 13 of silicon oxide is deposited and formed, an opening 14 is formed in the source region 11, and a source electrode 15 is formed.

Subsequently, as shown in FIG. 16, an insulating layer 16 of silicon oxide is formed, and an opening 17 is formed in the insulating layer 16.
A pixel electrode 18 is formed in the opening 17, and a thin film transistor array 19 is formed.

Here, the problem of the conventional thin film transistor array will be described.

An insulating layer 2 of silicon oxide is formed on a glass substrate 1 and an amorphous silicon layer 3 is irradiated with an excimer laser having a suitable energy to be crystallized, so that the average diameter of the crystal is present per unit area. If defined as the square root of the reciprocal of the number of single crystals, a polycrystalline silicon layer 4 having an average crystal diameter of about 0.5 μm is formed, and a polycrystalline semiconductor layer 5 is formed based on the polycrystalline silicon layer 4. .

However, in the polycrystalline semiconductor layer 5 formed by the above-described method, the thickness of the polycrystalline semiconductor layer 5 increases along the crystal boundary during the crystal growth process, and the surface of the polycrystalline semiconductor layer 5 extends along the crystal boundary. It has a shape with raised irregularities. The height of the bulge is about 1000 Å when the thickness of the polycrystalline semiconductor layer 5 is 1000 Å and the average crystal diameter is about 0.5 μm, for example. For this reason,
When the polycrystalline semiconductor layer 5 having such irregularities is used as a base, even if the gate insulating film 6 of silicon oxide is formed to have a thickness of 1000 Å by the CVD method, for example, the thickness of the side walls of the irregularities becomes small. The withstand voltage of the film 6 decreases.

In particular, when the polycrystalline semiconductor layer 5 having this uneven surface shape is used as the lower electrode of the auxiliary capacitor, the electrode area of the auxiliary capacitor is overwhelmingly larger than the channel layer 10 of the thin film transistor. On the other hand, while the gate breakdown voltage failure of the thin film transistor rarely occurs, the failure of the liquid crystal display panel due to the breakdown voltage failure of the auxiliary capacitance element predominantly occurs, and the image quality tends to be poor.

[0015]

As described above, in the conventional thin film transistor array, since the polycrystalline semiconductor layer 5 having the unevenness on the surface is used as the lower electrode of the auxiliary capacitance element, a breakdown voltage failure of the auxiliary capacitance element causes. There is a problem that a defect of the liquid crystal display panel may occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a thin film transistor array in which additional steps are suppressed and a withstand voltage failure of an auxiliary capacitance element is prevented, and a method for manufacturing the same.

[0017]

According to the present invention, a polycrystalline semiconductor layer is provided on an insulating substrate, and a gate electrode and an auxiliary capacitance element are provided on the polycrystalline semiconductor layer via a gate insulating film. The average diameter of the crystal in the polycrystalline semiconductor region located below the auxiliary capacitance line is smaller than the average diameter of the crystal in the polycrystalline semiconductor region located below the gate electrode. Then, by reducing the average diameter of the crystal of the polycrystalline semiconductor layer serving as the lower electrode of the auxiliary capacitance element, the irregularities of the polycrystalline semiconductor layer are reduced, and the withstand voltage failure of the auxiliary capacitance element is less likely to occur. Since the channel is made of polycrystalline silicon having a crystal having an average diameter of a conventional size, characteristics such as mobility and threshold voltage of the thin film transistor are not affected.

Further, the polycrystalline semiconductor layer has a semiconductor containing silicon as a main component, the gate insulating film has silicon oxide,
The thickness of the gate insulating film is D, and the crystal of the polycrystalline semiconductor region located below the auxiliary capacitance element defines the crystal diameter as the square root of the reciprocal of the number of single crystals existing per unit area,
When the average of the diameters of the crystals is L, L <2D. The reason is that the average grain size (L) of the polycrystalline silicon of the polycrystalline semiconductor layer having a thickness of 1,000 angstroms or less, which is a thickness that is practically used, and the height of irregularities on the surface of the polycrystalline silicon ( Z), Z <L /
In the case where a gate insulating film having a thickness (D) is placed on the polycrystalline semiconductor layer to form an auxiliary capacitance element, the height of the irregularities of the polycrystalline silicon in the polycrystalline semiconductor layer If the relationship of Z> D / 2 is established with (Z), a leakage current occurs in the auxiliary capacitance element. In this case, L> 2D
Is satisfied, and conversely, if L <2D, then the withstand voltage failure of the auxiliary capacitance element can be sufficiently suppressed.

Further, according to the present invention, an amorphous semiconductor is deposited on an insulating substrate to form an amorphous semiconductor layer, and the amorphous semiconductor layer is selectively doped with ions. The semiconductor layer is crystallized by irradiating a laser to form a polycrystalline semiconductor layer, a gate insulating film is formed on the polycrystalline semiconductor layer, a gate electrode is formed on the gate insulating film, and ions are doped. An auxiliary capacitance element is formed only above the polycrystalline semiconductor layer via the insulating film. Then, before crystallization of the amorphous semiconductor layer by laser irradiation, ions are doped to form a large number of defects at an interface between the amorphous semiconductor layer and the gate insulating film. To be at the core of growth,
At the time of crystallization by laser irradiation, a polycrystalline semiconductor layer of fine crystals is formed, the height of the irregularities on the surface of the polycrystalline semiconductor layer is reduced, and the breakdown voltage failure of the auxiliary capacitance element can be reduced without increasing the number of steps. This is unlikely to occur, and characteristics such as mobility and threshold voltage of the thin film transistor are not affected because polycrystalline silicon having a crystal having an average diameter of a conventional size is used for the channel of the gate electrode.

Further, according to the present invention, an amorphous semiconductor layer is formed by depositing an amorphous semiconductor on an insulating substrate, and at least one of implantation intensity and concentration is changed to form an auxiliary capacitance element on the upper portion. By doping the amorphous semiconductor layer with ions at a higher intensity or higher concentration than the region where the gate electrode is located at the top, and irradiating the amorphous semiconductor layer with a laser. The polycrystalline semiconductor layer is formed by crystallization, a gate insulating film is formed on the polycrystalline semiconductor layer, and a gate electrode and an auxiliary capacitance line are formed on the gate insulating film. Before irradiating the laser to crystallize the amorphous semiconductor layer, the region where the auxiliary capacitance element is located above has a higher intensity or a higher concentration than the region where the gate electrode is located above. At the interface between the amorphous semiconductor layer and the gate insulating film according to the intensity or concentration of ion doping, and these many defects become nuclei for crystal growth. In addition, a polycrystalline semiconductor layer of fine crystals is formed, the height of the irregularities on the surface of the polycrystalline semiconductor layer is reduced, and withstand voltage failure of the auxiliary capacitance element is less likely to occur without increasing the number of steps, and the gate electrode Since the polycrystalline silicon having a crystal having an average diameter of a conventional size is used for the channel, the characteristics such as the mobility and the threshold voltage of the thin film transistor are not affected.

Further, the amorphous semiconductor layer and the polycrystalline semiconductor layer have a semiconductor containing silicon as a main component, the gate insulating film has silicon oxide, and is injected into a region where the auxiliary capacitance element is located above. Ion doping intensity is 10 keV
The above and the doping concentration are 1 × 10 ¹³ cm ⁻² or more. Then, by doping ions with such intensity or concentration, the crystal at the position corresponding to the auxiliary capacitance element can be reliably reduced.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the thin film transistor array according to the present invention will be described below with reference to the drawings.

As shown in FIGS. 1 and 2, for example, silicon oxide (Si) is formed on a glass substrate 21 as an insulating substrate.
An insulating layer 22 of O _x ) and a polycrystalline semiconductor layer 23 are laminated, and the polycrystalline semiconductor layer 23 has a channel region 24, a source region 25, a drain region 26, and an average diameter of a polycrystalline silicon crystal from the channel region 24. Has a small lower electrode region 27.

A gate insulating film 31 is formed on the polycrystalline semiconductor layer 23 so as to cover the entire surface, and a gate wiring is formed on the gate insulating film 31 above the channel region 24 of the polycrystalline semiconductor layer 23. A metal gate electrode 32 also serving as a gate electrode is formed, and a metal auxiliary capacitance line 33 is similarly formed above the lower electrode region 27.

Further, an insulating layer 34 of silicon oxide is formed on the gate electrode 32 and the auxiliary capacitance wiring 33. An opening 35 is formed in the gate insulating film 31, an opening 36 communicating with the opening 35 of the gate insulating film 31 is formed in the insulating layer 34, and a source region is formed on the insulating layer 34 through the openings 35 and 36.
A source electrode 37 connected to 25 and also serving as a signal wiring is formed. An opening 38 is also formed on the drain region 26,
A drain electrode 39 connected to the drain region 26 via the opening 38 is formed.

Further, an insulating layer 41 of silicon oxide is formed on the insulating layer 34, an opening 42 is also formed in the insulating layer 41, and an ITO (Indium Titanium) is formed on the insulating layer 41 through the opening 42.
In Oxide) pixel electrode 43 is formed
44 and an auxiliary capacitance element 45 are formed to form a matrix array substrate 46.

A counter substrate having a counter electrode facing the pixel electrode 43 is opposed to the matrix array substrate 46, and liquid crystal is sealed between the counter substrate and the matrix array substrate 46, thereby forming a liquid crystal display device. You.

Next, the manufacturing process of the above embodiment will be described.

First, as shown in FIG. 3, an insulating layer 22 of, for example, silicon oxide (SiO _x ) is formed on a glass substrate 21, and an amorphous silicon layer 51 is formed on the insulating layer 22.

Next, as shown in FIG. 4, a partial region of the amorphous silicon layer 51 is covered with a photoresist 52,
Phosphorus (P) ions are implanted into a region not covered with the photoresist 52, that is, a lower electrode region 27 of the auxiliary capacitance element 45 by an ion doping method. The conditions for the implantation are an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁴ cm ⁻² .

After removing the photoresist 52,
As shown in FIG. 5, the amorphous silicon layer 51 is irradiated with an excimer laser to convert the amorphous silicon layer 51 into polycrystalline silicon layers 53 and 54. The polycrystalline silicon layer 53 is a region doped with phosphorus ions.

Further, as shown in FIG. 6, the polycrystalline silicon layers 53 and 54 are formed so as to form the channel region 24, the source region 25 and the drain region 26 of the thin film transistor 44, and the lower electrode region 27 of the auxiliary capacitance element 45. Pattern. The lower electrode region 27 of the auxiliary capacitance element 45 is formed in a region doped with phosphorus ions.

Subsequently, as shown in FIG. 7, a gate insulating film is formed on the entire surface so as to cover the patterned polysilicon layers 53 and 54.
A gate region 31 is formed on the gate insulating film 31.
A metal gate electrode 32 is formed on the lower electrode region 24, and a metal auxiliary capacitance line 33 is formed on the lower electrode region 27 in the same manner.

Thereafter, as shown in FIG.
The source region 25 and the drain region 26 are formed in the thin film transistor 44 from above, and are connected to the channel layer 24 to form two conductive regions.

Further, as shown in FIG. 9, an insulating layer 34 of silicon oxide is formed, openings 35 and 36 communicating with the gate insulating film 31 and the insulating layer 34 are provided, and then a source electrode 37 is formed.

Further, as shown in FIG. 1, an insulating layer 41 of silicon oxide is formed, an opening 42 is provided on the source electrode 37, and the pixel is brought into contact with the source electrode 37 via the opening 42 on the insulating layer 41. The electrodes 18 are formed, and the matrix array substrate 46 is formed.

According to the above embodiment, the auxiliary capacitance element 45
After the amorphous silicon layer 51 is doped with phosphorus ions and then crystallized by excimer laser irradiation, the lower electrode region 27 of the lower electrode region 27 Since many defects at the interface become the core of crystal growth,
The average diameter of the polycrystalline silicon in the lower electrode region 27 of the auxiliary capacitance element 45 is smaller than the average diameter of the polycrystalline silicon in the channel region 24 of the thin film transistor 44, and the height of the surface of the lower electrode region 27 is low. Therefore, for example, a thin film transistor array for a liquid crystal display panel can be formed without lowering the withstand voltage of the auxiliary capacitance element 45.

In the above embodiment, the ions to be implanted into a part of the amorphous silicon layer 51 are phosphorus (P). However, the ions are not limited to phosphorus, and boron (B), arsenic (As), and antimony ( Similar effects can be obtained with ions of other elements such as Sb).

Although ions are selectively doped in a part of the inclined region of the amorphous silicon layer 51, for example, doping ions of silicon oxide are added to a region of the amorphous silicon layer 51 where the thin film transistor 44 is formed. After forming a thin film that partially transmits, by doping ions, a low concentration doping is performed on a region where the thin film transistor 44 is formed, and a high concentration doping can be performed on the lower electrode region 27 of the auxiliary capacitance element 45. After removing the silicon oxide film used as this mask after doping,
By irradiating an excimer laser to crystallize the amorphous silicon layer 51, the irregularities on the surface of the polycrystalline silicon which becomes the lower electrode region 27 of the auxiliary capacitance element 45 are suppressed, and at the same time, the threshold of the thin film transistor 44 is reduced by the effect of impurity implantation. Voltage control is also possible.

Further, the lower electrode region 27 of the auxiliary capacitance element 45
Before irradiating an excimer laser, the amorphous silicon layer 51 forming the lower electrode region 27 of the auxiliary capacitance element 45 is doped with ions to suppress irregularities on the surface of the polycrystalline silicon in the lower electrode region 27. Although the average diameter is reduced, for example, on the glass substrate 21 below the lower electrode region 27 of the auxiliary capacitance element 45, or on the insulating film 22 formed on the glass substrate 21, the pattern is almost the same as that of the lower electrode region 27. By arranging a thin film having better thermal conductivity than silicon oxide or the like with an amorphous silicon layer 51 via an insulating layer or directly in contact with the amorphous silicon layer 51, the lower electrode region 27 can be irradiated with excimer laser. Since the heat is conducted and released, the growth of the crystal is slowed down, so that the average diameter of the crystal is reduced and the unevenness of the lower electrode region 27 can be reduced.

Further, by changing at least one of the intensity and the concentration of ion implantation, ions are implanted into the lower electrode region 27 with a higher intensity or a higher concentration than the channel region 24 to reduce the average diameter of the crystal. You may.

According to the above embodiment, the height of the irregularities on the surface formed by irradiating an excimer laser to the amorphous silicon layer 51 formed on the glass substrate 21, for example, on the insulating layer 22 and crystallizing the same, It is almost proportional to the average diameter of the polycrystalline silicon crystal. Therefore, by reducing the average diameter of the crystal of the lower electrode region 27 of the auxiliary capacitance element 45, the unevenness of the lower electrode region 27 of the auxiliary capacitance element 45 is reduced, and the withstand voltage failure of the auxiliary capacitance element 45 is less likely to occur. In addition, since polycrystalline silicon having the same average diameter as the conventional one is used for the channel region 24 of the thin film transistor 44, characteristics such as the mobility and the threshold voltage of the thin film transistor 44 are not affected.

According to an experiment, the average diameter (L) of the lower electrode region 27 is, if L <2D, relative to the film thickness (D) of the gate insulating film 31, if the auxiliary capacitance element 45 is used. Can be avoided. That is, the polycrystalline silicon layer 53,
In the case where the thickness of the film 54 is the maximum practical thickness of 1000 Å used for the thin film transistor 44, the average diameter (L) of the polycrystalline silicon and the height (Z) of the irregularities on the surface of the polycrystalline silicon are There is an approximate relationship of Z = L / 4, and in order to form the auxiliary capacitance element 45 on polycrystalline silicon without generating a leakage current in the gate insulating film 31 having the thickness (D), the lower electrode serving as a base is required. This is because a relationship of Z <D / 2 was observed between the height (Z) of the unevenness of the polycrystalline silicon in the region 27.

On the other hand, the thickness of the polycrystalline silicon actually used for the matrix array substrate 46 is less than 1000 Å, and is generally formed in a range of 500 Å to 800 Å.
In this case, the height of the irregularities on the surface of the polycrystalline silicon is smaller than when the thickness of the polycrystalline silicon is 1000 Å, and Z <L / 4. Therefore, also in this case, L <2D is a sufficient condition for avoiding the withstand voltage failure of the auxiliary capacitance element 45.

When the matrix array substrate 46 is used for a liquid crystal display panel, display failure due to a withstand voltage failure of the auxiliary capacitance element 45 can be prevented, and the image quality can be improved.

[0046]

According to the present invention, by reducing the average crystal diameter of the polycrystalline semiconductor layer serving as the lower electrode of the auxiliary capacitive element, the irregularities of the polycrystalline semiconductor layer are reduced, and the breakdown voltage of the auxiliary capacitive element is reduced. Is less likely to occur, and since polycrystalline silicon having a crystal of an average diameter of a conventional size is used for the channel of the gate electrode, it is possible to prevent the characteristics of the thin film transistor such as mobility and threshold voltage from being affected. .

An approximate relationship of Z = L / 4 is established between the average grain size (L) of the polycrystalline silicon of the polycrystalline semiconductor layer and the height (Z) of the irregularities on the surface of the polycrystalline silicon. In order to form an auxiliary capacitance element on a polycrystalline semiconductor layer without causing a gate insulating film having a thickness (D) to cause a leakage current, the height (Z) of the unevenness of the polycrystalline silicon of the polycrystalline semiconductor layer is required. Have a relationship of Z <D / 2 and a relationship of L <2D, it is possible to suppress the withstand voltage failure of the auxiliary capacitance element.

Further, prior to crystallization of the amorphous semiconductor layer by laser irradiation, ions are doped to form a large number of defects at the interface between the amorphous semiconductor layer and the gate insulating film. Since defects serve as nuclei for crystal growth, a microcrystalline polycrystalline semiconductor layer is formed during crystallization by laser irradiation, and the height of irregularities on the surface of the polycrystalline semiconductor layer is reduced, which increases the number of steps. Without causing a breakdown voltage failure of the auxiliary capacitance element, and using polycrystalline silicon having a crystal having an average diameter of a conventional size for the channel of the gate electrode, so that the mobility of the thin film transistor can be improved.
Influence on characteristics such as threshold voltage can be prevented.

Prior to crystallization of the amorphous semiconductor layer by irradiating a laser, the region where the auxiliary capacitance element is located above has a higher intensity and higher concentration than the region where the gate electrode is located above. In the interface between the amorphous semiconductor layer and the gate insulating film, defects are formed according to the intensity or concentration of the ion doping, and these many defects become nuclei for crystal growth. During crystallization, a microcrystalline polycrystalline semiconductor layer is formed,
The height of the irregularities on the surface of the polycrystalline semiconductor layer is reduced, the breakdown voltage of the auxiliary capacitance element is less likely to occur without increasing the number of steps, and a crystal having an average diameter of a conventional size is formed in the channel of the gate electrode. Since polycrystalline silicon is used, it is possible to prevent influence on characteristics such as mobility and threshold voltage of the thin film transistor.

Further, the ion doping intensity is set to 10 k
Since the doping concentration is not less than eV and the doping concentration is not less than 1 × 10 ¹³ cm ⁻² , the crystal at the position corresponding to the auxiliary capacitance element can be surely made small by doping ions with such intensity or concentration.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a thin film transistor array of the present invention.

FIG. 2 is a plan view of the thin film transistor array shown in FIG. 1;

FIG. 3 is a cross-sectional view showing one manufacturing process of the thin film transistor array.

FIG. 4 is a sectional view showing the next manufacturing step shown in FIG. 3 of the thin film transistor array.

FIG. 5 is a sectional view showing the next manufacturing step of the thin film transistor array shown in FIG. 4;

FIG. 6 is a cross-sectional view showing a next manufacturing step of the thin film transistor array shown in FIG. 5;

FIG. 7 is a cross-sectional view showing a next manufacturing step of the thin film transistor array shown in FIG. 6;

FIG. 8 is a cross-sectional view showing a next manufacturing step of the thin film transistor array shown in FIG. 7;

FIG. 9 is a sectional view showing the next manufacturing step of the thin film transistor array shown in FIG. 8;

FIG. 10 is a cross-sectional view showing one manufacturing process of a conventional thin film transistor array.

FIG. 11 is a sectional view showing the next manufacturing step shown in FIG. 10 of the thin film transistor array.

FIG. 12 is a cross-sectional view showing a next manufacturing step of the thin film transistor array shown in FIG. 11;

FIG. 13 is a cross-sectional view showing the next manufacturing step shown in FIG. 12 of the thin film transistor array.

FIG. 14 is a cross-sectional view showing the next manufacturing step shown in FIG. 13 of the thin film transistor array.

FIG. 15 is a cross-sectional view showing a next manufacturing step of the thin film transistor array shown in FIG. 14;

FIG. 16 is a sectional view showing the next manufacturing step shown in FIG. 15 for the thin film transistor array.

[Explanation of symbols]

 21 Glass substrate as insulating substrate 23 Polycrystalline semiconductor layer 31 Gate insulating film 32 Gate electrode 44 Thin film transistor 45 Auxiliary capacitance element

Claims (5)

[Claims] 1. A thin film transistor array in which a polycrystalline semiconductor layer is provided on an insulating substrate, and a gate electrode and an auxiliary capacitance element are provided on the polycrystalline semiconductor layer via a gate insulating film. The thin-film transistor array according to claim 1, wherein the average diameter of the crystal of the polycrystalline semiconductor region located below the element is smaller than the average diameter of the crystal of the polycrystalline semiconductor region located below the gate electrode. 2. A semiconductor device comprising: a polycrystalline semiconductor layer having a semiconductor containing silicon as a main component; a gate insulating film having silicon oxide; The crystal of the crystal semiconductor region is characterized in that, when the diameter of the crystal is defined as the square root of the reciprocal of the number of single crystals existing per unit area, and when the average diameter of the crystal is L, L <2D. The thin film transistor array according to claim 1. 3. An amorphous semiconductor is deposited on an insulating substrate to form an amorphous semiconductor layer, and the amorphous semiconductor layer is selectively doped with ions. To form a polycrystalline semiconductor layer, form a gate insulating film on the polycrystalline semiconductor layer, form a gate electrode on the gate insulating film, and dope ions with the polycrystalline semiconductor layer. A method for manufacturing a thin film transistor array, comprising forming an auxiliary capacitance element only above a layer via the insulating film. 4. An amorphous semiconductor layer is formed by depositing an amorphous semiconductor on an insulating substrate, and at least one of implantation intensity and concentration is changed to form a region where an auxiliary capacitance element is located above the semiconductor device. Is formed by doping the amorphous semiconductor layer with ions at a higher intensity or a higher concentration than the region where the gate element is located above, and crystallizing the amorphous semiconductor layer by irradiating the amorphous semiconductor layer with a laser. A method for manufacturing a thin film transistor array, comprising: forming a crystalline semiconductor layer; forming a gate insulating film on the polycrystalline semiconductor layer; and forming a gate electrode and an auxiliary capacitance wiring on the gate insulating film. 5. The amorphous semiconductor layer and the polycrystalline semiconductor layer have a semiconductor containing silicon as a main component, the gate insulating film has silicon oxide, and is implanted into a region where an auxiliary capacitance element is located above. 5. The method according to claim 3, wherein the ion doping intensity is 10 keV or more and the doping concentration is 1 × 10 ¹³ cm ⁻² or more.