JPH10105454A - Multi-port memory and display system provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-port memory whereby rotation display is easily executed and its display system. SOLUTION: The multi-port memory which transfers data stored in a RAM part to a SAM part by low address unit so as to output data is provided with a low address decoder 111 for designating plural continuous low addresses at every column address and a column address decoder 112 for designating plural continuous column addresses at every low address. The multi-port memory is also the one for outputting data transferred to the SAM part as serial data in a string direction or a row direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiport memory and a display system having the multiport memory, and more particularly to a rotation display of an image.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG.
It has a display address generation unit 803 for controlling the address of M802, and when the rotation display is instructed from the CPU 801, switching of the display address generation method by the display address generation unit 803 and bit order conversion of the display data by the display control unit 804. This enables display in a state in which the contents of the VRAM 802 are rotated by 180 degrees, and realizes high-speed rotation display as compared with a method of rewriting by software.

A multi-port RAM shown in FIG.
Is a 4-bit input / output port I / O3 for random access
0 to 4 bit output port Sou for serial access
t3 ~ 0 and a memory cell array for data storage (512 × 512 ×
4) 900, a row address decoder 901 for generating a row address of the memory cell array 900, a column address decoder 902 for generating a column address, and data from the memory cell array 900 via a transfer gate 907 in units of one row. Data register 908 for capturing the
SAM column address decoder to specify the address of
910 and a serial address counter that increments the SAM column address in synchronization with serial access
It has 911 and so on.

The memory cell array 900 has four layers of cell array blocks of 512 × 512 bits. In this multiport RAM, a memory cell array (512 × 512
× 4) Serial access to 900 is performed as follows.

First, a 9-bit row address is sent to a row address buffer 904 and supplied to a row decoder 901.
The data (512 × 4) of the memory cell on the selected row line in the four cell array layers of the memory cell array (512 × 512 × 4) 900 is transmitted through the transfer gate 907 having a four-layer structure to S.
The data is stored in a data register 908 which is a storage unit of the AM.

[0006] The data stored in the data register 908 is selected by the SAM column address decoder 910 for four bits, and the selected four bits are synchronized with the serial clock signal SC via the serial output buffer 912 for the serial output port 912. Output to Sout3 ~ 0. At this time, the serial address counter 911 is incremented, and the SAM column address decoder 911 selects 4-bit data of the next address. This operation enables the data in the data register 908 to be read continuously.

[0007]

In these prior art multiport memories, data on a row address of a RAM section is transferred to a data register of a SAM section, and the data is sequentially transmitted in one direction by a serial access from a display control section. In order to read the data, the normal display can be performed at a high speed, but in order to perform the rotation display, the data in the rotated state must be written when the data is written to the RAM unit by the CPU. Is heavy.
Further, as disclosed in JP-A-6-289848, when the rotation display is performed only by the address generation unit and the display control unit in the external display control device, even if the rotation by 180 degrees can be easily performed, the rotation of 90 degrees and 270 degrees is possible. Rotating display is difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiport memory which can solve the above problems and can easily perform a rotating display, and a display system therefor.

[0009]

According to the first aspect of the present invention, a row address decoder for designating a row address, a column address decoder for designating a column address, and data are stored in a randomly accessible RAM unit. With serializable memory cell array
The data stored in the RAM unit is stored in the M unit in the RAM unit.
A data register for storing data in a unit of row address, a transfer gate for transferring data from the memory cell array of the RAM unit to the data register of the SAM unit, a SAM unit row address decoder and a SAM unit for specifying an address of the data register. A column address decoder and S
By providing two serial address counters for incrementing the row address and the column address of the AM section by a clock signal, the address of the SAM section data register is specified in a plurality of continuous rows and a single column, or in a single row and a continuous plurality of columns. The above problem is solved by a configuration in which the data of the SAM section data register can be serially accessed in the column direction or the row direction.

According to a second aspect of the present invention, there is provided the multiport memory according to the first aspect, further comprising a function capable of incrementing and decrementing a count value from a start address designated by the SAM section row address counter and the SAM section column address counter. The above problem is solved by a configuration in which data in a data register is read out in an arbitrary order.

According to a third aspect of the present invention, in the multiport memory having the configuration of the first and second aspects, a circuit (address row-column conversion circuit) for replacing a row address and a column address in a random accessible RAM section is provided. The above problem is solved by a configuration that allows the arrangement of data to be written to be switched between rows and columns.

According to a fourth aspect of the present invention, there is provided a display device, the multi-port memory for storing data to be displayed on the display device, and a SAM of the multi-port memory synchronized with a screen scan on the display device. Read data from the
A display control device for performing display on the display device; and a central processing unit for controlling the display control device. The transfer from the RAM unit of the multiport memory to the SAM unit is performed by the RAM.
SAM is performed in the direction in which the row address is decremented.
Of multiple rows in which the address designation of the external data register is continuous
By using the AM section row address and the SAM section column address of one column, and using the two serial access clocks from the display control device, data is read out in a serial access manner in the direction of decrementing the SAM section column address from the start address. In order to solve the above-mentioned problem, a configuration that enables an image display on the display device to be rotated by 180 degrees is performed.

According to a fifth aspect of the present invention, in the display system according to the fourth aspect, when writing data to the RAM section of the multiport memory according to the third aspect, the RAM section row address and the R address are used.
The column address of the AM section is replaced by the address row-column conversion circuit of the RAM section, the transfer from the RAM section of the multiport memory to the SAM section is performed in the direction of decrementing the row address of the RAM section, The address is specified by the SAM section row address of one row and the SAM section column address of a plurality of continuous columns, and the SAM section row address is decremented from the start address by using two serial access clocks from the display control device. The above problem is solved by reading data in a serial access method in a direction in which is incremented by 1, thereby enabling image display on the display device to be performed by rotating 270 degrees clockwise.

According to a sixth aspect of the present invention, in the display system of the fourth aspect, when writing data to the RAM section of the multiport memory of the third aspect, the RAM section row address and R
The column address of the AM section is replaced by the address row-column conversion circuit of the RAM section, the transfer from the RAM section of the multiport memory to the SAM section is performed in the direction of incrementing the RAM section row address, The address is specified by the SAM section row address of one row and the SAM section column address of a plurality of continuous columns, and the display control device uses two serial access clocks,
By reading the data by the serial access method in the direction in which the SAM section row address is incremented from the start address and the SAM section column address is decremented, it is possible to rotate the image display on the display device 90 degrees clockwise. The above problem is solved by the configuration described above.

According to a seventh aspect of the present invention, a random access RAM section includes a row address decoder for designating a row address, a column address decoder for designating a column address, and a memory cell array for storing data.
A first data register for storing data stored in the RAM unit in a row address unit of the RAM unit in a serially accessible SAM unit, and a column address unit of the RAM unit for storing data stored in the RAM unit in the RAM unit A second data register, a transfer gate for transferring data from the memory cell array of the RAM unit to the data register of the SAM unit, an address decoder for specifying an address of the data register, and an address by a serial access clock. A serial address counter for counting and a data register selection circuit for switching the selection of two data registers are provided, and the arrangement of the memory cells indicated by the column addresses of the RAM unit and the arrangement of the second data registers are easily changed. The above configuration can be rotated To resolve the problem.

According to an eighth aspect of the present invention, there is provided a display device, the multi-port memory for storing data to be displayed on the display device, and the SAM of the multi-port memory synchronized with a screen scan on the display device. Read data from the
A display control device for performing display on the display device; and a central processing unit for controlling the display control device. The first SAM portion data corresponding to the RAM portion row address in the data register selection circuit of the multiport memory. By selecting a register, the serial address counter is incremented and decremented by the serial access clock from the display control device in the previous period, thereby performing normal display and 180-degree rotation display of the image. By selecting the second SAM section data register corresponding to the column address, the serial address counter is incremented and decremented by the serial access clock from the display control device in the previous period, thereby rotating clockwise by 90 degrees and 270 degrees. Display To solve the above problems by the configuration that allows.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multiport memory according to the first, second, and third inventions. FIG. 2 is a block diagram of a display system using the multiport of FIG. FIGS. 5, 6, 7, and 8 show the data arrangement of the multi-port memory and the display state of the LCD when the rotating display is performed in the display system of FIG. 2, respectively. An 8 × 8 × 2 multiport memory and an 8 × 8 LCD are used. The LCD is sequentially scanned from the upper left to the lower right in the figure.

In FIG. 1, reference numeral 100 denotes a memory cell array for storing display data, 101 denotes a row address decoder in the RAM, and 102 denotes a column address decoder in the RAM. 1
03 is a sense amplifier and I / O bus, which is connected to the system data bus. 104 is an address row-column conversion circuit.
When a 90 ° and 270 ° rotation display is instructed clockwise, the row address and the column address of the RAM section are exchanged. A transfer gate 115 transfers data specified by the row address decoder 101 from the memory cell array 100 in the RAM unit to the SAM unit. 110 is a data register, which stores display data transferred by the transfer gate 115,
Outputs data by serial access. 111 is S
The AM section row address decoder 112 is a SAM section column address decoder, which can simultaneously designate addresses for a plurality of continuous rows and a plurality of columns. 113 is a serial address counter for the SAM section row address, and 114 is a serial address counter for the SAM section column address, which can increment and decrement from the start address, respectively.

In FIG. 2, reference numeral 200 denotes a central processing unit, 201 denotes a display control device, 202 denotes an LCD, and 203 denotes the multiport memory of FIG. 1, which has two serial address clock inputs.

In the display system shown in FIG. 2, when an image is displayed in a normal state, the data is arranged in the memory shown in FIG. The address row-column conversion circuit 104 does not function, and data is stored in the memory cell array 100 as shown in FIG. The data register 110 has a RAM section row address R0.
The data is transferred in the order from to R7. The SAM section row address decoder 111 constantly indicates two rows of addresses r0 and r1, and the SAM section column address decoder 112 indicates one column of addresses in the order of c0 to c3. Are output in 2-bit units in synchronization with the serial address clock 1 shown in FIG. The data is displayed on the LCD 2 by the display controller 201.
The normal display is performed by sequentially displaying 02.

When an image is displayed after being rotated by 180 degrees, the data is arranged in the memory shown in FIG. The address row-column conversion circuit 104 does not function, and the memory cell array 100 has the configuration shown in FIG.
The data is stored as shown in FIG. Data register 110
Are transferred in the order of the RAM section row addresses R7 to R0. SAM row address decoder 111 is 2
The row addresses r0 and r1 are continuously specified, and the SAM section column address decoder 112 changes the address of one column from c3 to c3.
By designating in the order of 0, the data transferred to the data register 110 is output in 2-bit units in synchronization with the serial address clock 1 shown in FIG. By displaying the data on the LCD 202 sequentially by the display control device 201, an image rotated by 180 degrees is displayed.

When an image is displayed in a state of being rotated 270 degrees clockwise, the data is arranged in the memory of FIG. The address row-column conversion circuit 104 interchanges the row address of the RAM section and the column address of the RAM section, and the data is stored in the memory cell array 100 as shown in FIG.
Data is transferred to the data register 110 in the order of the RAM section row addresses R3 to R0. The SAM section row address decoder 111 indicates the address r1 of one row,
Section column address decoder 112 outputs the address of two columns to c
By indicating in the order of 0, c1 to c6, c7,
The data designated by the SAM section row address r1 is output in 2-bit units in synchronization with the serial address clock 1 shown in FIG. Next, by inputting the serial address clock 2 shown in FIG. 1, the instruction of the SAM section row address is shifted to r0, and the column address decoder 11 is again sent.
2 designates two columns of addresses in the order of c0, c1 to c6, c7, so that the data designated by the SAM section row address r0 is output in 2-bit units in synchronization with the serial address clock 1 shown in FIG. Is done. The display control device 201 sequentially displays the data on the LCD 202 to display an image rotated 270 degrees clockwise.

When an image is displayed in a state rotated 90 degrees clockwise, the data is arranged in the memory of FIG. The address row-column conversion circuit 104 interchanges the RAM section row address and the RAM section column address, and the data is stored in the memory cell array 100 as shown in FIG. The data register 110 has RAM row addresses R0 to R
Data is transferred in the order of 3. The SAM section row address decoder 111 designates an address r0 of one row, and the SAM section column address decoder 112 designates an address of two columns as c7,
By instructing in the order of c6 to c1 and c0, SA
The data specified by the M section row address r0 is output in 2-bit units in synchronization with the serial address clock 1 shown in FIG. Next, the serial address clock 2 shown in FIG.
Is input, the instruction of the SAM section row address is shifted to r1, and again the column address decoder 112 designates the address of two columns in the order of c7, c6 to c1, c0, so that the SAM section row address r1 is changed to r1. The designated data is output in 2-bit units in synchronization with the serial address clock 1 shown in FIG. The data is sequentially displayed on the LCD 202 by the display control device 201 to display an image rotated clockwise by 90 degrees.

FIG. 3 is a block diagram of a multiport memory according to another embodiment of the present invention. FIG. 4 is a block diagram of a display system using the multiport of FIG. FIGS. 9, 10, 11, and 12 show the data arrangement of the multi-port memory and the display state of the LCD when the rotating display is performed in the display system of FIG. 4, respectively. An 8 × 8 × 2 multiport memory and an 8 × 8 LCD are used. The LCD is sequentially scanned from the upper left to the lower right in the figure.

In FIG. 3, reference numeral 300 denotes a memory cell array for storing display data, 301 denotes a row address decoder in the RAM, and 302 denotes a column address decoder in the RAM. Three
03 is connected to the system data bus by a sense amplifier and an I / O bus. A transfer gate 315 transfers data specified by the row address decoder 301 from the memory cell array 300 in the RAM unit to the SAM unit. A data register 310 stores display data transferred by the transfer gate 315 and outputs the data by serial access. 325
Is also a transfer gate, and the memory cell array 300 of the RAM section
To transfer the data specified by the column address decoder 302 to the SAM unit. Reference numeral 320 denotes a data register which is arranged so that display data transferred by the transfer gate 325 can be easily rotated and displayed, and outputs data by serial access. 312 is an address decoder for the data register 310, and 322 is an address decoder for the data register 320. Reference numeral 314 denotes a serial address counter for the SAM unit address decoders 312 and 322, which can increment and decrement from the start address, respectively. 330 is a data register selection circuit for selecting which of the two data registers 310 and 320 to use.

In FIG. 4, reference numeral 400 denotes a central processing unit, 401 denotes a display control device, 402 denotes an LCD, and 403 denotes the multiport memory of FIG. In the display system of FIG. 4, when displaying an image in a normal state, the data is arranged in the memory of FIG. Data is stored in the memory cell array 300 as shown in FIG. By the data register selection circuit 330,
The data register 310 is selected, and data is transferred to the data register 310 in the order of the RAM unit row addresses R0 to R7. When the SAM unit address decoder 312 designates the address in the order of c0 to c3, the data transferred to the data register 310 is output two bits at a time in synchronization with the serial address clock. Normal display is performed by sequentially displaying the data on the LCD 402 by the display control device 401.

When an image is displayed in a state rotated by 180 degrees, the data is arranged in the memory of FIG. Data is stored in the memory cell array 300 as shown in FIG.
The data register selection circuit 330 allows the data register 310
Is selected, and data is transferred to the data register 310 in the order of the RAM unit row addresses R7 to R0. SAM
When the external address decoder 312 designates the address in the order of c3 to c0, the data transferred to the data register 310 becomes 2-bi in synchronization with the serial address clock.
It is output every t. The data is sequentially displayed on the LCD 402 by the display control device 401 to display an image rotated by 180 degrees.

When an image is displayed in a state of being rotated 270 degrees clockwise, the data is arranged in the memory of FIG. Data is stored in the memory cell array 300 as shown in FIG. The data register 320 is selected by the data register selection circuit 330.
Data is transferred in the order of the section column addresses C3 to C0. The data transferred to the data register 320 is shown in FIG.
Are arranged as shown in FIG. SAM section address decoder 32
When 2 designates the address in the order of r0 to r7, the data transferred to the data register 320 is output in 2-bit units in synchronization with the serial address clock. By displaying the data sequentially on the LCD 402 by the display control device 401, an image rotated 270 degrees clockwise is displayed.

When an image is displayed in a state rotated 90 degrees clockwise, the data is arranged in the memory of FIG. Data is stored in the memory cell array 300 as shown in FIG. The data register 320 is selected by the data register selection circuit 330, and data is transferred to the data register 320 in the order of the RAM section column addresses C0 to C3. The data transferred to data register 320 is arranged as shown in FIG. SAM section address decoder 322
Designates the address in the order of r7 to r0, so that the data transferred to the data register 320 is output in 2-bit units in synchronization with the serial address clock. The data is sequentially displayed on the LCD 402 by the display control device 401 to display an image rotated clockwise by 90 degrees.

[0030]

According to the first aspect of the present invention, the serial access memory unit has a row address recorder for designating a plurality of continuous row addresses for each column address, and a plurality of continuous column addresses for a row address. Since a column address recorder to specify each time is provided, the image can be rotated in the multi-port memory, which has the effect of enabling high-speed rotation display compared to the method of rewriting the contents of the multi-port memory by software. is there.

According to the multiport memory of the second aspect, in the multiport memory of the first aspect, the row address or the column address is incremented or decremented from a start address. There is an effect that the data transferred to the section can be output as serial data in the column direction or the row direction.

According to the multiport memory of the third aspect, in the multiport memory of the second aspect, matrix conversion is performed when data is written to the random access memory section, so that data is stored in the random access memory section. There is an effect that matrix conversion can be automatically performed when data is written.

According to the display system of the present invention, when the image is rotated and displayed by 90 degrees, 180 degrees, and 270 degrees by the multiport memory according to the first to third aspects, software or the like is used. There is no need to write the data subjected to the rotation processing to the multi-port memory, and it is possible to realize a very high-speed rotation display.

According to the multiport memory of the present invention, when storing the column address data of the RAM section in the SAM section corresponding to the column address of the RAM section,
Since the data arrangement is rotated, there is an effect that the arrangement of the data necessary for the rotation display can be easily changed.

According to the multiport memory of the eighth aspect, in the multiport memory of the seventh aspect, data is transferred from the RAM section to a data register of the SAM section corresponding to a row address of the RAM section. Thus, normal display and 180-degree rotation display are performed on the display device, and data is transferred from the RAM unit to the data register of the SAM unit corresponding to the column address of the RAM unit. Since the rotation display is performed in degrees and 270 degrees, it is not necessary to write data that has been subjected to rotation processing by software or the like to the multiport memory, and there is an effect that a very high-speed rotation display can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiport memory according to an embodiment of the present invention.

FIG. 2 is a block diagram of a display system according to an embodiment of the present invention.

FIG. 3 is a block diagram of a multi-port memory according to another embodiment of the present invention.

FIG. 4 is a block diagram of a display system according to another embodiment of the present invention.

FIG. 5 is a data layout diagram of a multi-port memory during normal display in the display system of FIG. 2;

FIG. 6 is a data layout diagram of a multiport memory at the time of 180-degree rotation display in the display system of FIG. 2;

FIG. 7 shows a clockwise 270 in the display system of FIG. 2;
FIG. 7 is a data layout diagram of a multi-port memory at the time of rotation display.

8 is a data layout diagram of a multi-port memory at the time of clockwise rotation by 90 degrees in the display system of FIG. 2;

9 is a data layout diagram of a multi-port memory at the time of normal display in the display system of FIG. 4;

10 is a data layout diagram of a multiport memory at the time of 180-degree rotation display in the display system of FIG. 4;

FIG. 11 shows a clockwise rotation of 27 in the display system of FIG. 4;
FIG. 4 is a data layout diagram of a multiport memory at the time of 0-degree rotation display.

FIG. 12 shows a clockwise 90 rotation in the display system of FIG. 4;
FIG. 7 is a data layout diagram of a multi-port memory at the time of rotation display.

FIG. 13 is a block diagram of a display system according to the related art.

FIG. 14 is a block diagram of a conventional multiport memory.

[Explanation of symbols]

 100 memory cell array 101 RAM section row address decoder 102 RAM section column address decoder 103 sense amplifier and I / O bus 104 address row-column conversion circuit 110 data register 111 SAM section row address decoder 112 SAM section column address decoder 113 serial address counter 2 114 Serial address counter 1 115 Transfer gate 200 Central processing unit 201 Display control unit 202 LCD 203 Multi-port memory 300 Memory cell array 301 RAM unit row address decoder 302 RAM unit column address decoder 303 Sense amplifier and I / O bus 310 Data register 1 312 SAM section address decoder 1 314 Serial address counter 315 Transfer gate 1 320 Data register 2 322 SAM section address decoder 2 325 Transfer gate 2 330 Data register selection circuit 400 Central processing unit 401 Display Control device 402 LCD 403 Multi-port memory 800 Display control device 801 CPU 802 VRAM 803 Display address generation unit 804 Display control unit 805 LCD 900 Memory cell array 901 RAM unit row decoder 902 RAM unit column decoder 903 Sense amplifier and I / O bus 904 Row Address buffer 905 Column address buffer 906 I / O buffer 907 Transfer gate 908 Data register 909 SAM section output bus 910 SAM section column decoder 911 Serial address counter 912 Serial output buffer

Claims (8)

[Claims] 1. A multiport memory for transferring data stored in a random access memory unit to a serial access memory unit in row address units and outputting data, wherein a plurality of row addresses continuous to the serial access memory unit are provided. A row address recorder that specifies a plurality of continuous column addresses for each row address, and a column address recorder that specifies a plurality of continuous column addresses for each row address. A multiport memory characterized by outputting as data. 2. The row address recorder and the column address recorder each include an address counter, and the row address or the column address is transferred to the serial access memory unit in an arbitrary order by incrementing or decrementing from a start address. 2. The multiport memory according to claim 1, wherein the output data is output as serial data in a column direction or a row direction. 3. The random access memory unit according to claim 2, further comprising a matrix conversion circuit for exchanging a row address and a column address, and performing a matrix conversion when data is written to the random access memory unit. Multi-port memory. 4. A display device, the multi-port memory storing data to be displayed on the display device, and reading data from a serial memory unit of the multi-port memory in synchronization with a screen scan on the display device. A display control device for performing display on a display device, and a central processing device for controlling the display control device, wherein the central processing device transfers data from the random access memory unit of the multiport memory to the serial access memory unit. The row address of the random access memory unit is decremented, the display control device, the multi-port memory,
A plurality of consecutive row addresses of the serial access memory unit are designated for each column address, and a serial data output is performed by designating an address in a direction of decrementing a column address of the serial access memory unit from the start address. 4. A display system comprising a multi-port memory according to claim 1, wherein image display on the display device is performed by rotating the image by 180 degrees. 5. The multiport memory according to claim 1, wherein said matrix conversion is performed at the time of writing to a random access memory unit, and transfer from said random access memory unit to said serial access memory unit is performed by a row address of said random access memory unit. Is performed in the direction of decrement, and a plurality of continuous column addresses of the serial access memory unit are designated for each row address. The display control device decrements the row address of the serial access memory unit from the start address and increments the column address. 5. The display system according to claim 4, wherein an image obtained by rotating the display on the display device by 270 degrees is displayed by reading in a direction in which the display is performed. 6. 6. The matrix conversion is performed at the time of writing to the random access memory section of the multiport memory, and the transfer from the random access memory section to the serial access memory section of the multiport memory is performed by a row address of the random access memory section. Is performed in the direction of incrementing, and a plurality of continuous column addresses of the serial access memory unit are designated for each row address. The display control device increments the row address of the serial access memory unit from the start address and decrements the column address. 5. The display system according to claim 4, wherein an image obtained by rotating the display on the display device by 90 degrees can be displayed by reading in a direction in which the display is performed. 7. A randomly accessible RAM unit, and two serially accessible SAMs corresponding to a row address and a column address of the RAM unit, respectively.
When storing the column address data of the RAM unit in the SAM unit corresponding to the RAM unit column address,
A multi-port memory characterized by rotating data arrangement. 8. A display device, the multi-port memory storing data to be displayed on the display device, and reading data from the SAM section of the multi-port memory in synchronization with screen scanning on the display device. A display control device that performs display on a display device; and a central processing unit that controls the display control device, wherein the SAM unit stores data corresponding to a row address and a column address of the RAM unit from the RAM unit. A data register of the SAM unit corresponding to a row address of the RAM unit from the RAM unit to perform normal display and 180-degree rotation display on the display device; By transferring data to the data register of the SAM unit corresponding to the column address of the RAM unit, The display system provided with a multiport memory according to claim 7, wherein the display device performs rotation display by 90 degrees and 270 degrees.