JPH098617A - Delay control circuit - Google Patents

Abstract

PURPOSE: To provide stable DRAM access by preventing sensitivity from being lowered by delay time fluctuation caused by dispersion in environmental conditions such as power supply voltage or temperature or the like and processes. CONSTITUTION: This circuit is provided with a PLL circuit 1 for synchronizing the phases of external and internal clocks CK and CKi and outputting a control signal VL for this phase synchronization. Delay circuits 21-23 are respectively provided with (n), (p) and (q) pieces of serially connected delay unit elements 131 for varying delay time in response to the supply of the control signal VL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay control circuit, and more particularly to a delay control circuit for adjusting timing formed inside a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A delay control circuit of this type is, for example, a DR
RA using AM row address strobe (RAS)
It is used to adjust the timing of each signal in the signal read / write control (hereinafter referred to as RAS access) circuit by S access. In particular, the timing difference between the word activation signal and the sense amplifier activation signal corresponds to the time from when the word rises until the cell data is output on the digit line. If this timing difference is too large, the digit line The above cell data is sufficiently output, but RAS access becomes slow,
If it is too small, the sensing operation is started before the cell data is sufficiently output, so that the sensing sensitivity is lowered. Therefore, in order to provide the appropriate timing difference, a word control signal and a sense amplifier activation signal are generated by using a delay control circuit including a plurality of delay circuits and giving a predetermined delay to each RAS signal.

Referring to FIG. 6, which shows a block diagram of a conventional first delay control circuit applied to a DRAM RAS access circuit, the conventional first delay control circuit is connected in series and delay times Td1 and Td2 are provided. Delay circuits 210 and 220 which output signals u and v respectively in response to the supply of RAS signal inversion RAS (hereinafter referred to as RASB)
And a delay circuit 230 having a delay time Td3 and outputting a signal w in response to the supply of the signal RASB, and signals u and w.
And a NAND circuit 24 that outputs a word activation signal WA by performing a NAND operation and a NAND circuit 25 that outputs a sense amplifier (SA) activation signal SA by performing a NAND operation of signals v and w.

Next, the operation of the first conventional delay control circuit will be described with reference to FIG. 6 and FIG. 7A showing the operation time chart. First, the negative polarity RAS signal RASB is applied to the delay circuit 210. , 230, the delay circuits 210, 230 respectively output signals u, w obtained by delaying the falling front edge of the signal RASB by the delay times Td1, Td3, respectively. NAND circuit 24
Performs a NAND operation in response to the supply of these signals u and w, and outputs the word activation signal WA whose leading edge is delayed by the delay time Td1 from the leading edge of the signal RASB. In response to the supply of the word activation signal WA, a word signal generation circuit (not shown) generates the word signal W. Next, the delay circuit 220 outputs the signal v obtained by further delaying the signal u by the delay time Td2. The NAND circuit 25 performs a NAND operation in response to the supply of the signals v and w, and outputs the SA activation signal SA whose leading edge is delayed by the delay time Td2 from the leading edge of the signal WA. Then, a sense amplifier (not shown) is activated and the digit signal D and the inverted D (DB) are output on the complementary digit lines.

Next, the RAS is synchronized with the external clock CK.
Referring to FIG. 7B showing an operation time chart of the second conventional delay control circuit applied to the synchronous RAS access circuit for accessing, the above-mentioned conventional second delay control circuit of the conventional second delay control circuit is referred to. The difference from the delay control circuit of No. 1 is that the RAS signal RASB is generated in synchronization with the external clock CK, and the other circuit configuration and operation are the same as those of the conventional first delay control circuit described above.

Delay circuits 210, 220, which are important components of these conventional first and second delay control circuits,
The delay circuit 230 has the same configuration except that the delay time is different. For convenience of description, the delay circuit 210 will be described here.

Referring to FIG. 8A showing a block diagram of a general delay circuit 210, this delay circuit 210
Is provided with a delay unit element 211 composed of n inverters I1 and a capacitor C1 which are connected in cascade. The number n of the delay unit elements 211 changes according to the required delay time Td.

Referring to FIG. 8B, which is a circuit diagram showing the configuration of the delay unit element 211, the inverter I1 has a P
It is composed of a channel type MOS transistor P1 and an N channel type MOS transistor N1. The current capability of these MOS transistors changes due to variations in power supply voltage, temperature, process, and the like. Therefore, the delay unit element 2
The delay time of 11 is +
/ -20%, and eventually the delay time of the delay circuit 210 also changes.

In the conventional first delay control circuit,
A delay time Td2 from generation of the word activation signal WA to generation of the SA activation signal SA is set to 6 ns as a value for obtaining a certain degree of sense sensitivity. When designing the delay time Td2 so as not to be 6 ns or less, the delay of 6 ns is set when the delay is expected to be minimum, that is, when the power supply voltage is set to the maximum, the temperature is set to the minimum, and the process is set to the maximum speed level. Design to meet.

However, the delay circuit 21 having the above-mentioned structure
When a delay of 0 to 6 ns is designed, the delay is expected to be the maximum, that is, when the power supply voltage is set to the minimum, the temperature is set to the maximum, and the process is set to the minimum speed level, the power supply voltage, temperature, and process variations cause Delay is +/- 2
If it changes by 0%, this 6ns will increase by 40% to 8.4ns.
Therefore, the RAS access will be delayed by 2.4 ns.

Next, in the second conventional delay control circuit, the access to the DRAM is not completed for each external clock CK, but four cycles of the external clock correspond to the width of the signal RASB as shown in FIG. 7, for example. are doing. On the other hand, a DRAM for word activation signal WA, SA activation signal SA, etc.
The internal signal of is not synchronized with the external clock CK and is controlled by the internal delay circuits 210, 220 and 230. Delay times Td1 and Td2 controlled by them
Is irrelevant to the timing of the external clock CK, so that, for example, when the delay time Td2 is short and the sense sensitivity is poor, no matter how much the external clock CK is delayed, the sense sensitivity is not improved.

[0012]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the second delay control circuit, the delay circuit, which is a main component, uses the inverter composed of the MOS transistor as the unit delay element. Therefore, the current capability may be changed due to variations in environmental conditions such as power supply voltage and temperature and manufacturing process conditions. The setting delay time changes due to the change, and the RAS
There is a drawback in that the timing of access is changed to cause a decrease in sense sensitivity.

Further, in the second conventional synchronous delay control circuit, the delay time of the internal signals such as the word activation signal and the SA activation signal is not related to the timing of the external clock, so that the set delay time There is a drawback in that the decrease in sense sensitivity due to fluctuation cannot be corrected by adjusting the timing of the external clock signal.

[0014]

A delay control circuit according to the present invention comprises first and second delay circuits connected in series and having first and second delay times, respectively, an input signal and the first delay circuit. A first timing difference between the first signal passing through the circuit and a second timing difference between the first signal and the second signal passing through the first and second delay circuits are respectively defined as the second timing difference. In the delay control circuit for setting the first and second delay times, the first
Phase synchronization between the first frequency-divided signal obtained by frequency-dividing the clock of No. 1 with the first frequency-division ratio and the second frequency-divided signal obtained by frequency-dividing the internally generated second clock with the second frequency division ratio. And a clock phase synchronizing means for outputting the control signal for phase synchronization and each of the first and second delay circuits is connected in cascade for a first and a second number, respectively, to supply the control signal. It is configured to include a first delay unit element having a first unit delay time that changes the delay time in response.

[0015]

1 is a block diagram showing an embodiment of the present invention.
Referring to FIG. 3, the delay control circuit of the present embodiment shown in this figure is a PL that synchronizes the internal clock CKi with the external clock CK and outputs the control voltage VL of the VCO.
The L circuit 1 and the variable delay circuit 2 including the delay circuits 21 to 23 whose delay times are controlled in response to the supply of the control voltage VL are provided.

The PLL circuit 1 selectively outputs either the charge down pulse CD or the charge up pulse CU in response to the phase comparison result of the clocks CK and CKi, and the charge down pulse CD,
Control voltage V in response to supply of charge-up pulse CU
A charge pump 12 that generates L and a VCO 13 that generates a clock CKi whose frequency is controlled in response to the supply of the control voltage VL are provided.

The variable delay circuits 2 are connected in series, and each of them can be varied in response to the supply of the control signal VL.
RAS signal inversion RAS (hereinafter referred to as RAS) having d1 and Td2.
B) and the delay circuits 21 and 22 which output the signals a and b, respectively, and the signal RA which also has a variable set delay time Td3 in response to the supply of the control signal VL.
Delay circuit 2 that outputs signal c in response to the supply of SB
3, a NAND circuit 24 for performing a NAND operation of the signals a and c and outputting a word activation signal WA, and signals b and c
And a NAND circuit 25 for performing a NAND operation and outputting a sense amplifier (SA) activation signal SA.

Referring to FIG. 2, which is a circuit diagram showing the configuration of the delay circuits 21, 22, 23, the delay circuit 21,
Each of 22 and 23 comprises n, p, and q delay unit elements 131 connected in cascade. The delay unit element 131 is the same transistor P as the conventional one.
1, an inverter I1 composed of N1; a capacitor C1 having one end grounded; and an N-channel MOS transistor N2 for delay control inserted between the output end of the inverter I1 and the other end of the capacitor C1.

Next, referring to FIGS. 1 and 2 and FIG. 3 showing an operation time chart, the operation of the delay control circuit of this embodiment will be described. H. B. Bakoglu, Circuits, Interconnections, and Packaging For VLSI (Circuit, Intercon)
injections, and Packaging fo
r VLSI), pp. 358-360, Addison-Wesley, 1990 (reference 1).

Referring also to FIGS. 4A and 4B showing the operation time chart of the PLL circuit 1, if the internal clock CKi is delayed with respect to the external clock CK, the phase comparison circuit 11 is charged down. Output pulse CD,
The charge pump 12 lowers the voltage level of the control voltage VL of the VCO, raises the oscillation frequency of the VCO 13 and speeds up the cycle of the clock CKi. On the contrary, if the clock CKi is faster than the clock CK, the phase comparison circuit 11 outputs the charge-up pulse CU, the charge pump 12 raises the voltage level of the control voltage VL, lowers the oscillation frequency of the VCO 13, and decreases the cycle of the clock CKi. Slow down.

Referring to FIGS. 5A to 5C which are circuit diagrams of the respective constituent elements 11 to 13 of the PLL circuit 1, the phase comparison circuit 11 shown in FIG.
1, with charge-up and charge-down pulses C
Set the pulse width of U and CD. The switches 123 and 124 of the charge pump 12 shown in FIG. 4 (B) are pseudo, and show that the current source 121 connected to the power source and the control voltage VL are connected when the pulse CU is at the H level, for example. When the pulse CU is supplied, the current source 1 is added to the capacitor 125.
A current is supplied from 21, and the voltage level of the control voltage VL rises.

Referring to FIG. 5 (C), the VCO 13 has a common delay unit with m delay circuits 21 to 23 in which a first stage input terminal and a final stage output terminal connected in cascade are connected in a ring shape. It is configured to include the element 131.

In response to the increase in the voltage level of the control voltage VL, the conduction resistance of the transistor N2 of the VCO 13 decreases, and the influence of the capacitance C1 on the output of the inverter I1 becomes strong, and as a result, the delay of the delay unit element 131 is delayed. Becomes larger, the oscillation frequency of the VCO is lowered and the cycle of the clock CKi is delayed. When the pulse CD is supplied,
By the operation opposite to the above, the cycle of the clock CKi is shortened.

Since the VCO 13 and the delay unit element 131 of the delay circuits 21 to 23 are the same, as in the conventional case,
The number of delay unit elements 131 changes according to the required delay time Td. Further, the variable amount of the unit delay time by the control voltage VL is the same, and therefore, these VCO
13 and the delay amount of the delay circuits 21 to 23 as a whole are determined by the number m, n, p of cascade connection of the delay unit elements 131.
depends on q.

Assuming that the cycle of the external clock CK is T, the delay times Td1 and Td of the delay circuits 21 to 23 respectively.
d2 and Td3 are respectively Tn / m, Tp / m, T
q / m, which is constant regardless of changes in external conditions such as voltage and temperature or changes in the manufacturing process.

The time chart of this embodiment shown in FIG.
This is a case where the number m of the delay unit elements 131 of the VCO 13 is 5, and the numbers n, p, and q of the delay unit elements 131 of the delay circuits 21, 22, and 23 are 3, 3, and 6, respectively.

The overall operation will be described with reference to FIG. 2. As in the conventional case, the negative polarity RAS signal RASB generated in synchronization with the external clock CK is delayed by the delay circuit 21 ,.
23, each of the delay circuits 21 and 23 receives the divided signal RAS of the delay times Td1 and Td3, respectively.
The signals a and c delayed from the falling edge of B are output. NA
The ND circuit 24 performs a NAND operation in response to the supply of these signals a and c, and outputs the word activation signal WA whose leading edge is delayed by the delay time Td1 from the leading edge of the signal RASB. In response to the supply of the word activation signal WA, a word signal generation circuit (not shown) generates the word signal W. next,
The delay circuit 22 outputs the signal b which is obtained by further delaying the signal a by the delay time Td2. The NAND circuit 25 performs the NAND operation in response to the supply of the signals b and c, and outputs the SA activation signal SA whose leading edge is delayed by the delay time Td2 from the leading edge of the signal WA. Then, a sense amplifier (not shown) is activated and the digit signal D and the inverted D (DB) are output on the complementary digit lines.

As described above, the delay circuits 21 and 2 are responsive to the supply of the control voltage VL regardless of changes in the external environment.
The delay times Td1, Td2 and Td3 of 2 and 23 are respectively set to T · 3/5, T · 3/5 and T · 6/5.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, in the embodiment, the case where the VCO and the other delay circuit use the delay unit element of the same design has been described, but the current capacity of the inverter of the delay circuit is halved and the capacitance value is doubled with respect to the VCO. When the delay unit element is used, the amount of change in the delay time can be set to four times for the same control voltage, so that the number of elements of the delay circuit can be reduced to 1/4 as long as it does not depart from the gist of the present invention. Of course you can.

Further, instead of directly comparing the phases of the external clock and the VCO oscillation signal, that is, the internal clock, the VCO is generated by performing the phase comparison after frequency division by the frequency division ratios of A and B, respectively.
The oscillation cycle of B becomes A / B times that of the external clock, and the internal delay can also be made B / A times by utilizing this.

[0031]

As described above, the delay control circuit of the present invention is provided with the clock phase synchronizing means for performing the phase synchronization between the external clock and the internal clock and outputting the control signal for this phase synchronization. Since each of them is connected in cascade and provided with a delay unit element that varies the delay time in response to the supply of the control signal, the delay time is determined in accordance with the phase synchronization, that is, the external clock is used. The advantage is that a stable delay time can be obtained regardless of changes in external conditions or changes in the manufacturing process.

Further, when applied to the RAS access circuit of DRAM, there is an effect that a stable operation can be guaranteed because the timing variation of the RAS access, which is a factor of lowering the sensitivity of the sense, can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a delay control circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a delay circuit of FIG.

FIG. 3 is a time chart showing an example of the operation of the delay control circuit of this embodiment.

FIG. 4 is a time chart showing an example of the operation of the PLL circuit of FIG.

5 is a circuit diagram showing a configuration of each part of the PLL circuit of FIG.

FIG. 6 is a block diagram showing an example of a conventional first delay control circuit.

FIG. 7 is a time chart showing an example of operations of conventional first and second delay control circuits.

8 is a circuit diagram showing a configuration of a delay circuit of FIG.

[Explanation of symbols]

 1 PLL Circuit 2 Variable Delay Circuit 11 Phase Comparison Circuit 12 Charge Pump 13 VCO 111 Pulse Generation Circuit 21-23, 210, 220, 230 Delay Circuit 24, 25 NAND Circuit 131, 211 Delay Unit Element I1 Inverter C1 Capacitance N1, N2 P1 transistor

Claims (5)

[Claims] 1. A first and a second delay circuits connected in series, each having a first and a second delay time, respectively, and a first input signal and a first signal passed through the first delay circuit. Control for setting the first timing difference and the second timing difference between the first signal and the second signal that has passed through the first and second delay circuits to the first and second delay times, respectively. In the circuit, a first frequency-divided signal obtained by dividing a first clock supplied from the outside by a first frequency division ratio and a second clock generated internally by a second frequency division ratio are divided by a second frequency division ratio. Clock phase synchronization means for performing phase synchronization with the frequency-divided signal of 2 and outputting a control signal for this phase synchronization, wherein each of the first and second delay circuits is provided with a first and second number, respectively. Are connected in cascade and respond to the supply of the control signal. Delay control circuit further comprising a first first unit delay time of the delay unit element for varying the delay time by. 2. The clock phase synchronization means delays in response to a supply of a third number of the control signals, which is a ring connection in which a first-stage input terminal and a last-stage output terminal connected in cascade are connected. A second delay unit element having a second unit delay time for varying the time; a voltage controlled oscillator circuit for varying the frequency of the second divided signal in response to the supply of the control signal; And a phase comparison circuit for selectively outputting a positive direction and a negative direction charge pulse signal for instructing charge of either positive polarity or negative polarity according to the result of phase comparison with the second divided signal clock. The delay control circuit according to claim 1, further comprising a PLL circuit including a charge pump circuit that generates the control signal in response to the supply of the charge pulse signal. 3. The first and second unit delay circuits,
An inverter composed of first and second transistors, a variable resistor for varying a conduction resistance in response to the supply of the control signal and a capacitor connected in series between the output terminal of the inverter and the first or second power supply. 3. The delay control circuit according to claim 1, further comprising an element. 4. The delay control circuit according to claim 1, wherein the first and second frequency division ratios are both 1, and the first and second unit delay times are equal to each other. 5. The delay control circuit according to claim 3, wherein the variable resistance element is a MOS transistor having a gate supplied with the control voltage.