JPH0936143A - Semiconductor device, its manufacture and mounting - Google Patents
Semiconductor device, its manufacture and mountingInfo
- Publication number
- JPH0936143A JPH0936143A JP20511495A JP20511495A JPH0936143A JP H0936143 A JPH0936143 A JP H0936143A JP 20511495 A JP20511495 A JP 20511495A JP 20511495 A JP20511495 A JP 20511495A JP H0936143 A JPH0936143 A JP H0936143A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- anisotropic conductive
- conductive adhesive
- semiconductor chip
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置および
その製造方法並びにその実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a manufacturing method thereof, and a mounting method thereof.
【０００２】[0002]
【従来の技術】例えば液晶表示素子において、ＣＯＧ
（Chip on Glass）方式とよばれる半導体装置（突起電
極を有する半導体チップ）の実装技術では、図９に示す
ように、半導体チップ１の下面に設けられた突起電極２
を液晶表示素子のガラス等からなる透明基板３の上面に
設けられた接続端子４に異方導電性接着剤５を介して導
電接続することにより、半導体チップ１を透明基板３上
に実装することがある。この場合、異方導電性接着剤５
は、絶縁性接着剤６中に導電性粒子７を適度な密度で混
入したものからなっている。2. Description of the Related Art For example, in a liquid crystal display device, COG
In a mounting technique of a semiconductor device (semiconductor chip having a protruding electrode) called a (Chip on Glass) method, as shown in FIG. 9, the protruding electrode 2 provided on the lower surface of the semiconductor chip 1 is used.
The semiconductor chip 1 is mounted on the transparent substrate 3 by conductively connecting to the connection terminals 4 provided on the upper surface of the transparent substrate 3 made of glass or the like of the liquid crystal display element via the anisotropic conductive adhesive 5. There is. In this case, the anisotropic conductive adhesive 5
Is composed of an insulating adhesive 6 in which conductive particles 7 are mixed at an appropriate density.
【０００３】従来のこのような半導体装置の実装方法に
ついてさらに詳述すると、まず図１０に示すように、透
明基板３の接続端子４を含む接続部分の上面にシート状
の異方導電性接着剤５を仮熱圧着し、このシート状の異
方導電性接着剤５の上面に半導体チップ１の突起電極２
を含む接続部分を位置合わせして載置する。次に、本熱
圧着した後、ポストベークを行うことにより、図９に示
すように、透明基板３の接続端子４と半導体チップ１の
突起電極２とを異方導電性接着剤５の導電性粒子７を介
して導電接続するとともに、半導体チップ１を透明基板
３上に異方導電性接着剤５の絶縁性接着剤６を介して接
着している。The conventional mounting method of such a semiconductor device will be described in more detail. First, as shown in FIG. 10, a sheet-like anisotropic conductive adhesive is formed on the upper surface of the connection portion of the transparent substrate 3 including the connection terminals 4. 5 is tentatively thermocompression bonded, and the protruding electrode 2 of the semiconductor chip 1 is attached to the upper surface of this sheet-shaped anisotropic conductive adhesive 5.
The connection part including is aligned and placed. Next, after the main thermocompression bonding, post-baking is performed to connect the connecting terminals 4 of the transparent substrate 3 and the protruding electrodes 2 of the semiconductor chip 1 with the anisotropic conductive adhesive 5 as shown in FIG. The semiconductor chip 1 is bonded to the transparent substrate 3 via the insulating adhesive 6 of the anisotropic conductive adhesive 5 while being electrically connected via the particles 7.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置の実装方法では、長尺な異方導電
性接着剤ベースシートを切断して得られたシート状の異
方導電性接着剤５を透明基板３の接続端子４を含む接続
部分毎に仮熱圧着することになるので、実装工程数が多
いという問題があった。また、図１１に示すように、本
熱圧着したとき、半導体チップ１の下面と異方導電性接
着剤５との間に局部的に空気８が取り残されることがあ
り、このような現象が生じた場合には、異方導電性接着
剤５の接合力が低下するという問題があった。この発明
の課題は、実装工程数を少なくすることができ、また異
方導電性接着剤の接合力が低下しないようにすることが
できるようにすることである。However, according to the conventional method for mounting a semiconductor device as described above, a sheet-shaped anisotropic conductive adhesive obtained by cutting a long anisotropic conductive adhesive base sheet is used. Since 5 is temporarily thermocompression bonded for each connection portion including the connection terminal 4 of the transparent substrate 3, there is a problem that the number of mounting steps is large. Further, as shown in FIG. 11, when the main thermocompression bonding is performed, air 8 may be left locally between the lower surface of the semiconductor chip 1 and the anisotropic conductive adhesive 5, and such a phenomenon may occur. In that case, there is a problem that the bonding force of the anisotropic conductive adhesive 5 is reduced. An object of the present invention is to reduce the number of mounting steps and prevent the bonding force of the anisotropic conductive adhesive from decreasing.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明に係
る半導体装置は、半導体チップと、この半導体チップの
一の面に設けられた突起電極と、前記半導体チップの一
の面に前記突起電極を覆うように設けられた異方導電性
接着剤層とを具備したものである。請求項４記載の発明
に係る半導体装置の製造方法は、一の面に突起電極が設
けられたウエハの一の面にスピンコートにより異方導電
性接着剤層を前記突起電極を覆うように形成し、次いで
前記ウエハを切断して個々のチップに分割するようにし
たものである。請求項７記載の発明に係る半導体装置の
実装方法は、半導体チップとこの半導体チップの一の面
に設けられた突起電極と前記半導体チップの一の面に前
記突起電極を覆うように設けられた異方導電性接着剤層
とからなる半導体装置を基板上に載置し、熱圧着するこ
とにより前記半導体チップを前記異方導電性接着剤層を
介して前記基板上に実装するようにしたものである。According to a first aspect of the present invention, there is provided a semiconductor device, a semiconductor chip, a projection electrode provided on one surface of the semiconductor chip, and the projection on the one surface of the semiconductor chip. And an anisotropic conductive adhesive layer provided so as to cover the electrodes. According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an anisotropic conductive adhesive layer is formed on one surface of a wafer having a protruding electrode on one surface by spin coating so as to cover the protruding electrode. Then, the wafer is cut and divided into individual chips. According to a seventh aspect of the present invention, there is provided a semiconductor device mounting method, wherein a semiconductor chip, a bump electrode provided on one surface of the semiconductor chip, and a bump electrode provided on the one surface of the semiconductor chip so as to cover the bump electrode. A semiconductor device comprising an anisotropic conductive adhesive layer is placed on a substrate and thermocompression bonded to mount the semiconductor chip on the substrate via the anisotropic conductive adhesive layer. Is.
【０００６】請求項４記載の発明によれば、ウエハの一
の面にスピンコートにより異方導電性接着剤層を突起電
極を覆うように形成し、次いでウエハを切断して個々の
チップに分割しているので、請求項１記載の発明のよう
に、異方導電性接着剤層を予め備えた半導体装置を得る
ことができる。この結果、請求項７記載の発明のよう
に、異方導電性接着剤層を備えた半導体装置を基板上に
載置すればよく、したがって従来のようにシート状の異
方導電性接着剤を基板上に仮熱圧着する必要がなく、実
装工程数を少なくすることができる。また、請求項４記
載の発明によれば、ウエハの一の面にスピンコートによ
り異方導電性接着剤層を突起電極を覆うように形成して
いるので、半導体チップと異方導電性接着剤層との間に
空気が取り残されないようにすることができ、したがっ
て異方導電性接着剤の接合力が低下しないようにするこ
とができる。According to the fourth aspect of the present invention, an anisotropic conductive adhesive layer is formed on one surface of the wafer by spin coating so as to cover the protruding electrodes, and then the wafer is cut into individual chips. Therefore, as in the invention described in claim 1, it is possible to obtain a semiconductor device having an anisotropic conductive adhesive layer in advance. As a result, the semiconductor device provided with the anisotropic conductive adhesive layer may be placed on the substrate as in the invention according to claim 7, and therefore, the sheet-shaped anisotropic conductive adhesive as in the conventional case is used. Since it is not necessary to perform temporary thermocompression bonding on the substrate, the number of mounting steps can be reduced. Further, according to the invention of claim 4, since the anisotropic conductive adhesive layer is formed on one surface of the wafer by spin coating so as to cover the protruding electrodes, the semiconductor chip and the anisotropic conductive adhesive are formed. It is possible to prevent air from being left behind between the layers and thus to prevent the bonding force of the anisotropic conductive adhesive from being deteriorated.
【０００７】[0007]
【発明の実施の形態】図１〜図５はそれぞれこの発明の
第１実施形態における半導体装置の各製造工程を示した
ものである。そこで、これらの図を順に参照しながら、
この実施形態における半導体装置の構造についてその製
造方法と併せて説明する。1 to 5 show respective manufacturing steps of a semiconductor device according to a first embodiment of the present invention. So, referring to these figures in order,
The structure of the semiconductor device according to this embodiment will be described together with its manufacturing method.
【０００８】まず、図１に示すように、ウエハ１１上に
複数の突起電極１２が形成されたものを用意する。この
場合、ウエハ１１上の格子状の線はウエハ１１をダイシ
ングして個々のチップに分割するときのダイシングスト
リート１３を示している。突起電極１２は、高さ２０〜
１００μｍ程度の金や銅等の金属突起からなり、各チッ
プの外周部に対応する位置に配列して設けられている。
次に、ディスペンサ１４を用いて感光性ポリイミド等か
らなるショート防止壁形成用材料１５をウエハ１１の上
面中央部に滴下し、次いでウエハ１１を高速回転させる
と、図２に示すように、ウエハ１１の上面にショート防
止壁形成用層１６が突起電極１２の上部が露出するよう
に形成される。次に、図示しない所定のマスクを用いて
露光し、次いで現像して、ショート防止壁形成用層１６
の不要な部分を除去することにより、図３に示すよう
に、各チップの突起電極１２の配列部の外側の部分に、
つまり各チップの突起電極１２とダイシングストリート
１３との間に枠状のショート防止壁１７を形成する。First, as shown in FIG. 1, a wafer 11 having a plurality of protruding electrodes 12 formed thereon is prepared. In this case, the grid lines on the wafer 11 indicate the dicing streets 13 when the wafer 11 is diced and divided into individual chips. The protruding electrode 12 has a height of 20 to
The projections are made of metal projections of about 100 μm, such as gold and copper, and are arranged at positions corresponding to the outer peripheral portion of each chip.
Next, a short-circuit prevention wall forming material 15 made of photosensitive polyimide or the like is dropped on the central portion of the upper surface of the wafer 11 using the dispenser 14, and then the wafer 11 is rotated at a high speed, as shown in FIG. A short-circuit preventing wall forming layer 16 is formed on the upper surface of the so as to expose the upper portion of the protruding electrode 12. Next, the layer 16 for short-circuit prevention wall formation is exposed by using a predetermined mask (not shown) and then developed.
By removing the unnecessary portion of, as shown in FIG. 3, in the portion outside the array portion of the protruding electrodes 12 of each chip,
That is, the frame-shaped short-circuit prevention wall 17 is formed between the protruding electrode 12 and the dicing street 13 of each chip.
【０００９】次に、図示しないディスペンサを用いて溶
剤を含有する液状の異方導電性接着剤をウエハ１１の上
面中央部に滴下し、次いでウエハ１１を高速回転させ、
次いで溶剤を蒸発させて乾燥させると、図４に示すよう
に、ウエハ１１の上面に異方導電性接着剤層１８が突起
電極１２およびショート防止壁１７を覆うように形成さ
れる。この場合、異方導電性接着剤層１８は、絶縁性接
着剤１９中に絶縁性樹脂膜（図示せず）で表面が被覆さ
れた導電性粒子２０を適度な密度で混入したものからな
っている。このうち絶縁性接着剤１９は熱可塑性樹脂、
熱硬化性樹脂あるいは両者の混合物からなっている。導
電性粒子２０は金、銀、銅、鉄、ニッケル、アルミニウ
ム等の金属粒子、有機共役系高分子等の導電性高分子粒
子、あるいは樹脂粒子の表面にニッケルメッキ等からな
る金属被膜を被覆したものからなっている。導電性粒子
２０の表面に被覆された絶縁性樹脂膜は熱可塑性樹脂等
からなっている。Next, using a dispenser (not shown), a liquid anisotropic conductive adhesive containing a solvent is dropped onto the central portion of the upper surface of the wafer 11, and then the wafer 11 is rotated at a high speed.
Next, when the solvent is evaporated and dried, an anisotropic conductive adhesive layer 18 is formed on the upper surface of the wafer 11 so as to cover the bump electrodes 12 and the short-circuit prevention wall 17, as shown in FIG. In this case, the anisotropic conductive adhesive layer 18 is formed by mixing the conductive adhesive particles 20 whose surface is coated with an insulating resin film (not shown) in an insulating adhesive agent 19 at an appropriate density. There is. Of these, the insulating adhesive 19 is a thermoplastic resin,
It consists of a thermosetting resin or a mixture of both. The conductive particles 20 are metal particles of gold, silver, copper, iron, nickel, aluminum, etc., conductive polymer particles of organic conjugated polymer, etc., or resin particles whose surfaces are coated with a metal coating such as nickel plating. It consists of things. The insulating resin film coated on the surface of the conductive particles 20 is made of a thermoplastic resin or the like.
【００１０】このように、ウエハ１１の上面にスピンコ
ートにより異方導電性接着剤層１８を突起電極１２を覆
うように形成しているので、ウエハ１１の状態における
チップと異方導電性接着剤層１８との間に空気が取り残
されないようにすることができ、またウエハ１１の状態
における全てのチップの上面に一度に異方導電性接着剤
層１８を形成することができ、異方導電性接着剤層１８
を備えたチップを短時間で形成することができる。As described above, since the anisotropic conductive adhesive layer 18 is formed on the upper surface of the wafer 11 by spin coating so as to cover the protruding electrodes 12, the chips in the state of the wafer 11 and the anisotropic conductive adhesive are formed. Air can be prevented from being left behind with the layer 18, and the anisotropic conductive adhesive layer 18 can be formed on the upper surfaces of all the chips in the state of the wafer 11 at one time. Adhesive layer 18
Can be formed in a short time.
【００１１】次に、ウエハ１１上の異方導電性接着剤層
１８のみをダイシングストリート１３に沿って接着剤層
切断用のダイシングブレード（図示せず）によってダイ
シングし、次いでウエハ１１をダイシングストリート１
３に沿ってダイヤモンドブレード等のウエハ切断用のダ
イシングブレード（図示せず）によってダイシングして
切断し、個々のチップに分割すると、図５に示すよう
に、個々のチップからなる半導体装置２１が得られる。
この場合、２回に分けてダイシングするのは、ウエハ切
断用のダイシングブレードの劣化を防止するためであ
る。ところで、異方導電性接着剤層１８を接着剤層切断
用のダイシングブレードによってダイシングする際に、
ダイシングストリート１３に位置する導電性粒子２０が
突起電極１２の近傍に移動し、隣接する突起電極１２の
間でショートが生じることがある。しかしながら、突起
電極１２の外側にはショート防止壁１７が設けられてい
るので、ダイシングストリート１３に位置する導電性粒
子２０が突起電極１２の近傍に移動することがなく、突
起電極１２間がショートしないようにすることができ
る。Next, only the anisotropic conductive adhesive layer 18 on the wafer 11 is diced along the dicing streets 13 by a dicing blade (not shown) for cutting the adhesive layer, and then the wafer 11 is diced.
3 is diced and cut by a dicing blade (not shown) such as a diamond blade for cutting a wafer along 3 and divided into individual chips, as shown in FIG. 5, a semiconductor device 21 including individual chips is obtained. To be
In this case, the dicing is performed twice in order to prevent deterioration of the dicing blade for cutting the wafer. By the way, when dicing the anisotropic conductive adhesive layer 18 with a dicing blade for cutting the adhesive layer,
The conductive particles 20 located on the dicing streets 13 may move to the vicinity of the protruding electrodes 12, and a short circuit may occur between the adjacent protruding electrodes 12. However, since the short-circuit prevention wall 17 is provided outside the protruding electrodes 12, the conductive particles 20 located on the dicing streets 13 do not move to the vicinity of the protruding electrodes 12, and the protruding electrodes 12 are not short-circuited. You can
【００１２】このようにして得られた半導体装置２１で
は、半導体チップ２２の上面の外周部に突起電極１２が
配列して設けられ、半導体チップ２２の上面の突起電極
１２の配列部の外側の部分にショート防止壁１７がその
高さを突起電極１２の高さよりも低くされて設けられ、
半導体チップ２２の上面に異方導電性接着剤層１８が突
起電極１２およびショート防止壁１７を覆うように設け
られた構造となっている。この場合、異方導電性接着剤
層１８が外周雰囲気からの汚染や破損から半導体チップ
２２の上面（突起電極形成面）を十分に保護することが
できる。In the semiconductor device 21 thus obtained, the protruding electrodes 12 are provided in an array on the outer peripheral portion of the upper surface of the semiconductor chip 22, and the portion outside the array portion of the protruding electrodes 12 on the upper surface of the semiconductor chip 22 is provided. In addition, the short-circuit prevention wall 17 is provided so that its height is lower than that of the protruding electrode 12,
An anisotropic conductive adhesive layer 18 is provided on the upper surface of the semiconductor chip 22 so as to cover the protruding electrodes 12 and the short-circuit prevention wall 17. In this case, the anisotropic conductive adhesive layer 18 can sufficiently protect the upper surface (projection electrode formation surface) of the semiconductor chip 22 from contamination or damage from the outer atmosphere.
【００１３】次に、図６および図７は半導体装置２１を
液晶表示素子のガラス等からなる透明基板２３上に実装
する工程を示したものである。この実装方法では、まず
図６に示すように、透明基板２３の接続端子２４を含む
接続部分の上面に半導体装置２１の異方導電性接着剤層
１８を位置合わせして載置する。次に、熱圧着すると、
導電性粒子２０の表面に被覆されている絶縁性樹脂膜お
よび導電性粒子２０相互間に介在されている絶縁性接着
剤１９が溶融し、それらの一部が流動して逃げることに
より、図７に示すように、異方導電性接着剤層１８の導
電性粒子２０の一部が相対向する半導体チップ２２の突
起電極１２と透明基板２３の接続端子２４に共に接触
し、これにより相対向する突起電極１２と接続端子２４
とが導電接続される。この場合、導電接続に関与しない
導電性粒子２０の表面には絶縁性樹脂膜がそのまま被覆
されていることにより、絶縁性が維持されている。ま
た、導電性粒子２０相互間に介在されている絶縁性接着
剤１９が固化することにより、半導体チップ２２が透明
基板２３上に接着される。なお、ショート防止壁１７は
その厚さを突起電極１２の高さよりも低くされて形成さ
れているので、突起電極１２を透明基板２３の接続端子
２４に良好に導電接続することができる。Next, FIGS. 6 and 7 show steps of mounting the semiconductor device 21 on a transparent substrate 23 made of glass or the like of a liquid crystal display element. In this mounting method, first, as shown in FIG. 6, the anisotropic conductive adhesive layer 18 of the semiconductor device 21 is aligned and placed on the upper surface of the connection portion including the connection terminals 24 of the transparent substrate 23. Next, when thermocompression bonding,
The insulating resin film coated on the surface of the conductive particles 20 and the insulating adhesive 19 interposed between the conductive particles 20 are melted, and a part of them melts and escapes. As shown in FIG. 5, a part of the conductive particles 20 of the anisotropic conductive adhesive layer 18 both come into contact with the protruding electrodes 12 of the semiconductor chip 22 and the connection terminals 24 of the transparent substrate 23 which face each other, and thereby face each other. Projection electrode 12 and connection terminal 24
And are conductively connected. In this case, the surface of the conductive particles 20 not involved in the conductive connection is covered with the insulating resin film as it is, so that the insulating property is maintained. Further, the semiconductor chip 22 is bonded onto the transparent substrate 23 by solidifying the insulating adhesive 19 interposed between the conductive particles 20. Since the short-circuit prevention wall 17 is formed so that its thickness is lower than the height of the protruding electrode 12, the protruding electrode 12 can be satisfactorily conductively connected to the connection terminal 24 of the transparent substrate 23.
【００１４】このように、この半導体装置の実装方法で
は、異方導電性接着剤層１８を予め備えた半導体装置２
１を透明基板２３上に載置して熱圧着すればよいので、
図１０に示す従来のようなシート状の異方導電性接着剤
５を透明基板３上に仮熱圧着する必要がなく、したがっ
て実装工程数を少なくすることができる。また、既に説
明したように、ウエハ１１の上面にスピンコートにより
異方導電性接着剤層１８を突起電極１２を覆うように形
成することにより、半導体チップ２２と異方導電性接着
剤層１８との間に空気が取り残されないようにすること
ができるので、異方導電性接着剤の接合力が低下しない
ようにすることができる。As described above, in this semiconductor device mounting method, the semiconductor device 2 having the anisotropic conductive adhesive layer 18 in advance is provided.
Since 1 may be placed on the transparent substrate 23 and thermocompression bonded,
Since it is not necessary to temporarily thermocompress the sheet-shaped anisotropic conductive adhesive 5 shown in FIG. 10 on the transparent substrate 3, the number of mounting steps can be reduced. Further, as described above, the anisotropic conductive adhesive layer 18 is formed on the upper surface of the wafer 11 by spin coating so as to cover the protruding electrodes 12, thereby forming the semiconductor chip 22 and the anisotropic conductive adhesive layer 18. Since it is possible to prevent air from being left behind during this period, it is possible to prevent the bonding force of the anisotropic conductive adhesive from decreasing.
【００１５】図８はこの発明の第２実施形態における半
導体装置を示したものである。この半導体装置では、半
導体チップ２２の上面の突起電極１２の配列部の内側の
部分にショート防止壁１７と同一の材料からなる保護膜
３１がその厚さをショート防止壁１７の高さと同じとさ
れて設けられている。この場合、保護膜３１が熱圧着時
の圧力等から半導体チップ２２の上面を保護することが
できる。また、保護膜３１がその厚さを突起電極１２の
高さよりも低くされて形成されているので、突起電極１
２を透明基板２３の接続端子２４に良好に導電接続する
ことができる。なお、この半導体装置の製造方法では、
保護膜３１がショート防止壁形成用層１６のパターニン
グ時に、ショート防止壁１７と同時に形成される。FIG. 8 shows a semiconductor device according to the second embodiment of the present invention. In this semiconductor device, a protective film 31 made of the same material as that of the short-circuit prevention wall 17 has the same thickness as the height of the short-circuit prevention wall 17 on the upper surface of the semiconductor chip 22 inside the arrayed portion of the protruding electrodes 12. Is provided. In this case, the protective film 31 can protect the upper surface of the semiconductor chip 22 from the pressure during thermocompression bonding. Further, since the protective film 31 is formed so that its thickness is lower than the height of the protruding electrode 12, the protruding electrode 1
2 can be satisfactorily conductively connected to the connection terminal 24 of the transparent substrate 23. In this semiconductor device manufacturing method,
The protective film 31 is formed simultaneously with the short-circuit prevention wall 17 when the short-circuit prevention wall forming layer 16 is patterned.
【００１６】[0016]
【発明の効果】以上説明したように、請求項４記載の発
明によれば、ウエハの一の面にスピンコートにより異方
導電性接着剤層を突起電極を覆うように形成し、次いで
ウエハを切断して個々のチップに分割しているので、請
求項１記載の発明のように、異方導電性接着剤層を予め
備えた半導体装置を得ることができる。この結果、請求
項７記載の発明のように、異方導電性接着剤層を備えた
半導体装置を基板上に載置すればよく、したがって従来
のようにシート状の異方導電性接着剤を基板上に仮熱圧
着する必要がなく、実装工程数を少なくすることができ
る。また、請求項４記載の発明によれば、ウエハの一の
面にスピンコートにより異方導電性接着剤層を突起電極
を覆うように形成しているので、半導体チップと異方導
電性接着剤層との間に空気が取り残されないようにする
ことができ、したがって異方導電性接着剤の接合力が低
下しないようにすることができる。As described above, according to the invention described in claim 4, an anisotropic conductive adhesive layer is formed on one surface of the wafer by spin coating so as to cover the protruding electrodes, and then the wafer is formed. Since the semiconductor device is cut and divided into individual chips, it is possible to obtain a semiconductor device provided with an anisotropic conductive adhesive layer in advance, as in the first aspect of the invention. As a result, the semiconductor device provided with the anisotropic conductive adhesive layer may be placed on the substrate as in the invention according to claim 7, and therefore, the sheet-shaped anisotropic conductive adhesive as in the conventional case is used. Since it is not necessary to perform temporary thermocompression bonding on the substrate, the number of mounting steps can be reduced. Further, according to the invention of claim 4, since the anisotropic conductive adhesive layer is formed on one surface of the wafer by spin coating so as to cover the protruding electrodes, the semiconductor chip and the anisotropic conductive adhesive are formed. It is possible to prevent air from being left behind between the layers and thus to prevent the bonding force of the anisotropic conductive adhesive from being deteriorated.
【図１】この発明の第１実施形態における半導体装置の
製造に際し、ウエハの上面中央部にショート防止壁形成
用材料を滴下した状態の一部を拡大して示す斜視図。FIG. 1 is an enlarged perspective view showing a part of a state in which a material for forming a short-circuit prevention wall is dropped on a central portion of an upper surface of a wafer when manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】図１に続く工程であって、スピンコートにより
ウエハの上面にショート防止壁形成用層を突起電極の上
部が露出するように形成した状態を示す断面図。FIG. 2 is a cross-sectional view showing a state following the step of FIG. 1, in which a layer for forming a short-circuit prevention wall is formed on the upper surface of the wafer by spin coating so that the upper portion of the bump electrode is exposed.
【図３】図２に続く工程であって、ショート防止壁を形
成した状態を示す断面図。FIG. 3 is a cross-sectional view showing a state where a short-circuit prevention wall is formed in the step following FIG. 2;
【図４】図３に続く工程であって、スピンコートにより
ウエハの上面に異方導電性接着剤層を突起電極およびシ
ョート防止壁を覆うように形成した状態を示す断面図。FIG. 4 is a cross-sectional view showing a state following the step of FIG. 3 in which an anisotropic conductive adhesive layer is formed on the upper surface of the wafer by spin coating so as to cover the protruding electrodes and the short-circuit preventing walls.
【図５】図４に続く工程であって、ウエハをダイシング
ストリートに沿ってダイシングして個々のチップに分割
した状態を示す断面図。FIG. 5 is a cross-sectional view showing a state following the step of FIG. 4 in which the wafer is diced along the dicing streets and divided into individual chips.
【図６】半導体装置の実装に際し、半導体装置を透明基
板上に位置合わせして載置した状態の断面図。FIG. 6 is a cross-sectional view showing a state in which the semiconductor device is aligned and placed on a transparent substrate when the semiconductor device is mounted.
【図７】半導体装置を透明基板上に実装した状態の断面
図。FIG. 7 is a cross-sectional view of a semiconductor device mounted on a transparent substrate.
【図８】この発明の第２実施形態における半導体装置を
示す断面図。FIG. 8 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図９】従来の半導体装置を透明基板上に実装した状態
の断面図。FIG. 9 is a cross-sectional view of a conventional semiconductor device mounted on a transparent substrate.
【図１０】半導体装置の実装に際し、半導体装置を透明
基板上に位置合わせして載置した状態の断面図。FIG. 10 is a cross-sectional view showing a state in which the semiconductor device is aligned and placed on the transparent substrate when the semiconductor device is mounted.
【図１１】従来の半導体装置の実装方法の問題点の１つ
を説明するために示す断面図。FIG. 11 is a cross-sectional view for explaining one of the problems of the conventional semiconductor device mounting method.
１１ ウエハ １２ 突起電極 １７ ショート防止壁 １８ 異方導電性接着剤層 ２１ 半導体装置 ２２ 半導体チップ ２３ 透明基板 ２４ 接続端子 ３１ 保護膜 11 Wafer 12 Projection Electrode 17 Shorting Prevention Wall 18 Anisotropic Conductive Adhesive Layer 21 Semiconductor Device 22 Semiconductor Chip 23 Transparent Substrate 24 Connection Terminal 31 Protective Film
Claims (8)
の面に設けられた突起電極と、前記半導体チップの一の
面に前記突起電極を覆うように設けられた異方導電性接
着剤層とを具備することを特徴とする半導体装置。1. A semiconductor chip, a protruding electrode provided on one surface of the semiconductor chip, and an anisotropic conductive adhesive layer provided on the one surface of the semiconductor chip so as to cover the protruding electrode. A semiconductor device comprising:
電極は前記半導体チップの一の面の外周部に配列して設
けられ、前記半導体チップの一の面の前記突起電極の配
列部の外側の部分にショート防止壁がその高さを前記突
起電極の高さよりも低くされて設けられていることを特
徴とする半導体装置。2. The invention according to claim 1, wherein the protruding electrodes are arranged and provided on an outer peripheral portion of one surface of the semiconductor chip, and outside the arrangement portion of the protruding electrodes on the one surface of the semiconductor chip. The semiconductor device, wherein a height of the short-circuit prevention wall is provided at a portion of the lower portion than that of the protruding electrode.
体チップの一の面の前記突起電極の配列部の内側の部分
に前記ショート防止壁と同一の材料からなる保護膜がそ
の厚さを前記ショート防止壁の高さと同じとされて設け
られていることを特徴とする半導体装置。3. The invention according to claim 2, wherein a protective film made of the same material as that of the short-circuit prevention wall is provided on the inner surface of the arrayed portion of the protruding electrodes on one surface of the semiconductor chip to have the thickness of the protective film. A semiconductor device having the same height as a short-circuit prevention wall.
一の面にスピンコートにより異方導電性接着剤層を前記
突起電極を覆うように形成し、次いで前記ウエハを切断
して個々のチップに分割することを特徴とする半導体装
置の製造方法。4. An anisotropic conductive adhesive layer is formed on one surface of a wafer having projection electrodes on one surface by spin coating so as to cover the projection electrodes, and then the wafer is cut into individual pieces. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is divided into chips.
ハの一の面に設けられた前記突起電極は前記各チップの
外周部に対応する位置に配列して設けられ、前記異方導
電性接着剤層を形成する前に、前記ウエハの一の面であ
って前記各チップの前記突起電極の配列部の外側の部分
にショート防止壁をその高さが前記突起電極の高さより
も低くなるように形成することを特徴とする半導体装置
の製造方法。5. The invention according to claim 4, wherein the protruding electrodes provided on the one surface of the wafer are arranged in positions corresponding to the outer peripheral portions of the respective chips, and the anisotropic conductive adhesive is used. Before forming the agent layer, a short-circuit prevention wall is formed on a surface of the wafer outside the protruding electrode arranging portion of each chip so that its height is lower than the height of the protruding electrode. A method of manufacturing a semiconductor device, comprising:
ハの一の面であって前記各チップの前記突起電極の配列
部の内側の部分に前記ショート防止壁の形成と同時に該
ショート防止壁と同一の材料からなる保護膜をその厚さ
が前記ショート防止壁の高さと同じとなるように形成す
ることを特徴とする半導体装置の製造方法。6. The invention according to claim 5, wherein the short-circuit prevention wall is formed at the same time when the short-circuit prevention wall is formed on one surface of the wafer and inside the arrangement portion of the protruding electrodes of each chip. A method of manufacturing a semiconductor device, wherein a protective film made of the same material is formed so that its thickness is the same as the height of the short-circuit preventing wall.
面に設けられた突起電極と前記半導体チップの一の面に
前記突起電極を覆うように設けられた異方導電性接着剤
層とからなる半導体装置を基板上に載置し、熱圧着する
ことにより前記半導体チップを前記異方導電性接着剤層
を介して前記基板上に実装することを特徴とする半導体
装置の実装方法。7. A semiconductor chip, a projection electrode provided on one surface of the semiconductor chip, and an anisotropic conductive adhesive layer provided on the one surface of the semiconductor chip so as to cover the projection electrode. A method for mounting a semiconductor device, comprising mounting the semiconductor device on a substrate and thermocompression-bonding the semiconductor chip on the substrate via the anisotropic conductive adhesive layer.
板上に載置し、熱圧着することにより前記半導体チップ
を前記異方導電性接着剤層を介して前記基板上に実装す
ることを特徴とする半導体装置の実装方法。8. The semiconductor device according to claim 2 or 3 is mounted on a substrate and thermocompression bonded to mount the semiconductor chip on the substrate via the anisotropic conductive adhesive layer. A characteristic method of mounting a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20511495A JP3038703B2 (en) | 1995-07-20 | 1995-07-20 | Semiconductor device, method of manufacturing the same, and method of mounting the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20511495A JP3038703B2 (en) | 1995-07-20 | 1995-07-20 | Semiconductor device, method of manufacturing the same, and method of mounting the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0936143A true JPH0936143A (en) | 1997-02-07 |
| JP3038703B2 JP3038703B2 (en) | 2000-05-08 |
Family
ID=16501658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20511495A Expired - Fee Related JP3038703B2 (en) | 1995-07-20 | 1995-07-20 | Semiconductor device, method of manufacturing the same, and method of mounting the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3038703B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918113A (en) * | 1996-07-19 | 1999-06-29 | Shinko Electric Industries Co., Ltd. | Process for producing a semiconductor device using anisotropic conductive adhesive |
| JP2000340877A (en) * | 1999-05-05 | 2000-12-08 | Mitel Semiconductor Ab | Assembly of vertical resonator surface-emitting laser and monitor for photodetection and assembling method for them |
| SG97773A1 (en) * | 1997-12-17 | 2003-08-20 | Tdk Corp | Magnetic head device and method of manufacturing same |
| KR100520080B1 (en) * | 2003-07-18 | 2005-10-12 | 삼성전자주식회사 | Surface Mounting Method of Semi-conduct Chip on PCB |
| JP2007300052A (en) * | 2006-04-28 | 2007-11-15 | Chukaminkoku Taiwan Hakumaku Denshotai Ekisho Keijiki Sangyo Kyokai | Flip-chip packaging part, and manufacturing method |
| US7327041B2 (en) | 2001-05-28 | 2008-02-05 | Sharp Kabushiki Kaisha | Semiconductor package and a method for producing the same |
| WO2008091840A2 (en) * | 2007-01-24 | 2008-07-31 | Analog Devices, Inc. | Stress free package and laminate-based isolator package |
| JP2011100843A (en) * | 2009-11-05 | 2011-05-19 | Sekisui Chem Co Ltd | Method for manufacturing semiconductor chip with adhesive layer |
-
1995
- 1995-07-20 JP JP20511495A patent/JP3038703B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918113A (en) * | 1996-07-19 | 1999-06-29 | Shinko Electric Industries Co., Ltd. | Process for producing a semiconductor device using anisotropic conductive adhesive |
| SG97773A1 (en) * | 1997-12-17 | 2003-08-20 | Tdk Corp | Magnetic head device and method of manufacturing same |
| JP2000340877A (en) * | 1999-05-05 | 2000-12-08 | Mitel Semiconductor Ab | Assembly of vertical resonator surface-emitting laser and monitor for photodetection and assembling method for them |
| US7327041B2 (en) | 2001-05-28 | 2008-02-05 | Sharp Kabushiki Kaisha | Semiconductor package and a method for producing the same |
| KR100520080B1 (en) * | 2003-07-18 | 2005-10-12 | 삼성전자주식회사 | Surface Mounting Method of Semi-conduct Chip on PCB |
| JP2007300052A (en) * | 2006-04-28 | 2007-11-15 | Chukaminkoku Taiwan Hakumaku Denshotai Ekisho Keijiki Sangyo Kyokai | Flip-chip packaging part, and manufacturing method |
| WO2008091840A2 (en) * | 2007-01-24 | 2008-07-31 | Analog Devices, Inc. | Stress free package and laminate-based isolator package |
| WO2008091840A3 (en) * | 2007-01-24 | 2008-11-06 | Analog Devices Inc | Stress free package and laminate-based isolator package |
| US7871865B2 (en) | 2007-01-24 | 2011-01-18 | Analog Devices, Inc. | Stress free package and laminate-based isolator package |
| JP2011100843A (en) * | 2009-11-05 | 2011-05-19 | Sekisui Chem Co Ltd | Method for manufacturing semiconductor chip with adhesive layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3038703B2 (en) | 2000-05-08 |
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