JPH09285120A - Main switch control circuit of power source equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a main switch control circuit which controls the loss of a main switch of a power source equipment and reatrains it at a low level. SOLUTION: MOSFET's Q1 and Q2 of a main switch are connected in parallel. The output terminal of a control circuit 1 is connected with the gate of an MOSFET Q1. The output terminal B of a delay circuit 4 is connected with the gate of the MOSFET Q2. By shifting the timing of ON/OFF control of the MOSFET's Q1 and Q2 and controlling them, the switching loss and the conducting loss can be restrained to be low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main switch control circuit in a power supply device, and more particularly to a main switch control circuit for controlling a switching loss due to the main switch to be low.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a main switch control circuit in a conventional one-stone forward type switching power supply. 10 is a diagram showing operation waveforms of the main switch control circuit, and FIG. 11 is a diagram showing switching loss and conduction loss generated from the main switch.

The MOSFET Qb1 is driven by the drive voltage Vgs from the control circuit 1. When Vgs has a high potential, the MOSFET Qb1 is turned on to be in a conductive state, the drain current Id flows, and the drain-source voltage Vds has a low potential. Conversely, if Vgs becomes low potential, MOSFET
Qb1 is turned off and becomes non-conductive, and drain current Id
No longer flows, and the drain-source voltage Vds becomes high potential. When it changes to a high potential, it becomes a mountain shape due to the influence of the L component of the main transformer Tb1 and has a constant potential.

[0004]

The losses generated in the main switch MOSFET Qb1 in the above main switch control circuit include drive loss, switching loss Ps, and conduction loss Pon. In FIG. 11, the switching loss Ps is the sum of the switching loss Pr generated during the turn-on tr and the switching loss Pf generated during the turn-off tf, and the conduction loss Pon is the loss generated during the ON period ton.

Ps and Pon are

[Equation 1] It is found like From the above equations (1) to (3), in order to reduce the switching loss generated in the main switch MOSFET Qb1 by the main switch control circuit, the MOSFET Q
It is understood that the turn-on time tr and turn-off time tf of b1 may be shortened, that is, the switching speed may be increased. Further, from the equation (4), it is understood that the ON resistance Rdson of the MOSFET Qb1 can be lowered to reduce the conduction loss Pon.

In other words, if an element having the characteristics of high switching speed and low ON resistance is used as the characteristics of the MOSFET, the main switch MOSFET Qb
The loss generated in 1 is reduced. However, increasing the switching speed and decreasing the ON resistance have a contradictory relationship, and there is a limit to the realization of a MOSFET with a high switching speed and a low ON resistance.

Therefore, it has been desired to realize a control circuit for the main switch which can reduce the loss generated in the main switch by using such a MOSFET.

[0008]

Means for Solving the Problems MOSFE of main switch
In the main switch control circuit of the power supply device that controls T,
For the primary winding of the main transformer, the first M of the main switch
The OSFET and the second MOSFET are connected in parallel, and the output terminal of the control circuit is the input terminal of the delay circuit and the first M
Connected to the gate of OSFET, the output terminal of the delay circuit is
Connect to the gate of the second MOSFET.

When the pulse output voltage of the control circuit becomes a high potential, the first MOSFET is turned on and becomes conductive.
Switching loss occurs when turning on. When the pulse output voltage of the delay circuit becomes high potential, the second MOS
The FET turns on and turns on, but at this time the drain-source voltage is at a low potential.
No switching loss occurs at turn-on. First,
A conduction loss occurs when the second MOSFET is in a conductive state, but since it is connected in parallel, the ON resistance is low and the conduction loss is low.

When the pulse output voltage becomes low potential, the first MOSFET is turned off and becomes non-conductive and turned off, but the drain-source voltage remains low potential and switching loss does not occur. Further, when the pulse output voltage of the delay circuit becomes low potential, the second MOSFE
T is turned off and becomes non-conductive, and switching loss occurs when it is turned off.

In this case, the first and second MOSFETs are
ON resistance is relatively high, but switching speed is fast M
By using the OSFET, the switching loss at the time of turn-on and at the time of turn-off can be suppressed to a low level because the MOSFET having a high switching speed is used. Further, since the first and second MOSFETs are connected in parallel and used, ON resistance becomes low and conduction loss can be suppressed low.

Further, in the control circuit for the main switches of the first and second MOSFETs, due to the modification of the ON-OFF control timing, the MOSFET having a relatively high ON resistance but a high switching speed and the switching speed relatively slow. Is a combination of MOSFETs with low ON resistance,
Switching loss and conduction loss can be kept low.

[0013]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention. The circuit configuration of the first embodiment will be described below with reference to FIG. In the case of this embodiment, the main switch control circuit 10 comprises a control circuit 1 and a delay circuit 4.

The negative terminal of the power source V1 is connected to GND, and the positive terminal thereof is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to GND.
The connection point between the positive terminal of the power source V1 and the capacitor C1 is connected to the positive electrode of the primary winding N1 of the main transformer T1.
The negative electrode of the next winding N1 is MOSFET Q1 and MOSFET
It is connected to the drain of Q2. The sources of MOSFETQ1 and MOSFETQ2 are connected to GND.

The positive pole of the secondary winding N2 of the main transformer T1 is connected to the anode of the diode D1.
The cathode of 1 is connected to the cathode of the diode D2. The connection point between the cathode of the diode D1 and the cathode of the diode D2 is connected to one end of the coil L1, and the other end of the coil L1 is connected to one end of the capacitor C2 and one end of the load circuit 6. The other end of the load circuit 6 is connected to the other end of the capacitor C2, the connection point is connected to the anode of the diode D2, and further to the negative electrode of the secondary winding N2 of the main transformer T1.

The output terminal of the control circuit 1 is MOSFET Q1.
Of the gate and the input terminal of the delay circuit 4.
The output terminal of the delay circuit 4 is connected to the gate of the MOSFET Q2.

FIG. 3 shows a delay circuit used in the delay circuit 4. The configuration of the delay circuit will be described with reference to FIG. The negative terminal of the input signal source Va1 is GN
The positive terminal is connected to one end of the resistor Ra1. The other end of Ra1 is connected to one end of the capacitor Ca1 and one input terminal of the OR circuit ORa1.
The other end of Ca1 and the other input terminal of ORa1 are connected to GND. The output terminal of ORa1 is the output of this delay circuit.

FIG. 2 shows operation waveforms of the first embodiment. The operation of the first embodiment will be described below with reference to FIG.

At time a1 when the pulse output voltage A obtained by the control circuit 1 becomes high potential, the MOSFET Q1 is turned on.
Then, it becomes conductive, and a drain current I1 flows between the drain and source of the MOSFET Q1. At this time, MOSF
The drain-source voltage C of the ETQ1 and the MOSFET Q2 becomes low potential. When the MOSFET Q1 is turned on, switching loss occurs due to the MOSFET Q1.

Next, at a time point b1 when the pulse output voltage B obtained from the delay circuit 4 becomes a high potential, the MOSFET Q2 is turned on and becomes conductive, and a drain current I2 flows between the drain and source of the MOSFET Q2. At this time, since the drain-source voltage C of the MOSFET Q2 has already become a low potential, switching loss due to the MOSFET Q2 does not occur when the MOSFET Q2 is turned on.

From the time point b1 to the time point c1 when the MOSFET Q1 and the MOSFET Q2 are in the conductive state, M
Since the OSFET Q1 and the MOSFET Q2 are connected in parallel, the ON resistance is low, and thus the conduction loss generated is low.

At the time point c1 when the pulse output voltage A has a low potential, the MOSFET Q1 is turned off and becomes non-conductive, and the drain current I1 stops flowing. MOSFET Q
When 1 is turned off, the drain of MOSFET Q1
Since the source voltage C remains at the low potential, no switching loss occurs. At the time point d1 when the pulse output voltage B becomes low potential, the MOSFET Q2 is turned off and becomes non-conductive, and the MOSFET Q1 and the MOSFET Q2.
The drain-source voltage C becomes high potential. MOSFE
When TQ2 is turned off, switching loss occurs due to MOSFET Q2.

While the drain-source voltage C is low, a voltage is generated in the secondary winding N2 of the main transformer T1,
Current flows through the diode D1 and is supplied to the load circuit 6. Also, while the drain-source voltage C is high, 2
Since no voltage is generated in the next winding N2, the energy accumulated in the coil L1 causes a current to flow through the diode D2,
It is supplied to the load circuit 6.

FIG. 4 shows operation waveforms of the delay circuit.
Here, the operation of the delay circuit will be described with reference to FIG. When the pulse voltage p is input to the delay circuit, the output q of the differentiating circuit composed of Ra1 and Ca1 has a waveform in which the rising and falling edges are not smooth. Generally a logic gate IC
Threshold voltage Vth is about 1/2 of the power supply voltage Vcc, and in the case of a blunt input waveform like q, q
Takes a certain amount of time to reach the threshold voltage Vth. As a result, the output pulse voltage r whose phase is delayed from the input voltage p to the delay circuit is obtained from the output terminal of the OR circuit ORa1.

In the case of the first embodiment, M of the main switch
For the OSFET Q1 and the MOSFET Q2, MOSFETs having characteristics that the ON resistance is relatively high but the switching speed is fast are used. As a result, the loss of the main switch at turn-on a1 is
The loss of the main switch at the time of turn-off b1 is only the loss due to the MOSFET Q2, and the switching speed of the main switch is fast, so that the switching loss of the main switch can be suppressed low.

In addition, MOSFETQ1 and MOSFETQ
Since 2 are connected in parallel, the main switch O
N resistance becomes low, MOSFETQ1 and MOSFETQ
It is also possible to keep the conduction loss low between the time point b1 and the time point c1 when 2 is ON. Therefore, switching loss and conduction loss are suppressed to a low level, and the main switch MOSFET is
Loss can be kept low, and the efficiency of the power supply device can be improved.

FIG. 5 is a diagram showing a second embodiment. The circuit configuration of the second embodiment will be described below with reference to FIG. The same components as those in FIG. 1 are designated by the same reference numerals. In the case of this embodiment, the main switch control circuit 11 includes a control circuit 1 and a control circuit 2 including a delay circuit 4, an AND circuit AND1, and an OR circuit OR1.

The minus terminal of the voltage source V1 is connected to GND, and the plus terminal of the voltage source V1 is connected to one end of the capacitor C1. The other end of the capacitor C1 is GND
It is connected to the. The connection point between the positive terminal of the voltage source V1 and the capacitor C1 is connected to the positive electrode of the primary winding N1 of the main transformer T1, and the negative electrode of the primary winding N1 is MOSFET Q3.
And the drain of the MOSFET Q4. MOS
The sources of the FET Q3 and the MOSFET Q4 are connected to GND. The connection on the side of the secondary winding N2 is the same as that in the first embodiment, and the description thereof is omitted.

Next, the structure of the main switch control circuit 11 will be described. The output terminal of the control circuit 1 is an AND circuit AN.
It is connected to one input terminal of D1, one input terminal of the OR circuit OR1, and the input terminal of the delay circuit 4. The output terminal of the delay circuit 4 is connected to the other input terminal of the logical product circuit AND1 and the other input terminal of the logical sum circuit OR1. The output terminal of the AND circuit AND1 is MOSF
The gate of ETQ3 and the output terminal of the OR circuit OR1 are connected to the gate of MOSFETQ4.

FIG. 6 shows operation waveforms of the second embodiment. Next, the operation of the second embodiment will be described with reference to FIG.

The pulse output voltage A obtained by the control circuit 1 becomes a high potential at the time point a2, and the OR circuit OR1 of the pulse output voltage B and the pulse output voltage B whose phase is delayed by the delay circuit 4 is applied. Pulse output voltage E becomes high potential. Between the time point a2 and the time point d2 when the pulse output voltage E is at a high potential, the MOSFET Q4 is turned on and becomes conductive, and the drain current I4 flows between the drain and the source. Also, when the drain current I4 flows, the MOSF
The drain-source voltage C of the ETQ3 and the MOSFET Q4 becomes low potential, and when the MOSFET Q4 is turned on, switching loss occurs due to the MOSFET Q4.

At time b2 when the pulse output voltage D of the AND circuit AND1 of the pulse output voltage A and the pulse output voltage B becomes high potential, the MOSFET Q3 is turned on and becomes conductive, and the drain current between the drain and source of the MOSFET Q3. I3 flows. At this point, MOSFET Q3 has already
Since the drain-source voltage C of is low potential,
No switching loss occurs when turning on the MOSFET Q3.

From the time point b2 to the time point c2 when the MOSFET Q3 and the MOSFET Q4 become conductive, the MOS
Since the FET Q3 and the MOSFET Q4 are connected in parallel, the ON resistance of the main switch is low. This reduces the conduction loss.

Next, the pulse output voltage A becomes a low potential c
At time 2, the pulse output voltage D becomes low potential and the MOSF
ETQ3 turns off and becomes non-conductive. At this time MOS
Since the drain / source voltage E of the FET Q3 remains at a low potential, no switching loss occurs when the MOSFET Q3 is turned off. At time d2 when the pulse output voltage B has a low potential, the pulse output voltage E also has a low potential,
The MOSFET Q4 is turned off and becomes non-conductive. MO
When the SFET Q4 is turned off, switching loss occurs due to the MOSFET Q4.

In the case of this embodiment, a MOSFET having a low ON resistance is used as the MOSFET Q3 of the main switch although the switching speed is relatively slow,
Although the ON resistance is relatively high for TQ4, a MOSFET with a high switching speed is used.

The switching loss at the time of turn-on and at the time of turn-off is only the switching loss due to the MOSFET Q4, and since the MOSFET Q4 is a MOSFET having a high switching speed, the switching loss can be suppressed to a low level. The conduction loss when the MOSFETs Q3 and Q4 are ON is the ON of the MOSFET Q3.
Resistance is low, and MOSFETQ3 and MOSFETQ4
Can be kept low because they are connected in parallel.

Therefore, from this fact, the MOS of the main switch is
The loss of the FET can be suppressed to a low level, and the efficiency of the power supply device can be improved. In addition, in the case of this embodiment, it can be expected that the conduction loss can be further reduced as compared with the first embodiment. However, the timing of the main switch control circuit 11 is more complicated than that of the main switch control circuit 10.

FIG. 7 is a diagram showing a third embodiment. Next, the configuration of the third embodiment will be described below with reference to FIG. In this embodiment, the main switch control circuit 12 includes a control circuit 1 and a control circuit 3 including a delay circuit 4, a delay circuit 5, and an exclusive OR circuit Ex-OR1. The same components as those in the first and second embodiments are designated by the same reference numerals.

The minus terminal of the voltage source V1 is connected to GND, and the plus terminal is connected to one end of the capacitor C5. The other end of the capacitor C1 is connected to GND. The connection point between the positive terminal of the voltage source V3 and the capacitor C5 is connected to the positive electrode of the primary winding N1 of the main transformer T3. The negative electrode of the primary winding N1 has MOSFETs Q5 and MO.
It is connected to the drain of SFET Q6. MOSFET Q
5 and the sources of MOSFET Q6 are connected to GND. The configuration of the transformer T1 after the secondary side is the same as that of the first embodiment, and the description thereof is omitted.

Next, the structure of the main switch control circuit 12 will be described. The output terminal of the control circuit 1 is connected to one input terminal of the exclusive OR circuit Ex-OR1 and the input terminal of the delay circuit 4. The output terminal of the delay circuit 4 is a MOSFE
It is connected to the gate of TQ5 and the input terminal of the delay circuit 5. The output terminal of the delay circuit 5 is connected to the other input terminal of the Ex-OR1. Further, the exclusive OR circuit Ex
The output terminal of -OR1 is connected to the gate of MOSFET Q6. FIG. 8 shows operation waveforms of the third embodiment. The operation of the third embodiment will be described below with reference to FIG.

At time a3 when the pulse output voltage A obtained by the control circuit 1 becomes a high potential, the pulse output voltage A is delayed in phase by the delay circuit 4 and the delay circuit 5, and the pulse output voltage A. Exclusive-OR circuit Ex-O with
The pulse output voltage G of R1 has a high potential. At this time, MO
The SFET Q6 is turned on and becomes conductive, and the MOSFET
A drain current I6 flows between the drain and source of Q6. At this time, MOSFET Q5 and MOSFET
The drain-source voltage C of Q6 becomes low potential,
Switching loss occurs due to the MOSFET Q6 when the FET Q6 is turned on.

At time b3 when the phase of the pulse output voltage A is delayed by the delay circuit 4 and the pulse output voltage B becomes a high potential, the MOSFET Q5 is turned on to be in the conductive state, and the MO
Drain current I5 between the drain and source of SFET Q5
Flows. At this time, the drain-source voltage of the MOSFET Q5 has already become a low potential.
No switching loss occurs when Q5 is turned on.

At a time point c3 when the pulse output voltage G has a low potential, the MOSFET Q6 is turned off and becomes non-conductive. At this time, the drain-source voltage C of the MOSFET Q6 remains at a low potential, so that no switching loss occurs when the MOSFET Q6 is turned off.

With MOSFET Q5 conducting, MOSF
Between the time point c3 and the time point d3 when the ETQ6 is non-conductive, only the MOSFET Q5 has a conduction loss.

At time d3 when the pulse output voltage G has a high potential, the MOSFET Q6 is turned on to be in a conductive state. At this time, the drain-source voltage C of the MOSFET Q6 remains at a low potential, and switching is performed when the MOSFET Q6 is turned on. No loss occurs. At time e3 when the pulse output voltage B has a low potential, the MOSFET Q5 is turned off and becomes non-conductive, but at this time, the drain-source voltage C of the MOSFET Q5 remains at a low potential, and
No switching loss occurs when Q5 is turned off.

At time f3 when the pulse output voltage G has a low potential, the MOSFET Q6 is turned off and becomes non-conductive, and the drain-source voltage C of the MOSFET Q5 and the MOSFET Q6 has a high potential. At this time, MOSFET
Switching loss occurs due to MOSFET Q6 when Q6 is turned off.

In the case of this embodiment, the MO of the main switch is
SFET Q5 has a relatively slow switching speed,
Uses MOSFET with low ON resistance, and MOSFE
Although the ON resistance is relatively high for TQ6, a MOSFET with a high switching speed is used.

As a result, the switching loss at the time point a3 at the time of turn-on and at the time point f3 at the time of turn-off is only the loss due to the MOSFET Q6 having a high switching speed and can be kept low. Also, the main switch MO
The conduction loss from the time point c3 to the time point d3 when the SFET Q5 is ON is low because the MOSFET Q6 having a high ON resistance is OFF and the loss is only the MOSFET Q5 having a low ON resistance. Therefore, the MO of the main switch
The loss in the SFET can be suppressed low, and the efficiency of the power supply device is improved. In the case of this embodiment, the conduction loss can be expected to be further suppressed as compared with the cases of the first and second embodiments, but the timing of the main switch control circuit 12 becomes more complicated.

Although the first, second, and third embodiments are applied to the one-stone forward type power supply device, the present invention is not limited to this, and is also applied to a half-bridge type or full-bridge type power supply device. it can. Further, it is not limited to the voltage step-down type, but can be applied to the step-up type and the step-up / down type. Further, it is not limited to insulation or non-insulation. Furthermore, although these embodiments are applied to the main switch control circuit of the power supply device, the present invention is not limited to this and can be applied to a protection circuit and other control circuits.

Although the delay circuit is constructed by using an OR circuit, it may be constructed by another logic gate circuit, a comparator, or the like.

[0051]

According to the present invention, the MOS of the main switch is
As FETs, a plurality of FETs having a high switching speed but a relatively high ON resistance and a FET having a low ON resistance but a relatively slow switching speed are connected in parallel to be connected, and ON / OFF control thereof is performed. By shifting the timing, it is possible to keep the switching loss of the main switch low and the conduction loss low. This improves the efficiency of the power supply.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment.

FIG. 2 is a diagram showing operation waveforms of a main switch control circuit according to the first embodiment.

FIG. 3 is a diagram showing a delay circuit.

FIG. 4 is a diagram showing operation waveforms of a delay circuit.

FIG. 5 is a diagram showing a circuit configuration of a second embodiment.

FIG. 6 is a diagram showing operation waveforms of a main switch control circuit according to a second embodiment.

FIG. 7 is a diagram showing a circuit configuration of a third embodiment.

FIG. 8 is a diagram showing operation waveforms of a main switch control circuit according to a third embodiment.

FIG. 9 is a diagram showing a conventional main switch control circuit configuration.

FIG. 10 is a diagram showing operation waveforms of a conventional main switch control circuit.

FIG. 11 is a diagram showing switching loss and conduction loss generated from the main switch.

[Explanation of symbols]

 1 ... Control circuit 2, 3 ... Delay control circuit 4, 5 ... Delay circuit 6 ... Load circuit 10, 11, 12 ... Main switch control circuit

Claims (6)

[Claims] 1. In a main switch control circuit of a power supply device for controlling a MOSFET of a main switch, a first MOSF of the main switch is provided in a primary winding of a main transformer.
ET and the second MOSFET are connected in parallel, and the output terminal of the control circuit is the input terminal of the delay circuit and the first terminal.
Connected to the gate of the MOSFET, the output terminal of the delay circuit is connected to the gate of the second MOSFET, the ON / OFF control timing is shifted, and the first MOSFET and the second MOSFET of the main switch are connected. A main switch control circuit of a power supply device, characterized in that 2. The main switch control circuit of the power supply device according to claim 1, wherein the first and second MOSFETs have O
MO with high N resistance but high switching speed
It is characterized by using SFET. 3. A main switch control circuit of a power supply device for controlling a MOSFET of a main switch, wherein the primary winding of the main transformer has a first MOSF of the main switch.
ET and the second MOSFET are connected in parallel, the output terminal of the control circuit is one input terminal of the AND circuit,
One input terminal of the logical sum circuit and an input terminal of the delay circuit, the output terminal of the delay circuit is connected to the other input terminal of the logical product circuit and the other input terminal of the logical sum circuit, The output terminal of the logical product circuit is connected to the gate of the first MOSFET, the output terminal of the logical sum circuit is connected to the gate of the second MOSFET, and the ON / OFF control timing is shifted, A main switch control circuit for a power supply device, which controls a first MOSFET and a second MOSFET of a main switch. 4. The main switch control circuit of the power supply device according to claim 3, wherein the first MOSFET has a relatively low switching speed but a low ON resistance.
Is used, and a MOSFET having a relatively high ON resistance but a high switching speed is used for the second MOSFET. 5. A main switch control circuit of a power supply device for controlling a MOSFET of a main switch, wherein the primary winding of the main transformer has a first MOSF of the main switch.
ET and the second MOSFET are connected in parallel, the output terminal of the control circuit is connected to one input terminal of the exclusive OR circuit and the input terminal of the first delay circuit, and the output of the first delay circuit The terminal is the first MOSF
The gate of ET is connected to the input terminal of the second delay circuit, the output terminal of the second delay circuit is connected to the other input terminal of the exclusive OR circuit, and the output of the exclusive OR circuit The terminal is the second MOS
A main switch control circuit for a power supply device, which is connected to a gate of an FET and controls the first MOSFET and the second MOSFET of the main switch by shifting ON / OFF control timing. 6. The main switch control circuit for a power supply device according to claim 5, wherein a MOSFET having a relatively low switching speed but a low ON resistance is used for the first MOSFET, and an ON resistance is used for the second MOSFET. It is characterized by using a MOSFET having a relatively high switching speed.