JPH09283766A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance SOI type transistor which controls a substrate potential without wasting its area. SOLUTION: A MOS transistor is formed on a substrate 1 of SOI structure. A buried oxide layer 2 is provided on the conductive silicon substrate 1 or a conductive substrate 13. A device forming portion 4 and a device non-forming portion 5 are provided in a silicon layer on the buried oxide layer 2. The device forming portion 4 comprises a region including a source-drain region 6 and a channel region 7, a gate oxide film 8 and a gate electrode 9. The device non-forming portion 5 comprises a device isolation oxide film 10. Further, the device non-forming portion 5 has a mark and a positioning plug 11b. The buried oxide layer 2 includes a substrate-potential control electrode 12b to connect the channel region 1 to the conductive silicon substrate 1 or the conductive substrate 13. Thus, the substrate potential under the channel region can be reliably controlled. Further, different from conventional constitutions, the control is made from the rear surface, which avoids waste of area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using SOI and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, SOI type transistors are one of the technologies that have been attracting attention, and have a smaller parasitic capacitance than bulk type transistors, so that high speed operation and low power consumption are possible. However, when the partially depleted SOI transistor is operated without taking the substrate potential, minority carriers are accumulated in the substrate, which causes characteristic deterioration such as a kink phenomenon peculiar to the SOI transistor due to the substrate floating effect.

In the prior art, there is a method in which a part of the channel region of a MOS transistor is connected to an electrode different from the gate electrode to control the substrate potential through the electrode.

An example of the above substrate potential control technique will be described below with reference to the drawings.

As this technique, the technique described in JP-A-7-273340 is known. FIG. 4 is a schematic plan view showing a pattern of a conventional field effect transistor capable of controlling a substrate potential. In FIG. 4, the channel region 21 is formed on the SOI substrate.
a, b and source / drain diffusion layers 22 are formed,
The gate electrode 23 is formed so as to cover only the channel region 21a. The channel region 21b that is not covered by the gate electrode 23 is connected to the extraction electrode 25 via the channel contact 24, and the extraction electrode 25 extracts unnecessary charges accumulated in the substrate regions of the channel regions 21a and 21b. be able to.

[0006]

However, the above-mentioned structure has the following problems. The current driving force is lower than that of the transistor having the same gate width, and the area loss is larger than that of the transistor having the same driving force.

An object of the present invention is to provide a high-performance SOI-type transistor which is free from area loss and substrate floating effect in a transistor formed on an SOI substrate and a manufacturing method thereof.

[0008]

In order to solve the above problems, in the SOI type transistor of the present invention, an oxide film for element isolation is formed on the SOI substrate after element formation and wiring steps on the SOI substrate. Based on the formed mark and the alignment plug, a contact hole is opened from the back surface to the buried oxide film layer below the channel region, the electrode is buried, and the substrate potential is controlled. Unlike the conventional example, the area loss is eliminated by controlling the substrate potential from the back surface.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG.
The description will be made with reference to 1 and 2.

FIG. 1 is a sectional view of an SOI structure, and FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

First, FIG. 1 shows an SOI (Silicon) including a silicon substrate 1, a buried oxide film layer 2 and an upper silicon layer 3.
On Insulator) board is shown. Next, as shown in FIG. 2, MOS type transistors are formed on the substrate of FIG. However, in FIG. 2, the silicon substrate 1 of FIG. 1 is the conductive silicon substrate 1 or the conductive substrate 13. A buried oxide film layer 2 is provided on the conductive silicon substrate 1 or the conductive substrate 13, and an element forming portion 4 and a non-element forming portion 5 are provided on the upper silicon layer 3 thereon. The element forming portion 4 is composed of a region including a source / drain region 6 and a channel region 7, a gate oxide film 8 and a gate electrode 9. Element non-formation part
The element isolation oxide film 10 is formed. Further, the element non-formation portion 5 has a mark and an alignment plug 11b, and the channel region 7 and the conductive silicon substrate 1 or the conductive substrate 13 are connected in the buried oxide film layer 2. There is a substrate potential control electrode 12b. The configuration of the semiconductor device is as described above.

In particular, it is characterized in that it is provided with a mark of the element non-formation portion 4, a positioning plug 11b and a substrate potential control electrode 12b in the buried oxide film layer 2. With such a configuration, the substrate potential under the channel region can be surely controlled, and unlike the conventional example, since it is controlled from the back surface, there is an effect that an area loss is eliminated.

An embodiment of the present invention will be described below with reference to FIG. FIG. 3 is a process sectional view of a semiconductor device according to a second embodiment of the present invention. First, as shown in FIG. 3 (a), after forming the element isolation oxide film 10 on the upper silicon layer 3, the central portion of the element isolation oxide film 10 which is a SiO2 film is used as a mark and the alignment hole 11a is formed. For formation, etching is performed until reaching the lower silicon substrate 1. Further, the CVD (Chemic
A metal such as tungsten is embedded by an al Vapor Deposition) method to form a mark and a positioning metal plug 11b. The plug 11b serves both as a mark for aligning the wafer after removing the silicon substrate 1 from the back surface and as a mark for opening a contact hole in the buried oxide film layer below the channel region 7. After this step, elements are formed in the element forming portion 4 (FIG. 3 (b)). The plug 11b may be an insulator plug other than metal or a void.

Next, as shown in FIG. 3C, the element forming portion 4
After the necessary wiring process 14 and the protective film 15 are deposited on the upper surface, the entire surface of the protective film 15 is subjected to CMP (Chemical Mechanical Polis
hing) method, etc.

Next, as shown in FIG. 3D, a polishing supporting metal plate 16 is attached on the protective film 15 in order to increase the strength during polishing. Further, the silicon substrate 1 is polished by the CMP method until it reaches the buried oxide film layer 2 (from bottom to top in the figure). If the strength during polishing is sufficient, the step of flattening the protective film 15 and the polishing supporting metal plate 16 are unnecessary. This step is not limited to polishing, but may be etching with an alkaline solution such as an aqueous solution of ethylenediamine or pyrocatechol or an aqueous solution of hydrazine or isopropyl alcohol.
The reason for using these alkaline solutions is that silicon is etched due to a difference in selectivity, but an oxide film is difficult to etch.

Further, the wafer is aligned with the metal plug 11b as a mark, and then the contact hole 12a is formed in the buried oxide film layer 2 under the channel region 7 with the mark. The contact hole 12a reaches the channel region 7. After forming the contact hole, the contact hole
A metal such as aluminum is deposited on 12a and the entire surface by a CVD method to form a substrate potential control electrode 12b. Further patterning is performed to provide wiring with other elements.

As described above, the plug 11b is formed in the element non-forming portion 5.
Since it is possible to form the contact hole 12a which is connected to the channel region 7 by using this as a mark, it is possible to reliably control the substrate potential under the channel region 7.

[0018]

As described above, the present invention provides a silicon substrate,
It has a three-layer structure of a buried oxide film layer and an upper silicon layer.
In the SOI field effect transistor formed on the SOI substrate, by opening a contact hole in the buried oxide film layer below the channel region and embedding the electrode, the substrate potential can be controlled without area loss compared to the conventional example. . That is, the substrate floating effect can also be suppressed.

[Brief description of drawings]

FIG. 1 Schematic cross-sectional view of SOI substrate

FIG. 2 is a schematic sectional view of an SOI type transistor structure according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a method for manufacturing an SOI type transistor according to the second embodiment of the present invention.

FIG. 4 is a schematic plan view showing a pattern of a conventional field effect transistor capable of taking a substrate potential.

[Explanation of symbols]

 1 Silicon Substrate 2 Embedded Oxide Layer 3 Upper Silicon Layer 4 Element Forming Area 5 Element Non-Forming Area 6 Source / Drain Region 7 Channel Region 8 Gate Oxide Film 9 Gate Electrode 10 Element Isolation Oxide Film 11a Marks, Positioning Holes 11b Marks and alignment plugs 12a Contact holes 12b Substrate potential control electrode 13 Conductive substrate 14 Wiring 15 Protective film 16 Polishing support substrate 21a, b Channel region (conventional example) 22 Source / drain diffusion layer (conventional example) 23 Gate electrode (Conventional example) 24 Channel contact (Conventional example) 25 Extraction electrode (Conventional example) 26 Element region (Conventional example) 27 Source / drain electrode (Conventional example)

Claims (4)

[Claims] 1. A field effect transistor formed on an upper silicon layer of an SOI substrate, comprising at least one plug in a non-formed portion of the field effect transistor, and controlling a substrate potential below a channel region of the field effect transistor. A semiconductor device comprising an electrode. 2. A step of forming an element forming part in a part of an upper silicon layer of an SOI substrate, a step of providing at least one opening in a region other than the element forming part, and a plug embedded in the opening. A step, a step of forming a field effect transistor in the element forming portion, a step of sequentially forming a wiring pattern and a protective film, a step of removing the silicon substrate from the back surface to expose the plug, and a mark for the plug A step of forming the buried oxide film below the channel region of the field effect transistor as an alignment key to form a substrate potential control electrode. 3. The semiconductor device according to claim 1, wherein the plug is a metal, an insulator, or a void. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the plug is a metal, an insulator, or a void.