JPH09219460A - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute electrical isolations in the word line direction of a floating gate arrangement without making grooves form in an element isolation oxide film by a method wherein after oxygen-containing ions are implanted in a polycrystalline silicon film for floating gate use, a heat treatment is performed on the silicon film and only regions implanted the oxygen-containing ions out of the silicon film are partially converted into an insulative silicon dioxide film. SOLUTION: A resist film is formed on a polycrystalline silicon film 8 formed on the whole surface of a semiconductor substrate 2 and oxygen-containing ionic species are implanted in the film 8 using a resist pattern 30, which has rectangular open holes 32 on element isolation insulating films 4 for forming regions where isolations in the word line direction of a floating gate arrangement are executed, as a mask. After the pattern 30 is removed, a heat treatment is performed on the film 8 and only regions implanted the oxygen ions out of the film 8 are selectively made to convert into an insulative silicon dioxide film. By these mnsulative silicon dioxide films, the isolations in the word line direction of the floating gate arrangement can be executed without forming unintended grooves in an element isolation oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a stack gate composed of a floating gate and a control gate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 1 shows a manufacturing process including a commonly used method for forming a stack gate. (A) ~
(C) is XX ′ of (a) to (c) described on the right side thereof.
It is sectional drawing in a line position. (A) A field oxide film 4 as an element isolation region is formed on a silicon substrate 2, a gate insulating film 6 is formed, and then a first polycrystalline silicon layer 8 to be a floating gate is formed. A resist layer is formed on the polycrystalline silicon layer 8, and a resist pattern having a groove for forming a slit 10 for separating the floating gate in the word line direction is formed by photolithography. The slit 10 is formed by etching the silicon layer 8.

(B) The insulating film 12 is formed on the surface of the polycrystalline silicon layer 8, and the second polycrystalline silicon layer 1 is further formed thereon.
4 is formed. Then, the silicon layer 14, the insulating film 12 and the polycrystalline silicon layer 8 are patterned by photolithography and etching to complete the control gate 14, the insulating film 12 and the floating gate 8.

(C) After that, an interlayer insulating film 16 is formed,
After forming the contact hole 18 on the drain region, an aluminum film is formed, an aluminum wiring 20 is formed by patterning by photolithography and etching, and the aluminum wiring 20 and the drain region are connected through the contact hole 18. The aluminum wiring 20 becomes a bit line and the control gate 14 becomes a word line.

The stack gate forming method shown in FIG. 1 is a basic method, and the stack gate forming method described in, for example, JP-A-2-31466 and JP-A-3-34470 is also used. Is the same.

The method of FIG. 1 has the following drawbacks.
This is separated in the bit line direction in FIG.
The patterning step (B) will be described. FIG. 2 shows a state in which the second polycrystalline silicon film 14 is anisotropically etched using the resist pattern 15 for the purpose of separating in the bit line direction. Since the underlying first polycrystalline silicon film 8 is already patterned for separation in the word line direction and the groove 10 for separation is formed, the second polycrystalline silicon film 8 is formed in the groove 10 portion. Polycrystalline silicon film 1
4 remains in the form of sidewalls 14a.

Next, FIG. 3 shows that the insulating film 12 is subsequently anisotropically etched. Since the polycrystalline silicon film is not etched by the etching of the insulating film 12, the sidewall 14a formed of the polycrystalline silicon film remains as it is. Further, since the insulating film 12 exists between the side walls of the first polycrystalline silicon film 8 and the side walls 14a, the etching of this part is difficult to proceed. Therefore, the insulating film 12 remains in the form of the fence 12a.

Further, in the portion directly below the insulating film 12 and where the first polycrystalline silicon film 8 does not exist, the following problems occur. First, the first polycrystalline silicon film 8 is formed on the thick insulating film 4 for element isolation and directly below the insulating film 12.
In the portion where there is no (region 22 in FIG. 1B), the thick insulating film 4 for element isolation is continuously anisotropically etched following the anisotropic etching of the insulating film 12. As a result, the unintended groove 10a is formed in the thick insulating film 4 for element isolation (see FIG. 3B). The first insulating film 12 is formed on the gate insulating film 6 and directly below the insulating film 12.
Of the polycrystalline silicon film 8 of FIG.
In 4), the gate insulating film 6 is continuously anisotropically etched for the same reason, and the semiconductor substrate 2 is exposed (FIG. 3B).
reference).

Further, FIG. 4 shows that the first polycrystalline silicon film 8 is anisotropically etched. Although the sidewalls 14a of polycrystalline silicon are removed by this etching, the fences 12a of the insulating film formed in FIG. 3 cannot be removed, and thus remain as they are. Further, in the portion 10b where the semiconductor substrate 2 is exposed in FIG. 3, the semiconductor substrate is etched by the anisotropic etching at this time, so that an unintended groove 10c is formed (see FIG. 4C). Here, the trench 10a formed in the stage of FIG. 3 is a trench in which the thick insulating film 4 for element isolation is dug, and the trench 10c formed in the stage of FIG. 4 is a trench in which the semiconductor substrate 2 is dug. FIG. 1B shows a state in which the resist pattern 15 has been removed thereafter.

The drawbacks of the prior art shown in FIG. 1 can be summarized into the following three points. Disadvantage 1: Unintended groove 10 in thick insulating film 4 for element isolation
a is formed. Disadvantage 2: Unintended groove 10c is formed in the semiconductor substrate 2. Disadvantage 3: Unintended fence 12a remains on the inner wall surfaces of the grooves 10a and 10c.

Due to these drawbacks, the following problems occur in the subsequent steps. Inconvenience 1: Due to the groove 10a of the defect 1, the source / drain implantation in the later step penetrates the insulating film for element isolation and is implanted into the semiconductor substrate 2. Defect 2: Incomplete planarization due to the grooves 10a and 10c. Problem 3: In the semiconductor substrate 2, the region in which the groove 10c is formed serves as a common source line, so that the resistance value of the diffusion layer increases due to the step of the groove 10c.

Problem 4: When a memory element having this stack gate is formed on the same substrate as the MOS transistor of the peripheral circuit on the same substrate, if the three-layer polycrystalline silicon process is adopted, the third-layer polycrystalline silicon film will have a groove. Since they remain in the form of sidewalls in 10a and 10c, it is necessary to remove them. And if the removal is not complete, it causes a leak. Problem 5: The fence 12a peels off and becomes a foreign substance.

Therefore, some techniques for avoiding these problems have been proposed. The first suggestion is FIG. 5 (A).
As described above, the groove of the first polycrystalline silicon film 8 is formed in the insulating film 28.
(See Japanese Patent Application Laid-Open No. 62-128567 and Japanese Patent Application Laid-Open No. 2-65175). A second proposal is a method of filling the groove of the first polycrystalline silicon film 8 with the second polycrystalline silicon film 14 as shown in FIG. 5 (B) (Japanese Patent Laid-Open No. 186478/1988). Kaihei 4-586
No. 5).

[0014]

All of these proposals prevent the thick insulating film for element isolation and the semiconductor substrate from being exposed to unintentional etching and prevent film loss. It has such new drawbacks. According to the first proposal, it is extremely difficult to fill the groove of the first polycrystalline silicon film 8 with the insulating film 28. For example, if the method of etching the entire surface after depositing the insulating film 28 is used as a filling, the insulating film 28 is also embedded in the concave portion on the first polycrystalline silicon film 8 as shown in FIG. 5C. Therefore, it becomes impossible to form the insulating film 12 in the subsequent step, and it becomes impossible to form the memory.

In the second proposal, in order to fill the groove of the first polycrystalline silicon film 8 with the second polycrystalline silicon film 14, the thickness of the second polycrystalline silicon film 14 is made thicker than necessary. Must be done, resulting in a large stack gate height. This hinders the flattening in the subsequent process and leads to problems such as metal wiring disconnection. SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure of a memory device and a method of manufacturing the same that solve these problems.

[0016]

In a stack gate type non-volatile semiconductor memory device, electrical isolation in the word line direction of a floating gate array on an element isolation oxide film is performed by silicon oxide. And the oxygen concentration at the boundary between the floating gate and the polycrystalline silicon changes continuously.

The manufacturing method of the present invention is a method of forming a stack gate on a semiconductor substrate including the following steps (A) to (F). (A) A device isolation oxide film is selectively formed on a semiconductor substrate, a gate oxide film is formed on an active region of the substrate, and then a first floating gate is formed on the entire surface of the substrate.
Forming a polycrystalline silicon film, (B) has an opening in the isolation region for electrically isolating adjacent floating gates of the floating gate array in the word line direction on the element isolation oxide film. A step of forming a resist pattern, (C) a step of ion-implanting an ion species containing oxygen into the polycrystalline silicon film in the opening using the resist pattern as a mask, and (D) a heat treatment after removing the resist pattern. A step of selectively converting the ion-implanted region of the polycrystal silicon film into an insulating film by applying, (E) forming an insulating film to be an interlayer insulating film between the floating gate and the control gate, (F) Second control gate on the entire surface
And forming a stack gate by patterning the second polycrystalline silicon film, the insulating film, and the first polycrystalline silicon film by photolithography and etching. Implanted in the ion implantation step of step (C),
Ionic species containing oxygen include oxygen ions, NO ions, NO
It is preferably ₂ ions or N ₂ O ions.

[0018]

EXAMPLE Next, an example of the present invention will be described together with a manufacturing method. As shown in FIG. 6, after forming a gate insulating film 6 on a semiconductor substrate (silicon substrate) 2 on which a thick insulating film (field oxide film) 4 for element isolation is formed, the entire surface of the semiconductor substrate 2 is covered. The first polycrystalline silicon film 8 is formed.

A resist layer is formed on the polycrystalline silicon film 8 and, as shown in FIG. 6A, a rectangle is formed on the element isolation insulating film 4 for forming a region for performing isolation in the word line direction. A resist pattern 30 having a shaped opening 32 is formed by photolithography. After that, resist pattern 3
Ion species containing oxygen are implanted into the polycrystalline silicon film 8 using 0 as a mask. The ionic species containing oxygen are, for example, oxygen ions as well as molecular ions such as NO ions, NO ₂ ions, and N ₂ O ions. Here, for example, when oxygen ions are implanted under the conditions of energy of 30 KeV and dose amount of 5 × 10 ¹⁵ / cm ² , only the opened region 34 of the resist pattern 30 in the first polycrystalline silicon film 8 is selectively selected. Oxygen ions are implanted.

After removing the resist pattern 30, a heat treatment is performed at 1000 ° C. for 1 hour, for example, so that only the region of the polycrystalline silicon film 8 into which oxygen ions are implanted is selectively converted into insulating silicon dioxide 36. Let This insulating silicon dioxide 36 separates the floating gate in the word line direction.

Thereafter, as shown in FIG. 7, as in the prior art, the interlayer insulating film 12 between the floating gate and the control gate, and the second gate for the control gate.
Then, the polycrystalline silicon film 14 is formed. A resist layer is formed on the second polycrystalline silicon film 14 and is patterned by photolithography so as to be separated in the bit line direction to form a resist pattern 15 so as to be orthogonal to the region 36a. Then, the polycrystalline silicon film 14, the interlayer insulating film 12 and the polycrystalline silicon film 8 are patterned by anisotropic etching using the resist pattern 15 as a mask to obtain the stack gate of the present invention.

In the present invention, the drawback 1 pointed out in the prior art
Neither 2 nor 3 occurs. This will be described with reference to FIG. 7 in which a resist pattern 15 for separating in the bit line direction is arranged as a starting point. In the present invention, as shown in FIG.
Only the region 36a of the polycrystalline silicon film 8 is selectively converted into insulating silicon dioxide. First, FIG. 8 shows a state in which the second polycrystalline silicon film 14 is anisotropically etched using the resist pattern 15. In the present invention, the separation of the underlying first polycrystalline silicon film 8 is realized by partially converting the polycrystalline silicon into the insulating silicon dioxide 36 instead of the groove by etching, so that the groove originally exists. do not do. Therefore, the second polycrystalline silicon film 14 does not remain in the form of the sidewall 14a as shown in FIG.

Next, FIG. 9 shows a state in which the insulating film 12 is subsequently anisotropically etched. Since the etching is performed from the state shown in FIG. 8, it can be easily understood that FIG. 9 is obtained.
In the present invention, silicon dioxide 3 is formed in a portion immediately below the insulating film 12 and where the first polycrystalline silicon film 8 does not exist.
Since the region 36a converted into 6 exists, even if the anisotropic etching of the interlayer insulating film 12 progresses, the silicon dioxide 36 only needs to be removed. As a result, the unintended groove 10a is not formed in the thick insulating film 4 for element isolation as shown in FIG. 3 (avoidment of the defect 1 pointed out in the prior art).

Further, in the portion other than the silicon dioxide 36, the first polycrystalline silicon film 8 is always present immediately below the interlayer insulating film 12, so that the semiconductor substrate 2 is not exposed as shown in FIG. . Further, FIG. 10 shows a state in which the first polycrystalline silicon film 8 is anisotropically etched. Since the etching is performed from the state of FIG. 9, it can be easily understood that FIG. 10 is obtained. In the present invention, the semiconductor substrate 2 is not exposed unlike the prior art FIG. 3, so that the semiconductor substrate 2 is not etched by the anisotropic etching at this time. Therefore, the unintended groove 10c is not formed in the semiconductor substrate 2 (the defect 2 pointed out in the prior art is avoided).

Furthermore, as a matter of course, in the present invention, the fence 12a of the prior art shown in FIG. 4 is not essentially formed (avoidance of the defect 3 pointed out in the prior art). As described above, in the present invention, the drawbacks 1, 2, 3 pointed out in the prior art
None of these occur. Therefore, any of the problems pointed out in the prior art can be avoided.

FIG. 11 shows a state in which the resist pattern 15 is removed thereafter, and the stack gate is completed by this. The electrical isolation in the word line direction of the floating gate array on the element isolation oxide film 4 is performed by implanting ions containing oxygen into the polycrystalline silicon for the floating gate and then heat treating the polycrystalline silicon for the floating gate. Since it is realized by converting to 36,
The oxygen concentration at the boundary between the region of the silicon dioxide 36 and the polycrystalline silicon 8 of the floating gate continuously changes.

[0027]

According to the present invention, the electrical isolation in the word line direction of the floating gate array on the oxide film for element isolation is achieved by implanting ions containing oxygen into the polycrystalline silicon for the floating gate and subjecting it to heat treatment. Since it is realized by converting it into insulating silicon dioxide, an unintended groove is not formed in the element isolation oxide film, and an unintended groove is not formed in the semiconductor substrate. Further, since there is no groove for separating the floating gate array in the word line direction, unintended fences do not remain on both sides of the groove. As a result of these, a highly reliable nonvolatile semiconductor memory device is obtained. In the manufacturing method of the present invention, electrical isolation in the word line direction of the floating gate array is realized only by ion implantation and heat treatment, so that the manufacturing is easy and can be realized at low cost.

[Brief description of drawings]

1A to 1C are views showing a conventional stack gate manufacturing method, in which (A) to (C) are cross-sectional views thereof, (a) to (c) are plan views thereof, and the cross-sectional views are X- of the plan view. The cross-sectional view at the X ′ line position is shown.

FIG. 2 is a diagram showing a state in which a second polycrystalline silicon film is anisotropically etched using a resist pattern for the purpose of separating in the bit line direction in a conventional method, (A) is a plan view, (B) is a sectional view taken along the line AA 'of (A), (C) is a sectional view taken along the line BB' of (A), and (D) is taken along the line CC 'of (A). It is sectional drawing in a line position.

FIG. 3 is a diagram showing a state in which an interlayer insulating film between a floating gate and a control gate is subsequently anisotropically etched by a conventional method, and FIG.
(A) is a sectional view taken along the line AA ', (B) is a sectional view taken along the line BB', and (C) is a sectional view taken along the line CC '. is there.

FIG. 4 is a diagram showing a state in which the first polycrystalline silicon film is further anisotropically etched by a conventional method,
2A is a sectional view taken along the line AA ′ of FIG. 2A, FIG. 2B is a sectional view taken along the line BB ′ of FIG. 2, and FIG. It is sectional drawing in a position.

5A and 5B are cross-sectional views showing a proposal for solving the problem of the conventional method, and FIG. 5C is a cross-sectional view showing the problem of (A).

6A and 6B are diagrams showing a process of forming an electrical isolation region of a floating gate array in a word line direction in one embodiment, FIG. 6A being a plan view and FIG. 6B being its HH ′.
It is sectional drawing in a line position.

FIG. 7 is a diagram showing a state in which a resist pattern for performing isolation in the bit line direction is formed on a second polycrystalline silicon film in one example, (A) is a plan view,
(B) is a cross-sectional view taken along the line II 'of (A), (C) is a cross-sectional view taken along the line JJ' of (A), and (D) is KK 'of (A). It is sectional drawing in a line position.

FIG. 8 is a diagram showing a state in which the second polycrystalline silicon film is etched in the same Example, FIG.
(A) is a cross-sectional view taken along the line II ', (B) is a cross-sectional view taken along the line JJ', and (C) is a cross-sectional view taken along the line KK '. is there.

FIG. 9 is a diagram showing a state in which an interlayer insulating film between a floating gate and a control gate is etched in the same Example, FIG. 9 (A) showing I shown in FIG. 7 (A).
FIG. 6B is a cross-sectional view taken along the line I-I ', FIG. 8B is a cross-sectional view taken along the line JJ', and FIG. 7C is a cross-sectional view taken along the line KK '.

FIG. 10 is a view showing a state in which the second polycrystalline silicon film is etched in the same Example, FIG.
(A) is a cross-sectional view taken along the line II ', (B) is a cross-sectional view taken along the line JJ', and (C) is a cross-sectional view taken along the line KK '. is there.

FIG. 11 is a diagram showing a state in which the stack gate is completed in the example, (A) is a plan view, (B) is a sectional view taken along line LL ′ of (A), and (C). Is a cross-sectional view taken along line MM 'in (A), and (D) is NN' in (A).
6A is a cross-sectional view taken along the line, FIG. 6E is a cross-sectional view taken along the line OO ′ in FIG. 6A, and FIG. 6F is a cross-sectional view taken along the line PP ′ in FIG.

[Explanation of symbols]

 2 Semiconductor Substrate 4 Thick Insulation Film for Device Isolation 6 Gate Insulation Film 8 First Polycrystalline Silicon Film 30 Resist Pattern 32 Opening 36 Silicon Dioxide

Claims (3)

[Claims] 1. An element isolation oxide film is selectively formed on a semiconductor substrate, and a floating gate made of polycrystalline silicon is formed on an active region of the substrate via a gate oxide film, and the floating gate is active. The floating gate array extending in the word line direction is electrically isolated from each other on the element isolation oxide film while extending from the region to the element isolation oxide film. In a stacked gate type non-volatile semiconductor memory device in which a continuous strip-shaped control gate that becomes a floating gate is formed with an insulating film interposed between the floating gate array and the floating gate Separation is done in silicon oxide and the silicon oxide and the floaty The nonvolatile semiconductor memory device having an oxygen concentration of the boundary between Gugeto polycrystalline silicon is characterized in that continuously changes. 2. A method for manufacturing a non-volatile semiconductor memory device, comprising forming a stack gate on a semiconductor substrate including the following steps (A) to (F). (A) A device isolation oxide film is selectively formed on a semiconductor substrate, a gate oxide film is formed on an active region of the substrate, and then a first floating gate is formed on the entire surface of the substrate.
Forming a polycrystalline silicon film, and (B) forming an opening in the isolation region for electrically isolating adjacent floating gates of the floating gate array in the word line direction on the element isolation oxide film. A step of forming a resist pattern, (C) a step of ion-implanting an ion species containing oxygen into the polycrystalline silicon film in the opening using the resist pattern as a mask, (D) a heat treatment after removing the resist pattern A step of selectively converting the ion-implanted region of the polycrystalline silicon film into an insulating film by performing (E) a step of forming an insulating film to be an interlayer insulating film between the floating gate and the control gate on the entire surface; (F) A second polycrystalline silicon film for the control gate is formed on the entire surface, and the second polycrystalline silicon film is formed by photolithography and etching. Crystal silicon film to form a stacked gate by patterning the insulating film and the first polycrystalline silicon film. 3. The ion species containing oxygen, which is implanted in the ion implantation step of step (C), is oxygen ion, NO ion,
The method for manufacturing a non-volatile semiconductor memory device according to claim 2, wherein the method is NO ₂ ions or N ₂ O ions.