JPH09213202A - Field emission type cold cathode device and manufacture thereof - Google Patents
Field emission type cold cathode device and manufacture thereofInfo
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- JPH09213202A JPH09213202A JP1744896A JP1744896A JPH09213202A JP H09213202 A JPH09213202 A JP H09213202A JP 1744896 A JP1744896 A JP 1744896A JP 1744896 A JP1744896 A JP 1744896A JP H09213202 A JPH09213202 A JP H09213202A
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- gate electrode
- film
- cold cathode
- field emission
- type semiconductor
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体プロセスを利
用した電界放出型冷陰極装置及びその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission cold cathode device using a semiconductor process and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体集積回路を中心に発達してきた微
細加工技術を用いて微小冷陰極装置を形成する方法の開
発が近年活発に進められている。これまでに、超高周波
数素子、フラットディスプレイ、光源、センサー等への
微小冷陰極装置の応用研究が行われている。そして、そ
の電子源の特徴を生かした、半導体の固体素子の限界を
越えるデバイスの開発への期待が寄せられている。2. Description of the Related Art In recent years, development of a method for forming a micro cold cathode device by using a fine processing technique developed mainly for semiconductor integrated circuits has been actively pursued. So far, application research of micro cold cathode devices for ultra-high frequency devices, flat displays, light sources, sensors, etc. has been conducted. Further, there are expectations for the development of a device that takes advantage of the characteristics of the electron source and goes beyond the limit of a semiconductor solid-state element.
【０００３】その典型的な例としてはＣ．Ａ．Ｓpindt
により提案された電界放出型冷陰極装置が知られてい
る。この電界放出型冷陰極装置の例を図９に示す。同図
に示すように、この装置は、Ｓｉ等からなる基板１上に
形成された、Ｍｏ等からなるエミッタ２、ＳｉＯ2 等か
らなる酸化膜３、Ｍｏ等からなるゲート電極４等を具備
する。なお、エミッタ２は、先端部ができるだけ鋭くな
るよう、縦断面がほぼ三角形となるように形成されてい
る。A typical example thereof is C.I. A. Spindt
A field emission type cold cathode device proposed by K.K. is known. An example of this field emission type cold cathode device is shown in FIG. As shown in the figure, this device is provided with an emitter 2 made of Mo or the like, an oxide film 3 made of SiO 2 or the like, a gate electrode 4 made of Mo or the like formed on a substrate 1 made of Si or the like. . The emitter 2 is formed to have a substantially triangular vertical cross section so that its tip portion is as sharp as possible.
【０００４】電界放出型エミッタの原理としてＦowler-
Ｎordheim の理論が用いられている。この理論によれ
ば、放出電流値は、エミッタ材料の仕事関数と電子を放
射する部分の電界強度とによって決まる。As a principle of field emission type Fowler-
The Nordheim theory is used. According to this theory, the emission current value is determined by the work function of the emitter material and the electric field strength of the part that emits electrons.
【０００５】放出電流を高める方法としては、エミッタ
の先端の曲率半径を小さくして電界強度を高める方法
と、エミッタ材料として親和力の小さい材料を用いるこ
とにより仕事関数を小さくする方法と、が用いられてい
る。As a method of increasing the emission current, there are used a method of decreasing the radius of curvature of the tip of the emitter to increase the electric field strength, and a method of decreasing the work function by using a material having a low affinity as the emitter material. ing.
【０００６】従来の電界放出型冷陰極装置の基本構造
は、金属或いは半導体を鋭く尖らせた電子放射部（エミ
ッタ）と、エミッタの先端部に強い電界を誘起させるゲ
ートとからなる。この様なエミッタ及びゲートの組合わ
せが、アレイ基板上に多数集積配置される。The basic structure of the conventional field emission type cold cathode device comprises an electron emitting portion (emitter) in which a metal or a semiconductor is sharply pointed, and a gate for inducing a strong electric field at the tip of the emitter. A large number of such combinations of emitters and gates are arranged on the array substrate.
【０００７】しかしながら、上述した従来の電界放出型
冷陰極装置及びその製造方法においては、以下の重要な
問題点がある。However, the above-mentioned conventional field emission type cold cathode device and its manufacturing method have the following important problems.
【０００８】従来の電界放出型冷陰極装置では、エミッ
タの形状に依存して電界集中させるため、エミッタ先端
部の成形時におけるナノメートルオーダーサイズの制御
が不可欠となる。しかし、現在の微細加工技術では、エ
ミッタの高さや先端部の形状等にはバラ付きが生じやす
く、エミッタの構造を均一化することが困難である。エ
ミッタ放射電流は極めて構造に対して敏感であるため、
エミッタの寸法にバラツキがあると、アレイの一部しか
動作しない状態が生じる。これは、電界放出電流の低下
等の問題につながる。In the conventional field emission type cold cathode device, since the electric field is concentrated depending on the shape of the emitter, it is indispensable to control the nanometer order size at the time of molding the tip of the emitter. However, current microfabrication technology tends to cause variations in the height of the emitter, the shape of the tip, and the like, and it is difficult to make the structure of the emitter uniform. Since the emitter emission current is extremely structure sensitive,
Variations in the dimensions of the emitters create a situation where only part of the array is active. This leads to problems such as a decrease in field emission current.
【０００９】また、エミッタアレイの形状に凹凸が存在
するため、その後にゲート電極を形成する際、エミッタ
先端とゲート電極との間の距離の制御が難しくなる。即
ち、プロセスの再現性及び歩留まりが悪くなる上、ＬＳ
Ｉのプレーナ技術との整合性に欠けることとなる。Further, since there are irregularities in the shape of the emitter array, it becomes difficult to control the distance between the tip of the emitter and the gate electrode when the gate electrode is subsequently formed. That is, the process reproducibility and the yield are deteriorated, and the LS
It will be inconsistent with I's planar technology.
【００１０】一方、親和力が小さいまたは負になるエミ
ッタ材料として、最近、ダイヤモンドの研究が行われて
いる。ダイヤモンドは親和力が小さい以外に、耐久性と
耐熱性等構造的に安定であることも優れたエミッタ材料
として有望である。この場合、平面型エミッタの形成も
可能であり、エミッタを尖らせるための加工は必ずしも
必要ではないが、以下のような問題点がある。On the other hand, diamond has recently been studied as an emitter material having a low or negative affinity. In addition to its low affinity, diamond is also a promising emitter material because of its structural stability such as durability and heat resistance. In this case, it is possible to form a planar emitter, and the processing for sharpening the emitter is not always necessary, but there are the following problems.
【００１１】現在の成膜技術では、ダイヤモンド薄膜が
Ｐ型しか形成できない。従って、Ｐ型ダイヤモンドの場
合、電子親和力が負であっても、仕事関数はフェルミレ
ベルから真空準位までの差であるから、この値が約５．
５ｅＶ程大きくなる。このため、十分な電界放出電流が
取れない。With the current film forming technology, only a P-type diamond thin film can be formed. Therefore, in the case of P-type diamond, even if the electron affinity is negative, the work function is the difference from the Fermi level to the vacuum level, so this value is about 5.
It becomes as large as 5 eV. Therefore, a sufficient field emission current cannot be obtained.
【００１２】[0012]
【発明が解決しようとする課題】上述の如く、従来の電
界放出型冷陰極は、エミッタ形状の再現性や均一性が低
く、ゲート電極等の形成プロセスの制御性が悪いため、
電界放出効率の低下や不均一化、プレーナ技術との整合
性が悪い等の多くの問題をかかえている。As described above, the conventional field emission type cold cathode has low reproducibility and uniformity of the emitter shape and poor controllability of the formation process of the gate electrode and the like.
It has many problems such as reduction of field emission efficiency, non-uniformity, and poor compatibility with planar technology.
【００１３】また、ダイヤモンドエミッタの場合、成膜
技術の限界によりＰ型しか形成できないため、負の電子
親和力にも係らず、仕事関数は十分な低い値がとれな
い。従って、低電圧駆動の大電流放出は実現できていな
い。Further, in the case of a diamond emitter, only the P-type can be formed due to the limitation of the film forming technique, so that the work function cannot take a sufficiently low value despite the negative electron affinity. Therefore, low voltage driving and large current emission have not been realized.
【００１４】本発明の目的は、低電圧駆動下でも電界放
出効率の向上及び均一化が可能な電界放出型冷陰極装置
及びその製造方法を提供することである。It is an object of the present invention to provide a field emission type cold cathode device capable of improving and uniforming the field emission efficiency even under low voltage driving, and a method for manufacturing the same.
【００１５】本発明の別の目的は、プレーナプロセスと
の整合性を図ることができる電界放出型冷陰極装置及び
その製造方法を提供することである。Another object of the present invention is to provide a field emission type cold cathode device and a method for manufacturing the same, which can achieve compatibility with a planar process.
【００１６】本発明の更に別の目的は、大面積化が可能
で量産性に富んだ電界放出型冷陰極装置及びその製造方
法を提供することである。Still another object of the present invention is to provide a field emission type cold cathode device which can have a large area and is highly producible, and a manufacturing method thereof.
【００１７】[0017]
【課題を解決するための手段】本発明の第１の視点は、
電界放出型冷陰極装置において、電子親和力の小さい半
導体からなるＰ型半導体膜と、前記Ｐ型半導体層上に配
設された絶縁膜と、前記Ｐ型半導体膜と前記絶縁膜と
は、それらの界面に対して交差する端面を有すること
と、前記端面の近傍において前記絶縁膜を介して前記Ｐ
型半導体膜と対向するゲート電極と、を具備し、前記ゲ
ート電極と前記Ｐ型半導体膜との間に前記ゲート電極が
正となるように電圧を付与することにより、前記ゲート
電極と対向する前記Ｐ型半導体膜の表面領域の仕事関数
を低下させ、前記端面に位置する前記表面領域の部分か
ら電子を電界放出させることを特徴とする。SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
In a field emission cold cathode device, a P-type semiconductor film made of a semiconductor having a low electron affinity, an insulating film provided on the P-type semiconductor layer, the P-type semiconductor film and the insulating film are Having an end face intersecting with the interface, and in the vicinity of the end face, the P
A gate electrode facing the gate-type semiconductor film, and a voltage is applied between the gate electrode and the P-type semiconductor film so that the gate electrode is positive, thereby facing the gate electrode. It is characterized in that the work function of the surface region of the P-type semiconductor film is lowered, and electrons are field-emitted from the portion of the surface region located at the end face.
【００１８】本発明の第２の視点は、第１の視点の電界
放出型冷陰極装置において、前記Ｐ型半導体膜が基板上
に配設され、前記基板は前記Ｐ型半導体膜、前記絶縁膜
及び前記ゲート電極を埋め込む溝を有し、前記端面が複
数個、同一平面上に配置されることを特徴とする。A second aspect of the present invention is the field emission type cold cathode device according to the first aspect, wherein the P-type semiconductor film is disposed on a substrate, and the substrate is the P-type semiconductor film and the insulating film. And a plurality of the end faces arranged on the same plane, the trench having a groove for burying the gate electrode.
【００１９】本発明の第３の視点は、第１または第２の
視点の電界放出型冷陰極装置において、前記端面が薄い
絶縁膜で被覆されることを特徴とする。A third aspect of the present invention is characterized in that, in the field emission cold cathode device according to the first or second aspect, the end face is covered with a thin insulating film.
【００２０】本発明の第４の視点は、第２の視点の電界
放出型冷陰極装置の製造方法において、前記基板上に前
記溝を形成する工程と、前記基板上に前記Ｐ型半導体
膜、前記絶縁膜、前記ゲート電極の夫々の材料膜を順に
形成する工程と、少なくとも、前記絶縁膜、前記ゲート
電極の夫々の材料膜をエッチングし、前記端面の複数個
を、同一平面上に露出させる工程と、を具備することを
特徴とする。According to a fourth aspect of the present invention, in the method for manufacturing a field emission cold cathode device according to the second aspect, the step of forming the groove on the substrate, the P-type semiconductor film on the substrate, A step of sequentially forming each material film of the insulating film and the gate electrode, and at least etching each material film of the insulating film and the gate electrode to expose a plurality of the end faces on the same plane. And a process.
【００２１】本発明においては、凸形エミッタを加工形
成するのではなく、積層技術を用いてダイヤモンド等の
薄膜を含むＭＯＳダイオードを構成し、同薄膜の端面の
表面領域をエミッタとしている。これにより、ナノメー
トルオーダーサイズのエミッタ層を制御よく形成するこ
とができる。In the present invention, instead of forming a convex emitter by machining, a MOS diode including a thin film of diamond or the like is formed by using a lamination technique, and the surface region of the end face of the thin film is used as an emitter. Thereby, the nanometer-order-sized emitter layer can be formed with good control.
【００２２】また、トレンチ型のＭＯＳ構造を利用して
プレーナ型エミッタアレイを形成すると、大面積化可能
なトレンチ型ＭＯＳダイオードの断面から電子を電界放
出させることができる。Further, when the planar type emitter array is formed by utilizing the trench type MOS structure, electrons can be field-emitted from the cross section of the trench type MOS diode whose area can be increased.
【００２３】また、電子親和力の小さいまたは負の半導
体からなるＰ型半導体に電界を付与し、その表面領域の
仕事関数を大幅に低減しているため、低電圧駆動の高効
率な電界放出特性を得ることができる。Further, since an electric field is applied to the P-type semiconductor made of a semiconductor having a small electron affinity or a negative electron affinity and the work function of the surface region thereof is significantly reduced, a highly efficient field emission characteristic of low voltage driving can be obtained. Obtainable.
【００２４】本発明におけるエミッタ材料としては、ダ
イヤモンド等の親和力の小さいまたは負の半導体、或い
はＳｉＣ等の親和力の小さい半導体を用いることができ
る。また、エミッタ材料としては、Ｐ型半導体以外にＮ
型半導体を用いることができる。半導体の成膜技術とし
ては、ＣＶＤ、ＭＢＥ等を用いることができる。As the emitter material in the present invention, a semiconductor having a low affinity or a negative affinity such as diamond, or a semiconductor having a low affinity such as SiC can be used. In addition to the P-type semiconductor, N is used as the emitter material.
Type semiconductors can be used. As a semiconductor film forming technique, CVD, MBE, or the like can be used.
【００２５】[0025]
【発明の実施の形態】図１は本発明の実施の形態に係る
電界放出型冷陰極装置を製造工程順に示す断面図であ
る。本実施の形態においては、ダイヤモンド薄膜を具備
するトレンチ型ＭＯＳ構造が利用される。以下、図１を
参照し、この電界放出型冷陰極装置の製造工程を説明す
る。1 is a sectional view showing a field emission type cold cathode device according to an embodiment of the present invention in the order of manufacturing steps. In this embodiment, a trench type MOS structure including a diamond thin film is used. The manufacturing process of this field emission cold cathode device will be described below with reference to FIG.
【００２６】先ず、通常の半導体ウェハの標準洗浄によ
り表面処理したＮ型Ｓｉ基板１１を用意する。なお、Ｓ
ｉ基板１１はＰ型としてもよい。次に、フォトリソグラ
フィによりパターニングしたレジストマスクを使用し、
基板１１をドライエッチングする。これにより、図１
（ａ）に示すように、多数の円柱状の凸部１２ａとこれ
を囲む溝１２ｂとを基板１１上に形成する。First, an N-type Si substrate 11 whose surface is treated by standard cleaning of a normal semiconductor wafer is prepared. Note that S
The i substrate 11 may be a P type. Next, using a resist mask patterned by photolithography,
The substrate 11 is dry-etched. As a result, FIG.
As shown in (a), a large number of cylindrical protrusions 12 a and grooves 12 b surrounding the protrusions 12 a are formed on the substrate 11.
【００２７】次に、図１（ｂ）に示すように、基板１１
全面上、即ち凸部１２ａ及び溝１２ｂの全体上にＣＶＤ
を用いて数μｍ厚さのダイヤモンド薄膜１３を成膜す
る。この際、ダイヤモンド薄膜１３はＰ型の導電型を有
することとなる。次に、図１（ｃ）に示すように、ダイ
ヤモンド薄膜１３上にＳｉＯ2 絶縁膜１４を蒸着法によ
り成膜する。そして、図１（ｄ）に示すように、絶縁膜
１４上にＣＶＤ法によりポリシリコン膜１５を形成す
る。Next, as shown in FIG. 1B, the substrate 11
CVD on the entire surface, that is, the entire convex portion 12a and groove 12b.
Is used to form a diamond thin film 13 having a thickness of several μm. At this time, the diamond thin film 13 has a P-type conductivity type. Next, as shown in FIG. 1C, a SiO 2 insulating film 14 is formed on the diamond thin film 13 by a vapor deposition method. Then, as shown in FIG. 1D, a polysilicon film 15 is formed on the insulating film 14 by the CVD method.
【００２８】次に、ドライエッチングを用いてポリシリ
コン膜１５及びＳｉＯ2 絶縁膜１４をエッチングし、ダ
イヤモンド薄膜１３が露出したところでエッチングを停
止し、図１（ｅ）に示すように、ゲート絶縁膜１６及び
ゲート電極１７を形成する。ここで、ダイヤモンド薄膜
１３、ゲート絶縁膜１６及びゲート電極１７の露出端面
２０は、同一平面上にあり且つ膜１３、１６の界面に直
交する。最後に、端面２０に対して、真空雰囲気を介し
て対向するように、アノード電極１８を配設する。図２
は図１図示の工程により製造された電界放出型冷陰極装
置を示す部分断面斜視図である。Next, the polysilicon film 15 and the SiO 2 insulating film 14 are etched by dry etching, the etching is stopped when the diamond thin film 13 is exposed, and as shown in FIG. 1E, the gate insulating film is formed. 16 and the gate electrode 17 are formed. Here, the exposed end faces 20 of the diamond thin film 13, the gate insulating film 16, and the gate electrode 17 are on the same plane and are orthogonal to the interface between the films 13 and 16. Finally, the anode electrode 18 is arranged so as to face the end surface 20 with a vacuum atmosphere therebetween. FIG.
FIG. 2 is a partial cross-sectional perspective view showing a field emission cold cathode device manufactured by the process shown in FIG. 1.
【００２９】図１及び図２図示の電界放出型冷陰極装置
においては、ゲート電極１７が正となるようにゲート電
極１７と基板１１との間に電圧が印加されると、ダイヤ
モンド薄膜１３とゲート絶縁膜１６と界面に沿ったダイ
ヤモンド薄膜１３の表面領域の仕事関数が低下する。表
面領域の仕事関数は、ダイヤモンド薄膜１３の電子親和
力及び電極１７と基板１１との間の電圧に依存し、ゼロ
近傍まで低減することができる。また、薄膜１３の電子
親和力が負ではなく、小さいが正の場合は、表面領域の
導電型を反転させ、Ｎ型とすることができる。従って、
アノード電極１８にゲート電極１７よりも高い電位が印
加されると、仕事関数が低下したダイヤモンド薄膜１３
の表面領域の端面２０上の部分から、図１（ｅ）中に矢
印で示すように、電子が放出される。In the field emission type cold cathode device shown in FIGS. 1 and 2, when a voltage is applied between the gate electrode 17 and the substrate 11 so that the gate electrode 17 becomes positive, the diamond thin film 13 and the gate are The work function of the surface region of the diamond thin film 13 along the interface with the insulating film 16 decreases. The work function of the surface region depends on the electron affinity of the diamond thin film 13 and the voltage between the electrode 17 and the substrate 11, and can be reduced to near zero. When the electron affinity of the thin film 13 is not negative but small but positive, the conductivity type of the surface region can be inverted to make it N-type. Therefore,
When a higher potential than that of the gate electrode 17 is applied to the anode electrode 18, the diamond thin film 13 whose work function is lowered
Electrons are emitted from the portion of the surface region of the end face 20 on the end face 20 as indicated by an arrow in FIG.
【００３０】図３はダイヤモンド等の負の親和力をもつ
Ｐ型半導体のエネギーバンドの概念を示す。同図におい
て、Ｅｏは真空準位を表わし、Ｅｆはフェルミレベルを
表わす。また、ＥｃとＥｖと夫々伝導帯の底と価電帯の
上限とを表わし、Ｅｉは禁止帯の中央を表わす。仕事関
数ＷはＥｏからＥｆまでのエネルギー差を表わす。図３
より、Ｐ型半導体の場合、負の親和力をもつにも係ら
ず、仕事関数Ｗは依然として大きいことがわかる。FIG. 3 shows the concept of the energy band of a P-type semiconductor having a negative affinity such as diamond. In the figure, Eo represents a vacuum level and Ef represents a Fermi level. Ec and Ev represent the bottom of the conduction band and the upper limit of the valence band, respectively, and Ei represents the center of the forbidden band. The work function W represents the energy difference from Eo to Ef. FIG.
From the above, it can be seen that in the case of a P-type semiconductor, the work function W is still large despite having a negative affinity.
【００３１】図４は図１（ｅ）に示す構成におけるエネ
ルギーバンドの概念を示す。図４に示すように、このＭ
ＯＳ構造は半導体層３１（図１では膜１３）、絶縁膜３
２（図１では膜１６）及びゲート電極３３（図１では電
極１７）により構成されている。半導体層３１に電界が
かかると、半導体層３１と絶縁層３２との界面に沿っ
た、半導体層３１表面内の厚みが数ナノメートルオーダ
ーの表面領域３４の仕事関数が低下する。この時、図４
より、フェルミレベルが伝導帯の底より上に上がり、仕
事関数が大幅に低減されることがわかる。従って、電界
放出に必要な駆動電圧は半導体ＭＯＳダイオードの動作
電圧と同レベルのわずか数ボルトとなる。また、アノー
ド電圧も非常に低い電圧で放出電流を収集することがで
きる。FIG. 4 shows the concept of the energy band in the structure shown in FIG. As shown in FIG.
The OS structure includes the semiconductor layer 31 (the film 13 in FIG. 1) and the insulating film 3.
2 (membrane 16 in FIG. 1) and gate electrode 33 (electrode 17 in FIG. 1). When an electric field is applied to the semiconductor layer 31, the work function of the surface region 34 along the interface between the semiconductor layer 31 and the insulating layer 32 whose thickness in the surface of the semiconductor layer 31 is on the order of several nanometers is lowered. At this time, FIG.
It can be seen that the Fermi level rises above the bottom of the conduction band and the work function is significantly reduced. Therefore, the driving voltage required for field emission is only a few volts, which is the same level as the operating voltage of the semiconductor MOS diode. Also, the emission voltage can be collected with a very low anode voltage.
【００３２】図５は本発明の別の実施の形態に係る電界
放出型冷陰極装置を示す部分断面斜視図である。FIG. 5 is a partial sectional perspective view showing a field emission type cold cathode device according to another embodiment of the present invention.
【００３３】この冷陰極装置を製造する場合、先ず、Ｎ
型或いはＰ型のＳｉ基板４１に、断面がＶ字形の複数の
溝を平行に形成する。次に、ダイヤモンド薄膜４２をＣ
ＶＤにより全面に成膜する。次に、ＳｉＯ2 膜を全面に
堆積成膜すると共にエッチングによりパターニングし、
ゲート絶縁膜４３を形成する。次に、電極材料膜、例え
ばポリシリコン膜を全面に堆積成膜する共にエッチング
によりパターニングし、ゲート電極４４を形成する。こ
こで、ダイヤモンド薄膜４２及びゲート絶縁膜４３の界
面に交差するように、膜４２、４３及びゲート電極４４
の端面４６が露出する。最後に、端面４６に対して、真
空雰囲気を介して対向するように、アノード電極４５を
配設する。When manufacturing this cold cathode device, first, N
A plurality of V-shaped grooves are formed in parallel on the Si substrate 41 of the mold or P type. Next, the diamond thin film 42 is replaced with C
A film is formed on the entire surface by VD. Next, a SiO 2 film is deposited and formed on the entire surface and patterned by etching,
The gate insulating film 43 is formed. Next, an electrode material film, for example, a polysilicon film is deposited and formed on the entire surface and is patterned by etching to form a gate electrode 44. Here, the films 42 and 43 and the gate electrode 44 are arranged so as to intersect the interface between the diamond thin film 42 and the gate insulating film 43.
The end surface 46 of is exposed. Finally, the anode electrode 45 is arranged so as to face the end surface 46 via a vacuum atmosphere.
【００３４】図５図示の電界放出型冷陰極装置において
も、ゲート電極４４が正となるようにゲート電極４４と
基板４１との間に電圧が印加されると、ダイヤモンド薄
膜４２とゲート絶縁膜４３と界面に沿ったダイヤモンド
薄膜４２の表面領域の仕事関数が低下する。従って、ア
ノード電極４５にゲート電極４４よりも高い電位が印加
されると、仕事関数が低下したダイヤモンド薄膜４２の
表面領域の端面４６上の部分から、図５中に矢印で示す
ように、電子が放出される。Also in the field emission type cold cathode device shown in FIG. 5, when a voltage is applied between the gate electrode 44 and the substrate 41 so that the gate electrode 44 becomes positive, the diamond thin film 42 and the gate insulating film 43 are formed. And the work function of the surface region of the diamond thin film 42 along the interface decreases. Therefore, when a potential higher than that of the gate electrode 44 is applied to the anode electrode 45, electrons are emitted from the portion on the end face 46 of the surface region of the diamond thin film 42 having a reduced work function, as indicated by an arrow in FIG. Is released.
【００３５】図６は本発明の更に別の実施の形態に係る
電界放出型冷陰極装置を示す断面図である。FIG. 6 is a sectional view showing a field emission type cold cathode device according to still another embodiment of the present invention.
【００３６】この冷陰極装置を製造する場合、先ず、Ｎ
型或いはＰ型のＳｉ基板４１に、断面がＶ字形の複数の
溝を平行に形成する。次に、ダイヤモンド薄膜４２をＣ
ＶＤにより全面に成膜する。次に、厚みが数ナノメート
ルの薄いＳｉＯ2 絶縁膜５３を全面に堆積成膜する。最
後に、絶縁膜５３の尾根に対して、真空雰囲気を介して
対向するように引出し電極５４を配設する。When manufacturing this cold cathode device, first, N
A plurality of V-shaped grooves are formed in parallel on the Si substrate 41 of the mold or P type. Next, the diamond thin film 42 is replaced with C
A film is formed on the entire surface by VD. Next, a thin SiO 2 insulating film 53 having a thickness of several nanometers is deposited and formed on the entire surface. Finally, the extraction electrode 54 is arranged so as to face the ridge of the insulating film 53 via a vacuum atmosphere.
【００３７】図６図示の電界放出型冷陰極装置において
は、引出し電極５４が図５図示の構造のゲート電極４４
及びアノード電極４５の両者の役割を兼ねる。引出し電
極５４が正となるように電極５４と基板４１との間に電
圧が印加されると、ダイヤモンド薄膜４２と絶縁膜５３
と界面に沿ったダイヤモンド薄膜４２の表面領域の仕事
関数が低下する。そして、Ｓｉ基板４１の尾根に隣接す
るダイヤモンド薄膜４２と絶縁膜５３との界面の端面５
６から、図６中に矢印で示すように、絶縁膜５３を通過
して電子が放出される。また、ダイヤモンド薄膜４２上
に薄いＳｉＯ2膜５３が形成されているため、ダイヤモ
ンドの表面が理想的となり、表面準位を大幅に低減する
ことができる。In the field emission cold cathode device shown in FIG. 6, the extraction electrode 54 has the gate electrode 44 having the structure shown in FIG.
And both of the anode electrode 45. When a voltage is applied between the electrode 54 and the substrate 41 so that the extraction electrode 54 becomes positive, the diamond thin film 42 and the insulating film 53
And the work function of the surface region of the diamond thin film 42 along the interface decreases. Then, the end surface 5 of the interface between the diamond thin film 42 and the insulating film 53 adjacent to the ridge of the Si substrate 41.
6, electrons are emitted through the insulating film 53, as indicated by the arrow in FIG. Further, since the thin SiO 2 film 53 is formed on the diamond thin film 42, the surface of the diamond becomes ideal, and the surface level can be significantly reduced.
【００３８】図７は本発明の更に別の実施の形態に係る
電界放出型冷陰極装置を示す断面図である。FIG. 7 is a sectional view showing a field emission type cold cathode device according to still another embodiment of the present invention.
【００３９】この冷陰極装置を製造する場合、先ず、図
１の（ａ）〜（ｅ）までと同様な工程を経て図１（ｅ）
に示すような中間構造物を形成する。次に、ポリシリコ
ン膜をエッチングし、ゲート電極６７を形成する。この
際、ゲート絶縁膜６６となる薄いＳｉＯ2 酸化膜をエッ
チングせず、ダイヤモンド薄膜１３を覆った状態のまま
に残す。この場合、ＳｉＯ2 酸化膜６６の厚みは数ナノ
メートルの薄いものとする。In the case of manufacturing this cold cathode device, first, the steps similar to those in FIGS.
An intermediate structure as shown in is formed. Next, the polysilicon film is etched to form the gate electrode 67. At this time, the thin SiO 2 oxide film serving as the gate insulating film 66 is not etched, and the diamond thin film 13 is left covered. In this case, the thickness of the SiO 2 oxide film 66 is as thin as several nanometers.
【００４０】図７図示の電界放出型冷陰極装置において
も、ゲート電極６７が正となるようにゲート電極６７と
基板１１との間に電圧が印加されると共に、アノード電
極６８にゲート電極６７よりも高い電位が印加される
と、図７中に矢印で示すように、ゲート絶縁膜６６を通
過して電子が放出される。ダイヤモンド薄膜１３上にＳ
ｉＯ2 膜６６が存在しているため、ダイヤモンド薄膜１
３の断面は表面準位のない理想状態となる。従って、よ
り低電圧駆動と高放出効率とが実現できる。Also in the field emission type cold cathode device shown in FIG. 7, a voltage is applied between the gate electrode 67 and the substrate 11 so that the gate electrode 67 becomes positive, and the anode electrode 68 is applied to the anode electrode 68 by the gate electrode 67. When a high potential is applied, electrons are emitted through the gate insulating film 66 as shown by the arrow in FIG. S on the diamond thin film 13
Since the iO 2 film 66 exists, the diamond thin film 1
The cross section of 3 is in an ideal state with no surface states. Therefore, lower voltage driving and higher emission efficiency can be realized.
【００４１】図８は本発明の更に別の実施の形態に係る
電界放出型冷陰極装置を示す部分断面斜視図である。FIG. 8 is a partial cross-sectional perspective view showing a field emission type cold cathode device according to still another embodiment of the present invention.
【００４２】この冷陰極装置を製造する場合、先ず、Ｎ
型或いはＰ型のＳｉ基板７１上に、ダイヤモンド薄膜、
ＳｉＯ2 膜、及び電極材料膜を順に形成する。次に、エ
ッチングにより、これらの膜を順に選択的に除去すると
共に、Ｓｉ基板７１に断面がＵ字形の複数の溝を平行に
形成する。これにより、Ｓｉ基板７１の凸部上に、ダイ
ヤモンド薄膜７２、ゲート絶縁膜７３、ゲート電極７４
が積層された構造が得られる。最後に、Ｓｉ基板７１の
凸部に対して、真空雰囲気を介して対向するように、ア
ノード電極７５を配設する。When manufacturing this cold cathode device, first, N
Diamond film,
A SiO 2 film and an electrode material film are sequentially formed. Next, these films are selectively removed in order by etching, and a plurality of grooves having a U-shaped cross section are formed in parallel on the Si substrate 71. As a result, the diamond thin film 72, the gate insulating film 73, and the gate electrode 74 are formed on the convex portion of the Si substrate 71.
A laminated structure is obtained. Finally, the anode electrode 75 is arranged so as to face the convex portion of the Si substrate 71 via a vacuum atmosphere.
【００４３】図８図示の電界放出型冷陰極装置において
も、ゲート電極７４が正となるようにゲート電極７４と
基板７１との間に電圧が印加されると共に、アノード電
極７５にゲート電極７４よりも高い電位が印加される
と、ダイヤモンド薄膜７２とゲート絶縁膜７３との界面
の端面７６上の部分から、図８中に矢印で示すように、
電子が放出される。Also in the field emission type cold cathode device shown in FIG. 8, a voltage is applied between the gate electrode 74 and the substrate 71 so that the gate electrode 74 becomes positive, and the anode electrode 75 is applied to the anode electrode 75 by the gate electrode 74. When a high potential is applied, as shown by the arrow in FIG. 8, from the portion on the end face 76 at the interface between the diamond thin film 72 and the gate insulating film 73,
Electrons are emitted.
【００４４】[0044]
【発明の効果】本発明によれば、従来に比べて非常に小
さい仕事関数を有するエミッタを具備し、低電圧駆動と
高効率電界放出が可能な電界放出型冷陰極装置を実現で
きる。また、エミッタの凸形状加工なしに、プレーナ型
で量産性に富んだ大面積な電界放出型冷陰極装置を提供
することができる。According to the present invention, it is possible to realize a field emission type cold cathode device which has an emitter having a work function much smaller than that of a conventional one and is capable of low voltage driving and high efficiency field emission. Further, it is possible to provide a planar type large-area field-emission cold cathode device that is highly producible and mass-produced without processing the convex shape of the emitter.
【図１】本発明の実施の形態に係る電界放出型冷陰極装
置を製造工程順に示す断面図。FIG. 1 is a cross-sectional view showing a field emission cold cathode device according to an embodiment of the present invention in the order of manufacturing steps.
【図２】図１図示の工程により製造された電界放出型冷
陰極装置を示す部分断面斜視図。FIG. 2 is a partial sectional perspective view showing a field emission cold cathode device manufactured by the process shown in FIG.
【図３】負の親和力をもつＰ型半導体のエネギーバンド
の概念図。FIG. 3 is a conceptual diagram of an energy band of a P-type semiconductor having a negative affinity.
【図４】図１（ｅ）に示す構成におけるエネルギーバン
ドの概念図。FIG. 4 is a conceptual diagram of energy bands in the configuration shown in FIG.
【図５】本発明の別の実施の形態に係る電界放出型冷陰
極装置を示す部分断面斜視図。FIG. 5 is a partial sectional perspective view showing a field emission cold cathode device according to another embodiment of the present invention.
【図６】本発明の更に別の実施の形態に係る電界放出型
冷陰極装置を示す断面図。FIG. 6 is a sectional view showing a field emission type cold cathode device according to still another embodiment of the present invention.
【図７】本発明の更に別の実施の形態に係る電界放出型
冷陰極装置を示す断面図。FIG. 7 is a sectional view showing a field emission type cold cathode device according to still another embodiment of the present invention.
【図８】本発明の更に別の実施の形態に係る電界放出型
冷陰極装置を示す部分断面斜視図。FIG. 8 is a partial sectional perspective view showing a field emission cold cathode device according to still another embodiment of the present invention.
【図９】従来の電界放出型冷陰極装置を示す断面図。FIG. 9 is a sectional view showing a conventional field emission cold cathode device.
１１、４１、７１…基板、１３、４２、７２…ダイヤモ
ンド薄膜、１６、４３、６６、７３…ゲート絶縁膜、１
７、４４、６７、７４…ゲート電極、１８、４５、６
８、７５…アノード電極、２０、４６、５６、７６…端
面、５３…薄い絶縁膜、５４…引出し電極。11, 41, 71 ... Substrate, 13, 42, 72 ... Diamond thin film, 16, 43, 66, 73 ... Gate insulating film, 1
7, 44, 67, 74 ... Gate electrodes, 18, 45, 6
8, 75 ... Anode electrode, 20, 46, 56, 76 ... End face, 53 ... Thin insulating film, 54 ... Extraction electrode.
Claims (4)
導体膜と、 前記Ｐ型半導体層上に配設された絶縁膜と、前記Ｐ型半
導体膜と前記絶縁膜とは、それらの界面に対して交差す
る端面を有することと、 前記端面の近傍において前記絶縁膜を介して前記Ｐ型半
導体膜と対向するゲート電極と、 を具備し、前記ゲート電極と前記Ｐ型半導体膜との間に
前記ゲート電極が正となるように電圧を付与することに
より、前記ゲート電極と対向する前記Ｐ型半導体膜の表
面領域の仕事関数を低下させ、前記端面に位置する前記
表面領域の部分から電子を電界放出させることを特徴と
する電界放出型冷陰極装置。1. A P-type semiconductor film made of a semiconductor having a low electron affinity, an insulating film provided on the P-type semiconductor layer, and the P-type semiconductor film and the insulating film with respect to an interface between them. And a gate electrode facing the P-type semiconductor film via the insulating film in the vicinity of the end face, wherein the gate electrode and the P-type semiconductor film are provided between the gate electrode and the P-type semiconductor film. By applying a voltage so that the gate electrode becomes positive, the work function of the surface region of the P-type semiconductor film facing the gate electrode is lowered, and electrons are generated from the surface region portion located at the end face. A field-emission cold cathode device characterized by emitting light.
記基板は前記Ｐ型半導体膜、前記絶縁膜及び前記ゲート
電極を埋め込む溝を有し、前記端面が複数個、同一平面
上に配置されることを特徴とする請求項１に記載の電界
放出型冷陰極装置。2. The P-type semiconductor film is disposed on a substrate, and the substrate has a groove for filling the P-type semiconductor film, the insulating film and the gate electrode, and a plurality of the end faces are on the same plane. The field emission cold cathode device according to claim 1, wherein
特徴とする請求項１または２に記載の電界放出型冷陰極
装置。3. The field emission type cold cathode device according to claim 1, wherein the end face is covered with a thin insulating film.
ト電極の夫々の材料膜を順に形成する工程と、 少なくとも、前記絶縁膜、前記ゲート電極の夫々の材料
膜をエッチングし、前記端面の複数個を、同一平面上に
露出させる工程と、 を具備することを特徴とする請求項２に記載の電界放出
型冷陰極装置の製造方法。4. A step of forming the groove on the substrate, a step of sequentially forming material films of the P-type semiconductor film, the insulating film, and the gate electrode on the substrate, at least the insulating film. 3. The field emission type cold cathode device according to claim 2, further comprising the step of etching the film and each material film of the gate electrode to expose a plurality of the end faces on the same plane. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1744896A JP3320603B2 (en) | 1996-02-02 | 1996-02-02 | Field emission cold cathode device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1744896A JP3320603B2 (en) | 1996-02-02 | 1996-02-02 | Field emission cold cathode device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09213202A true JPH09213202A (en) | 1997-08-15 |
| JP3320603B2 JP3320603B2 (en) | 2002-09-03 |
Family
ID=11944312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1744896A Expired - Fee Related JP3320603B2 (en) | 1996-02-02 | 1996-02-02 | Field emission cold cathode device and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP3320603B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100296710B1 (en) * | 1997-09-18 | 2001-08-07 | 오길록 | Method of manufacturing a diamond vacuum microelectronic device |
| KR100575632B1 (en) * | 1999-06-12 | 2006-05-03 | 엘지전자 주식회사 | Field Emission Display Driving with Radio Frequency |
| JP2009054372A (en) * | 2007-08-24 | 2009-03-12 | Nec Lighting Ltd | Field emission type cathode and field emission type lamp |
| CN111627873A (en) * | 2020-04-17 | 2020-09-04 | 柯文政 | Diamond film conductive layer structure with high heat conductivity and manufacturing method thereof |
-
1996
- 1996-02-02 JP JP1744896A patent/JP3320603B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100296710B1 (en) * | 1997-09-18 | 2001-08-07 | 오길록 | Method of manufacturing a diamond vacuum microelectronic device |
| KR100575632B1 (en) * | 1999-06-12 | 2006-05-03 | 엘지전자 주식회사 | Field Emission Display Driving with Radio Frequency |
| JP2009054372A (en) * | 2007-08-24 | 2009-03-12 | Nec Lighting Ltd | Field emission type cathode and field emission type lamp |
| CN111627873A (en) * | 2020-04-17 | 2020-09-04 | 柯文政 | Diamond film conductive layer structure with high heat conductivity and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3320603B2 (en) | 2002-09-03 |
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