JPH09191087A - Thin film capacitor and its manufacture - Google Patents
Thin film capacitor and its manufactureInfo
- Publication number
- JPH09191087A JPH09191087A JP8003633A JP363396A JPH09191087A JP H09191087 A JPH09191087 A JP H09191087A JP 8003633 A JP8003633 A JP 8003633A JP 363396 A JP363396 A JP 363396A JP H09191087 A JPH09191087 A JP H09191087A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- type oxide
- dielectric
- perovskite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 239000003990 capacitor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000000470 constituent Substances 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 44
- 239000002994 raw material Substances 0.000 abstract description 17
- 238000004544 sputter deposition Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 229910002370 SrTiO3 Inorganic materials 0.000 abstract 3
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 abstract 2
- 229910002353 SrRuO3 Inorganic materials 0.000 abstract 1
- 229910004121 SrRuO Inorganic materials 0.000 description 15
- 229910002367 SrTiO Inorganic materials 0.000 description 11
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 11
- 229910002347 SrOx Inorganic materials 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 239000012159 carrier gas Substances 0.000 description 5
- 230000005284 excitation Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 229910004356 Ti Raw Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910016062 BaRuO Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910016063 BaPb Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Inorganic Compounds Of Heavy Metals (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、薄膜キャパシタの
構造と、その製造方法に関するものである。
【０００２】
【従来の技術】１Ｇビット以上の次世代高密度ＤＲＡＭ
用容量膜に適用するために、誘電特性、絶縁性、化学的
安定性に優れたＳｒＴｉＯ3 、（Ｂａ，Ｓｒ）Ｔｉ
Ｏ3 、（Ｐｂ，Ｚｒ）ＴｉＯ3 等のペロブスカイト型酸
化物誘電体薄膜の研究開発が行われている。同時に、容
量部の面積を拡大するために、立体的な加工が容易な下
部電極材料の検討も重要な課題となっている。ＲｕＯ2
は室温で４０μΩｃｍの低抵抗率を有し、加えてＯ2 ＋
ＣＦ4 プラズマによるドライエッチングが可能であるこ
とから（ジャパニーズ・ジャーナル・オブ・アプライド
・フィジクス、３１巻、１３５頁、１９９２年（Ｓ．Ｓ
ａｉｔｏ ｅｔ ａｌ．，Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈ
ｙｓ．３１，１３５，（１９９２））を参照）、高密度
ＤＲＡＭ用下部電極として期待されている。
【０００３】以下、このＲｕＯ2 等の導電性酸化物を薄
膜キャパシタの下部電極等に適用した従来例を示す。
【０００４】第１の従来例として、電極と、Ｐｂを組成
に含むペロブスカイト型強誘電体膜とで構成されるキャ
パシタにおいて、電極として導電性を有するペロブスカ
イト型酸化物（例えば、ＢａＰｂＯ3 またはＢａＰｂ
1-x Ｂｉx Ｏ3 ）またはＲｕＯ2 を用いることを特徴と
する発明（特開平５−２３４８０９号公報）がある。
【０００５】第２の従来例として下部電極としてＲｕＯ
2 を用い、この上に（Ｂａ，Ｓｒ）ＴｉＯ3 をスパッタ
法により成膜した報告がある（アプライド・フィジクス
・レターズ、６４巻、２９６７頁、１９９４年（Ｋ．Ｔ
ａｋｅｍｕｒａ ｅｔ ａｌ．，Ａｐｐｌ．Ｐｈｙｓ．
Ｌｅｔｔ．６４，２９６７，（１９９４））。
【０００６】第３の従来例として、基板上に形成された
第１の電極と、前記第１の電極上に形成された第２の電
極とを少なくとも有する半導体装置において、前記第１
もしくは第２の電極と強誘電体膜との間の少なくとも一
つの間に、酸化物層を介在させたことを特徴とする半導
体装置という発明がある（特開平４−２０６８７０号公
報）。この発明の実施例では、電極と強誘電体膜の間の
酸化物層としてＳｒＴｉＯ3 、ＢａＴｉＯ3 、ＰｂＬａ
ＴｉＯ3 が用いられている。酸化物層の膜厚は１０ｎｍ
以下としている。この技術では、ＳｉとＳｒＴｉＯ3 間
の緩衝層としてＳｒＲｕＯ3 、ＣａＲｕＯ3 用いる検討
も行われている（平谷ら、「酸化物薄膜の結晶工学」
（応用物理学会結晶工学分科会第１１回結晶工学シンポ
ジウム）、２３頁、１９９５年）。
【０００７】
【発明が解決しようとする課題】第１、２の従来例にお
けるＲｕＯ2 を下部電極に用いた場合についての課題を
説明する。一般に、ＣＶＤ、スパッタ法等でペロブスカ
イト型酸化物誘電体薄膜を成膜するためには、６００℃
以上の高温が必要である。しかしながら、ＲｕＯ2 電極
上にこのような高温でペロブスカイト型酸化物誘電体を
成膜または熱処理すると、誘電体膜中へのＲｕの拡散が
起こる（特にＣＶＤ法による成膜において顕著に生じ
る）。Ｒｕが酸化物誘電体薄膜中に混入すると誘電体薄
膜の誘電率、リーク電流が著しく悪化するという問題が
生じる。
【０００８】第３の従来例は電極と強誘電体膜の間にＳ
ｒＴｉＯ3 、ＢａＴｉＯ3 、ＰｂＬａＴｉＯ3 等の酸化
物を設けるというものであるが、これらは低誘電率層と
なりキャパシタ全体の誘電率を下げる原因となる。誘電
率低下を緩和するために、この酸化物層の厚さを１０ｎ
ｍ以下に厳密に制御する工程が加わり、キャパシタの量
産性が低下する。
【０００９】本発明の目的は、ＲｕＯ2 を下部電極に用
いて、誘電率、リーク電流特性、及び量産性に優れたペ
ロブスカイト型酸化物誘電体薄膜キャパシタを提供する
ことにある。
【００１０】
【課題を解決するための手段】本発明は、少なくとも下
部電極と、上部電極と、両電極に挟持された誘電体薄膜
とからなる薄膜キャパシタにおいて、前記下部電極がＲ
ｕＯ2 からなり、前記誘電体薄膜がペロブスカイト型酸
化物からなり、かつ該下部電極と該誘電体薄膜との界面
に該誘電体薄膜とは異なる材料よりなりＲｕを含むペロ
ブスカイト型酸化物層を有することを特徴とする薄膜キ
ャパシタである。また、該ペロブスカイト型酸化物を構
成するＲｕ以外の金属原料を下部電極であるＲｕＯ2 上
に供給することによってＲｕを含むペロブスカイト型酸
化物層を形成する工程を含むことを特徴とする薄膜キャ
パシタの製造方法である。
【００１１】ＳｒＲｕＯ3 等のＲｕを含むペロブスカイ
ト型酸化物とＳｒＴｉＯ3 等のペロブスカイト型酸化物
誘電体は同じ結晶構造を有する。さらに、ＳｒＲｕＯ3
とＳｒＴｉＯ3 の格子定数は非常に近い（ＳｒＲｕ
Ｏ3 ：０．３９３ｎｍ、ＳｒＴｉＯ3 ：０．３９０５ｎ
ｍ）。したがって、ＳｒＲｕＯ3 等のペロブスカイト型
酸化物層を介して成膜されたペロブスカイト型酸化物誘
電体の結晶性は、ルチル構造であるＲｕＯ2 上に直接成
膜するよりもはるかに向上する。さらに、両者は格子整
合することから、酸化物誘電体と酸化物層との界面にお
ける反応も抑制され、酸化物誘電体薄膜中へのＲｕの混
入が抑制される。また、Ｒｕを含むペロブスカイト型酸
化物は非常に低抵抗な導電性を示すことから、低誘電率
層にはならない。したがって、この酸化物の厚さに制限
はない。さらに、本発明の製造方法を用いれば、Ｒｕを
含むペロブスカイト型酸化物をスタック状に微細加工さ
れたＲｕＯ2 上に選択的に形成することができるため、
Ｒｕを含むペロブスカイト型酸化物を形成後に各下部電
極間を電気的に分離するための微細加工を行う必要がな
い。
【００１２】以上のことから、ＲｕＯ2 を下部電極に用
いて、誘電率、リーク電流特性、及び量産性に優れたペ
ロブスカイト型酸化物誘電体薄膜キャパシタを提供する
ことができる。
【００１３】
【発明の実施の形態】
（実施例１）以下、本発明の実施例１について、図１を
参照しながら説明する。図１は本発明の実施例１に関わ
る薄膜キャパシタの断面図である。
【００１４】スパッタ法によりＳｉ基板５上にＲｕＯ2
とＳｉの反応を防ぐバリア層（ＴｉＮ）４を５０ｎｍ、
下部電極（ＲｕＯ2 ）２を２００ｎｍ積層した。
【００１５】次に、Ｒｕを含むペロブスカイト型酸化物
層１としてＳｒＲｕＯ3 を、ウエハを６００℃に加熱し
た状態で、スパッタ法により形成した。膜厚は特に制限
はないがこの例においては５０ｎｍとした。
【００１６】このウエハをＥｌｅｃｔｒｏｎ Ｃｙｃｌ
ｏｔｒｏｎ Ｒｅｓｏｎａｎｃｅ（ＥＣＲ）−ＣＶＤ装
置成膜室に導入した。ウエハ温度を４５０℃とし、Ｓｒ
原料であるＳｒ（ＤＰＭ）2 、Ｔｉ原料であるＴｉ（ｉ
−ＯＣ3 Ｈ7 ）4 （ＴＩＰ）、Ｏ2 プラズマを供給し、
ＳｒＲｕＯ3 層１上にペロブスカイト型酸化物誘電体３
としてＳｒＴｉＯ3 ２を５０ｎｍ成膜した。Ｓｒ（ＤＰ
Ｍ）2 の原料温度は１９０℃、流量は７０ｓｃｃｍ、Ｔ
ＩＰ温度は３６℃、流量は７０ｓｃｃｍ（キャリアガス
はＡｒ）、プラズマ励起マイクロ波パワーは６００Ｗ、
成膜室圧力は１Ｐａ、堆積速度は１．０ｎｍ／ｍｉｎで
あった。ＥＣＲ−ＣＶＤ法によれば、４５０℃という低
温においてもペロブスカイト構造を有するＳｒＴｉＯ3
を成膜可能である（山口ら、第４１回応用物理学関係連
合講演会予稿集、４１０頁、１９９４年を参照）。
【００１７】ＳｒＴｉＯ3 膜３を成膜後、ウエハをＣＶ
Ｄ成膜室から取り出し、スパッタ法により上部電極６と
してＡｕをＳｒＴｉＯ3 薄膜３上に３００ｎｍ堆積し
た。
【００１８】以上のような工程により作製された薄膜キ
ャパシタは、誘電率１６０、リーク電流密度１×１０-7
（Ａ／ｃｍ2 ）（１Ｖ印加時）という良好な値を示し
た。これは下部電極としてＰｔを用いた場合と同等の特
性である。
【００１９】本実施例では、ＳｒＲｕＯ3 を６００℃の
高温で形成しているが、４５０℃程度の低温においても
形成可能であった。この上に成膜したＳｒＴｉＯ3 の電
気特性はＳｒＲｕＯ3 を６００℃で形成した場合と同等
であった。
【００２０】（実施例２）この例においては、実施例１
におけるＳｒＲｕＯ3 のかわりに、ＢａＲｕＯ3を形成
した。つまり、ウエハを６００℃に加熱した状態で、Ｂ
ａ原料であるＢａ（ＤＰＭ）2 、Ｒｕ原料であるＲｕ
（ＤＰＭ）3 及びＯ2 プラズマを供給するという方法で
成膜した。膜厚に制限はないが、１０ｎｍとした。Ｂａ
（ＤＰＭ）2原料温度は２００℃、流量は７０ｓｃｃ
ｍ、Ｒｕ（ＤＰＭ）3 は１８０℃、流量は７０ｓｃｃｍ
（それぞれ、キャリアガスはＡｒ）、Ｏ2 流量は２１０
ｓｃｃｍ、プラズマ励起マイクロ波パワーは６００Ｗ、
成膜室圧力は１Ｐａ、堆積速度は０．６ｎｍ／ｍｉｎで
あった。
【００２１】次に、ウエハ温度を５００℃とし、Ｂａ
（ＤＰＭ）2 、Ｏ2 プラズマに加え、Ｓｒ原料であるＳ
ｒ（ＤＰＭ）2 、Ｔｉ原料であるＴＩＰを供給し、Ｂａ
ＲｕＯ3 層上にペロブスカイト型酸化物誘電体である
（Ｂａ，Ｓｒ）ＴｉＯ3 ９をＥＣＲ−ＣＶＤ法により５
０ｎｍ成膜した。Ｓｒ（ＤＰＭ）2 温度は１９０℃、流
量は７０ｓｃｃｍ、ＴＩＰ温度は３６℃、流量は１４０
ｓｃｃｍ（それぞれ、キャリアガスはＡｒ）、プラズマ
励起マイクロ波パワーは８００Ｗ、成膜室圧力は１．３
Ｐａ、堆積速度は２．０ｎｍ／ｍｉｎであった。他の原
料温度、流量はＢａＲｕＯ3 成膜の場合と同じであっ
た。
【００２２】（Ｂａ，Ｓｒ）ＴｉＯ3 を成膜後、ウエハ
をＣＶＤ成膜室から取り出し、スパッタ法により上部電
極６としてＡｕを（Ｂａ，Ｓｒ）ＴｉＯ3 薄膜上に３０
０ｎｍ堆積した。
【００２３】以上のような工程により作製された薄膜キ
ャパシタは、誘電率３００、リーク電流密度３×１０-7
（Ａ／ｃｍ2 ）（１Ｖ印加時）という良好な値を示し
た。これは下部電極としてＰｔを用いた場合と同等の特
性である。
【００２４】本実施例における（Ｂａ，Ｓｒ）ＴｉＯ3
の成膜温度は５００℃という低温であったが、成膜温度
６００℃においても（Ｂａ，Ｓｒ）ＴｉＯ3 膜中へのＲ
ｕの拡散は生じなかった。結果として、電気特性は５０
０℃成膜の場合よりも向上し、誘電率は５００（ＢＳＴ
膜厚５０ｎｍ）を示した。
【００２５】（実施例３）以下、本発明の実施例３につ
いて、図２を参照にしながら説明する。図２は本発明の
実施例３に関わるスタック状に微細加工されたＲｕＯ2
を含む薄膜キャパシタの断面図である。
【００２６】Ｓｉ基板５上に設けた、熱酸化したＳｉＯ
2 層（６００ｎｍ）９中にｐｏｌｙ−Ｓｉプラグ８を形
成し、その上にスパッタ法によりバリア層（ＴｉＮ）４
を５０ｎｍ、下部電極（ＲｕＯ2 ）２を５００ｎｍ積層
した。ＲｕＯ2 ／ＴｉＮ構造はフォトリソグラフィによ
りパターニングし（パターン幅は０．４μｍ）、プラズ
マエッチングによりスタック型に加工した。
【００２７】このウエハをＥＣＲ−ＣＶＤ装置成膜室に
導入した。Ｒｕを含むペロブスカイト型酸化物層１とし
てＳｒＲｕＯ3 を、ウエハを５００℃に加熱した状態
で、Ｓｒ原料であるＳｒ（ＤＰＭ）2 とＯ2 プラズマを
供給するという方法で成膜した（膜厚１０ｎｍ程度）。
【００２８】ＳｒＲｕＯ3 膜１成膜の流れは、まずＲｕ
Ｏ2 膜２上にＳｒＯｘ層７が形成され、その後ＲｕＯ2
膜２からＲｕがＳｒＯｘ層７に拡散し、ＲｕＯ2 に接し
た部分のＳｒＯｘ層７のみがＳｒＲｕＯ3 になる、とい
うものである。Ｓｒ（ＤＰＭ）2 原料温度は１９０℃、
流量は７０ｓｃｃｍ（キャリアガスはＡｒ）、Ｏ2 流量
は２１０ｓｃｃｍ、プラズマ励起マイクロ波パワーは６
００Ｗ、成膜室圧力は１Ｐａ、堆積速度は０．６ｎｍ／
ｍｉｎであった。なお、ＳｒＯｘ層７は絶縁体であり、
ＲｕＯ2 と接していない部分はＳｒＯｘのまま残ること
より、ＲｕＯ2電極相互の絶縁は維持される。
【００２９】次に、Ｓｒ（ＤＰＭ）2 、Ｏ2 プラズマに
加え、Ｂａ原料であるＢａ（ＤＰＭ）2 、Ｔｉ原料であ
るＴＩＰを供給し、ＳｒＲｕＯ3 層上にペロブスカイト
型酸化物誘電体３である（Ｂａ，Ｓｒ）ＴｉＯ3 を３０
ｎｍ成膜した。Ｂａ（ＤＰＭ）2 温度は２００℃、流量
は７０ｓｃｃｍ、ＴＩＰ温度は３６℃、流量は１４０ｓ
ｃｃｍ（それぞれ、キャリアガスはＡｒ）、プラズマ励
起マイクロ波パワーは８００Ｗ、成膜室圧力は１．３Ｐ
ａ、堆積速度は１．０ｎｍ／ｍｉｎであった。他の原料
温度、流量はＳｒＲｕＯ3 成膜の場合と同じであった。
【００３０】（Ｂａ，Ｓｒ）ＴｉＯ3 を成膜後、ウエハ
をＣＶＤ成膜室から取り出し、スパッタ法により上部電
極６であるＡｌ（７００ｎｍ）／ＴｉＮ（５０ｎｍ）を
堆積した。
【００３１】以上の方法により作製した薄膜キャパシタ
の誘電率は２５０、リーク電流密度１×１０-7（Ａ／ｃ
ｍ2 ）（１Ｖ印加時）という良好な値を示した。
【００３２】また、断面ＴＥＭ観察から、ＳｉＯ2 表面
（（Ｂａ，Ｓｒ）ＴｉＯ3 層との間）にＳｒＯｘ層７の
存在が確認された。
【００３３】
【発明の効果】本発明の薄膜キャパシタによれば、下部
電極であるＲｕＯ2 上にＳｒＲｕＯ3等のＲｕを含むペ
ロブスカイト型酸化物層を設けることにより、結晶性の
良好なペロブスカイト型酸化物誘電体が成膜され、酸化
物誘電体薄膜中へのＲｕの拡散が抑制される。したがっ
て、ＲｕＯ2 を下部電極に用いて、誘電特性、リーク特
性、及び量産性に優れたペロブスカイト型酸化物誘電体
薄膜キャパシタを提供することができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film capacitor and a manufacturing method thereof. [0002] Next-generation high-density DRAM of 1 Gbit or more
SrTiO 3 , (Ba, Sr) Ti, which has excellent dielectric properties, insulating properties, and chemical stability for use as a capacitor film
Research and development of perovskite type oxide dielectric thin films such as O 3 and (Pb, Zr) TiO 3 have been conducted. At the same time, in order to expand the area of the capacitor portion, it is also an important subject to consider a lower electrode material that can be easily processed three-dimensionally. RuO 2
Has a low resistivity of 40 μΩcm at room temperature, in addition to O 2 +
Since dry etching with CF 4 plasma is possible (Japanese Journal of Applied Physics, Vol. 31, p. 135, 1992 (SS
aito et al. , Jpn. J. Appl. Ph
ys. 31, 135, (1992)), and is expected as a lower electrode for high density DRAM. A conventional example in which a conductive oxide such as RuO 2 is applied to a lower electrode of a thin film capacitor will be shown below. As a first conventional example, in a capacitor composed of an electrode and a perovskite type ferroelectric film containing Pb in its composition, a perovskite type oxide (for example, BaPbO 3 or BaPb) having conductivity as an electrode is used.
It is the invention (JP-A-5-234809), characterized in using 1-x Bi x O 3) or RuO 2. As a second conventional example, RuO is used as the lower electrode.
With 2, on the (Ba, Sr) there is a report that was deposited TiO 3 by sputtering (Applied Physics Letters, Vol. 64, pp. 2967, 1994 (K.T
akemura et al. , Appl. Phys.
Lett. 64, 2967, (1994)). As a third conventional example, in a semiconductor device having at least a first electrode formed on a substrate and a second electrode formed on the first electrode, the first device
Alternatively, there is an invention called a semiconductor device characterized in that an oxide layer is interposed between at least one of the second electrode and the ferroelectric film (JP-A-4-206870). In the embodiment of the present invention, SrTiO 3 , BaTiO 3 , PbLa are used as the oxide layer between the electrode and the ferroelectric film.
TiO 3 is used. The thickness of the oxide layer is 10 nm
It is as follows. In this technique, the use of SrRuO 3 and CaRuO 3 as a buffer layer between Si and SrTiO 3 is also being studied (Hiraya et al., “Crystal Engineering of Oxide Thin Films”).
(11th Crystal Engineering Symposium, Crystal Engineering Subcommittee of the Japan Society of Applied Physics), p. 23, 1995). Problems to be solved when RuO 2 is used for the lower electrode in the first and second conventional examples will be described. Generally, in order to form a perovskite type oxide dielectric thin film by CVD, sputtering, etc., 600 ° C.
The above high temperature is required. However, when the perovskite type oxide dielectric is formed or heat-treated on the RuO 2 electrode at such a high temperature, the diffusion of Ru into the dielectric film occurs (especially when the film is formed by the CVD method). When Ru is mixed in the oxide dielectric thin film, there arises a problem that the dielectric constant and the leak current of the dielectric thin film are significantly deteriorated. In the third conventional example, S is provided between the electrode and the ferroelectric film.
An oxide such as rTiO 3 , BaTiO 3 , PbLaTiO 3 or the like is provided, but these are low dielectric constant layers and cause a decrease in the dielectric constant of the entire capacitor. In order to reduce the decrease in the dielectric constant, the thickness of this oxide layer is set to 10n.
The step of strictly controlling the value of m or less is added, and the mass productivity of the capacitor is deteriorated. An object of the present invention is to provide a perovskite type oxide dielectric thin film capacitor excellent in permittivity, leak current characteristics and mass productivity by using RuO 2 for a lower electrode. The present invention is a thin film capacitor comprising at least a lower electrode, an upper electrode, and a dielectric thin film sandwiched by both electrodes, wherein the lower electrode is R.
uO 2 , the dielectric thin film is made of a perovskite type oxide, and a perovskite type oxide layer made of a material different from the dielectric thin film and containing Ru is provided at the interface between the lower electrode and the dielectric thin film. It is a thin film capacitor characterized in that. A thin film capacitor comprising a step of forming a perovskite type oxide layer containing Ru by supplying a metal raw material other than Ru constituting the perovskite type oxide onto RuO 2 which is a lower electrode. It is a manufacturing method. The perovskite type oxide containing Ru such as SrRuO 3 and the perovskite type oxide dielectric such as SrTiO 3 have the same crystal structure. In addition, SrRuO 3
And SrTiO 3 have very close lattice constants (SrRu
O 3: 0.393nm, SrTiO 3: 0.3905n
m). Therefore, the crystallinity of the perovskite type oxide dielectric formed through the perovskite type oxide layer such as SrRuO 3 is much improved as compared with the case where the film is directly formed on RuO 2 having the rutile structure. Furthermore, since the two are lattice-matched, the reaction at the interface between the oxide dielectric and the oxide layer is also suppressed, and the mixing of Ru into the oxide dielectric thin film is suppressed. Further, since the perovskite type oxide containing Ru has a very low resistance conductivity, it cannot be a low dielectric constant layer. Therefore, there is no limit to the thickness of this oxide. Furthermore, by using the manufacturing method of the present invention, a perovskite oxide containing Ru can be selectively formed on RuO 2 finely processed in a stack,
It is not necessary to perform fine processing for electrically separating the lower electrodes after forming the perovskite type oxide containing Ru. From the above, by using RuO 2 for the lower electrode, it is possible to provide a perovskite type oxide dielectric thin film capacitor excellent in permittivity, leak current characteristics and mass productivity. First Embodiment A first embodiment of the present invention will be described below with reference to FIG. First Embodiment FIG. 1 is a sectional view of a thin film capacitor according to a first embodiment of the present invention. RuO 2 was deposited on the Si substrate 5 by the sputtering method.
A barrier layer (TiN) 4 of 50 nm, which prevents the reaction between Si and Si,
The lower electrode (RuO 2 ) 2 was laminated to a thickness of 200 nm. Next, SrRuO 3 was formed as a perovskite type oxide layer 1 containing Ru by a sputtering method while the wafer was heated to 600 ° C. Although the film thickness is not particularly limited, it is 50 nm in this example. This wafer was replaced with an Electron Cycle.
Otron Resonance (ECR) -CVD apparatus It was introduced into the film forming chamber. Wafer temperature is set to 450 ° C and Sr
Raw material Sr (DPM) 2 , Ti raw material Ti (i
-OC 3 H 7 ) 4 (TIP), O 2 plasma is supplied,
Perovskite oxide dielectric 3 on SrRuO 3 layer 1
The SrTiO 3 2 was 50nm formed as. Sr (DP
The raw material temperature of M) 2 is 190 ° C., the flow rate is 70 sccm, and T
IP temperature is 36 ° C., flow rate is 70 sccm (carrier gas is Ar), plasma excitation microwave power is 600 W,
The film forming chamber pressure was 1 Pa, and the deposition rate was 1.0 nm / min. According to the ECR-CVD method, SrTiO 3 having a perovskite structure even at a low temperature of 450 ° C.
Can be formed into a film (see Yamaguchi et al., Proceedings of the 41st Joint Lecture on Applied Physics, page 410, 1994). After forming the SrTiO 3 film 3, the wafer is subjected to CV
The film was taken out of the D film forming chamber, and Au was deposited as the upper electrode 6 on the SrTiO 3 thin film 3 by sputtering to a thickness of 300 nm. The thin film capacitor manufactured by the above steps has a dielectric constant of 160 and a leakage current density of 1 × 10 −7.
A good value of (A / cm 2 ) (when 1 V was applied) was shown. This is the same characteristic as when Pt is used as the lower electrode. In this embodiment, SrRuO 3 was formed at a high temperature of 600 ° C., but it could be formed at a low temperature of about 450 ° C. The electrical characteristics of the SrTiO 3 film formed on this were similar to those when SrRuO 3 was formed at 600 ° C. (Embodiment 2) In this embodiment, Embodiment 1
BaRuO 3 was formed in place of SrRuO 3 in. In other words, with the wafer heated to 600 ° C., B
a Raw material Ba (DPM) 2 , Ru raw material Ru
A film was formed by supplying (DPM) 3 and O 2 plasma. The film thickness is not limited, but it is set to 10 nm. Ba
(DPM) 2 Raw material temperature is 200 ° C., Flow rate is 70 scc
m, Ru (DPM) 3 is 180 ° C., flow rate is 70 sccm
(The carrier gas is Ar) and the O 2 flow rate is 210.
sccm, plasma excitation microwave power 600W,
The film forming chamber pressure was 1 Pa, and the deposition rate was 0.6 nm / min. Next, the wafer temperature is set to 500 ° C. and Ba is set.
In addition to (DPM) 2 and O 2 plasma, S that is a Sr raw material
r (DPM) 2 and Ti raw material TIP are supplied, and Ba
On the RuO 3 layer, (Ba, Sr) TiO 3 9 which is a perovskite type oxide dielectric is formed by ECR-CVD method.
0 nm was formed. Sr (DPM) 2 temperature is 190 ° C., flow rate is 70 sccm, TIP temperature is 36 ° C., flow rate is 140
sccm (respectively, the carrier gas is Ar), the plasma excitation microwave power is 800 W, and the film forming chamber pressure is 1.3.
Pa and the deposition rate were 2.0 nm / min. The other raw material temperatures and flow rates were the same as in the case of BaRuO 3 film formation. After forming the (Ba, Sr) TiO 3 film, the wafer is taken out from the CVD film forming chamber, and Au is used as the upper electrode 6 on the (Ba, Sr) TiO 3 thin film by a sputtering method.
0 nm was deposited. The thin film capacitor manufactured by the above steps has a dielectric constant of 300 and a leakage current density of 3 × 10 −7.
A good value of (A / cm 2 ) (when 1 V was applied) was shown. This is the same characteristic as when Pt is used as the lower electrode. (Ba, Sr) TiO 3 in this embodiment
Although the film forming temperature of was as low as 500 ° C., even when the film forming temperature was 600 ° C., R in the (Ba, Sr) TiO 3 film was
No u diffusion occurred. As a result, the electrical characteristics are 50
The dielectric constant is 500 (BST
The film thickness was 50 nm). (Third Embodiment) A third embodiment of the present invention will be described below with reference to FIG. FIG. 2 shows RuO 2 finely processed into a stack according to Example 3 of the present invention.
3 is a cross-sectional view of a thin film capacitor including Thermally oxidized SiO provided on the Si substrate 5.
A poly-Si plug 8 is formed in two layers (600 nm) 9, and a barrier layer (TiN) 4 is formed on the poly-Si plug 8 by a sputtering method.
Of 50 nm and a lower electrode (RuO 2 ) 2 of 500 nm. The RuO 2 / TiN structure was patterned by photolithography (pattern width: 0.4 μm) and processed into a stack type by plasma etching. This wafer was introduced into the ECR-CVD apparatus film forming chamber. SrRuO 3 was formed as a perovskite type oxide layer 1 containing Ru by a method of supplying Sr (DPM) 2 as an Sr raw material and O 2 plasma in a state where the wafer was heated to 500 ° C. (film thickness 10 nm degree). The flow of forming the SrRuO 3 film 1 is as follows.
A SrOx layer 7 is formed on the O 2 film 2 and then RuO 2 is formed.
Ru diffuses from the film 2 into the SrOx layer 7, and only the portion of the SrOx layer 7 in contact with RuO 2 becomes SrRuO 3 . Sr (DPM) 2 raw material temperature is 190 ° C.,
The flow rate is 70 sccm (carrier gas is Ar), the O 2 flow rate is 210 sccm, and the plasma excitation microwave power is 6
00W, deposition chamber pressure 1 Pa, deposition rate 0.6 nm /
min. The SrOx layer 7 is an insulator,
Since the portion not in contact with RuO 2 remains as SrOx, the insulation between the RuO 2 electrodes is maintained. Next, in addition to Sr (DPM) 2 and O 2 plasma, Ba (DPM) 2 which is a Ba raw material and TIP which is a Ti raw material are supplied to form a perovskite type oxide dielectric 3 on the SrRuO 3 layer. 30% of (Ba, Sr) TiO 3
nm. Ba (DPM) 2 temperature is 200 ° C., flow rate is 70 sccm, TIP temperature is 36 ° C., flow rate is 140 s
ccm (respectively, the carrier gas is Ar), the plasma excitation microwave power is 800 W, and the film forming chamber pressure is 1.3 P.
a, the deposition rate was 1.0 nm / min. The other raw material temperatures and flow rates were the same as those for the SrRuO 3 film formation. After forming the (Ba, Sr) TiO 3 film, the wafer was taken out from the CVD film forming chamber, and Al (700 nm) / TiN (50 nm) as the upper electrode 6 was deposited by the sputtering method. The thin film capacitor manufactured by the above method has a dielectric constant of 250 and a leak current density of 1 × 10 −7 (A / c).
m 2 ) (at the time of applying 1 V) was a good value. The presence of the SrOx layer 7 was confirmed on the SiO 2 surface (between the (Ba, Sr) TiO 3 layer) by TEM observation of the cross section. According to the thin film capacitor of the present invention, by providing a perovskite type oxide layer containing Ru such as SrRuO 3 on RuO 2 which is a lower electrode, a perovskite type oxide having good crystallinity is obtained. A physical dielectric film is formed, and diffusion of Ru into the oxide dielectric thin film is suppressed. Therefore, by using RuO 2 for the lower electrode, it is possible to provide a perovskite type oxide dielectric thin film capacitor having excellent dielectric characteristics, leak characteristics and mass productivity.
【図面の簡単な説明】
【図１】本発明の一実施例を示す薄膜キャパシタの断面
図である。
【図２】本発明の一実施例を示す薄膜キャパシタの断面
図である。
【符号の説明】
１ Ｒｕを含むペロブスカイト型酸化物層
２ 下部電極（ＲｕＯ2 ）
３ ペロブスカイト型酸化物誘電体薄膜
４ バリア層（ＴｉＮ）
５ Ｓｉ基板
６ 上部電極（Ａｕ）
７ ＳｒＯｘ層
８ ｐｏｌｙ−Ｓｉプラグ
９ ＳｉＯ2 層BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a thin film capacitor showing an embodiment of the present invention. FIG. 2 is a sectional view of a thin film capacitor showing an embodiment of the present invention. [Description of Reference Signs] 1 Perovskite type oxide layer containing Ru 2 Lower electrode (RuO 2 ) 3 Perovskite type oxide dielectric thin film 4 Barrier layer (TiN) 5 Si substrate 6 Upper electrode (Au) 7 SrOx layer 8 poly- Si plug 9 SiO 2 layer
Claims (1)
電極に挟持された誘電体薄膜とからなる薄膜キャパシタ
において、前記下部電極がＲｕＯ2 からなり、前記誘電
体薄膜がペロブスカイト型酸化物からなり、かつ該下部
電極と該誘電体薄膜との界面に該誘電体薄膜とは異なる
材料よりなりＲｕを含むペロブスカイト型酸化物層を有
することを特徴とする薄膜キャパシタ。 【請求項２】下部電極と誘電体薄膜との界面に該誘電体
薄膜とは異なる材料よりなりＲｕを含むペロブスカイト
型酸化物層を有する薄膜キャパシタの製造方法であっ
て、該ペロブスカイト型酸化物を構成するＲｕ以外の金
属原料を下部電極であるＲｕＯ2 上に供給することによ
ってＲｕを含むペロブスカイト型酸化物層を形成する工
程を含むことを特徴とする薄膜キャパシタの製造方法。Claim: What is claimed is: 1. A thin film capacitor comprising at least a lower electrode, an upper electrode, and a dielectric thin film sandwiched by both electrodes, wherein the lower electrode is made of RuO 2 , and the dielectric thin film is A thin film capacitor comprising a perovskite type oxide, and having a perovskite type oxide layer made of a material different from that of the dielectric thin film and containing Ru at the interface between the lower electrode and the dielectric thin film. 2. A method for manufacturing a thin film capacitor having a perovskite oxide layer made of a material different from that of the dielectric thin film and containing Ru at the interface between the lower electrode and the dielectric thin film, wherein the perovskite oxide is formed. A method of manufacturing a thin film capacitor, comprising the step of forming a perovskite type oxide layer containing Ru by supplying a constituent metal material other than Ru to RuO 2 which is a lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8003633A JP2924753B2 (en) | 1996-01-12 | 1996-01-12 | Method for manufacturing thin film capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8003633A JP2924753B2 (en) | 1996-01-12 | 1996-01-12 | Method for manufacturing thin film capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09191087A true JPH09191087A (en) | 1997-07-22 |
| JP2924753B2 JP2924753B2 (en) | 1999-07-26 |
Family
ID=11562899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8003633A Expired - Fee Related JP2924753B2 (en) | 1996-01-12 | 1996-01-12 | Method for manufacturing thin film capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2924753B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999025014A1 (en) * | 1997-11-10 | 1999-05-20 | Hitachi, Ltd. | Dielectric element and manufacturing method therefor |
| KR20000014388A (en) * | 1998-08-20 | 2000-03-15 | 윤종용 | Ferroelectric memory capacitor and forming method thereof |
| US6335551B2 (en) | 1997-11-04 | 2002-01-01 | Nec Corporation | Thin film capacitor having an improved bottom electrode and method of forming the same |
| US6392265B2 (en) | 2000-01-12 | 2002-05-21 | Fujitsu Limited | Semiconductor device |
| JP2002521846A (en) * | 1998-07-28 | 2002-07-16 | アプライド マテリアルズ インコーポレイテッド | Method and apparatus for enhancing step coverage and boundary control of high K dielectric capacitors and associated electrodes |
| US6573584B1 (en) * | 1999-10-29 | 2003-06-03 | Kyocera Corporation | Thin film electronic device and circuit board mounting the same |
| KR100438769B1 (en) * | 1997-12-09 | 2004-12-17 | 삼성전자주식회사 | Method for forming metal oxide thin film of semiconductor device by cvd method and capacitor forming method using the same to embody high capacitance |
| KR100483359B1 (en) * | 2003-04-01 | 2005-04-15 | 학교법인 성균관대학 | Method for manufacturing semiconductor element |
| KR100898974B1 (en) * | 2007-06-18 | 2009-05-25 | 삼성전기주식회사 | Thin capacitor, laminated structure and methods of manufacturing the same |
-
1996
- 1996-01-12 JP JP8003633A patent/JP2924753B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335551B2 (en) | 1997-11-04 | 2002-01-01 | Nec Corporation | Thin film capacitor having an improved bottom electrode and method of forming the same |
| KR100359756B1 (en) * | 1997-11-04 | 2003-03-28 | 닛본 덴기 가부시끼가이샤 | Manufacturing method of thin film capacitor |
| WO1999025014A1 (en) * | 1997-11-10 | 1999-05-20 | Hitachi, Ltd. | Dielectric element and manufacturing method therefor |
| KR100438769B1 (en) * | 1997-12-09 | 2004-12-17 | 삼성전자주식회사 | Method for forming metal oxide thin film of semiconductor device by cvd method and capacitor forming method using the same to embody high capacitance |
| JP2002521846A (en) * | 1998-07-28 | 2002-07-16 | アプライド マテリアルズ インコーポレイテッド | Method and apparatus for enhancing step coverage and boundary control of high K dielectric capacitors and associated electrodes |
| KR20000014388A (en) * | 1998-08-20 | 2000-03-15 | 윤종용 | Ferroelectric memory capacitor and forming method thereof |
| US6573584B1 (en) * | 1999-10-29 | 2003-06-03 | Kyocera Corporation | Thin film electronic device and circuit board mounting the same |
| US6392265B2 (en) | 2000-01-12 | 2002-05-21 | Fujitsu Limited | Semiconductor device |
| KR100483359B1 (en) * | 2003-04-01 | 2005-04-15 | 학교법인 성균관대학 | Method for manufacturing semiconductor element |
| KR100898974B1 (en) * | 2007-06-18 | 2009-05-25 | 삼성전기주식회사 | Thin capacitor, laminated structure and methods of manufacturing the same |
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| JP2924753B2 (en) | 1999-07-26 |
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