JPH0917996A - Mos semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: To reduce the resistance of the gate electrode of a MOS semiconductor device, thereby reducing the noise. CONSTITUTION: A gate electrode 13 formed on a semiconductor substrate 10 through a gate oxide film 11 uses a MoW alloy film which has a lower resistivity than that of the conventional Mo or W layer, thereby enabling the reduction of the noise. By setting the W content in the MoW alloy film to 20-80atom%, pref. 30-70-atom% the resistivity of the gate electrode 13 can be more reduced to more enhance the noise reduction.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a MOS (Metal Oxide)
Semiconductor) type semiconductor device and its manufacturing method, and more particularly to a gate structure of a MOS type field effect transistor (FET) operating at high frequency.

[0002]

2. Description of the Related Art A MOS type FET operating at a high frequency is required to have a short gate length in order to improve power characteristics, and the order is currently below 1 μm. Therefore, in the conventional MOS FET, after forming the gate electrode on the surface of the semiconductor substrate via the gate oxide film, impurity ions are implanted using the gate electrode as a mask and the impurity ion-implanted layer is annealed to form the source and drain regions. Are manufactured by self-alignment. As the gate electrode, a high melting point metal film is preferable because it is subjected to heat treatment at 800 to 1000 ° C. during annealing, and the noise figure of the MOS type FET is proportional to the resistivity of the gate electrode, which is effective in reducing noise. Is preferably a metal film having a low resistivity. Because of this,
As the gate electrode, a single film of high melting point and low resistance molybdenum (Mo) or tungsten (W) is used.

[0003]

However, for example, in a dual-gate MOS type FET with two gate fingers, an effective gate length of 1 μm, a gate width of 600 μm, and a gate electrode of a single layer of Mo with a thickness of 400 nm. , The resistance of the gate electrode is about 188 Ω, the noise figure in the high frequency region 800 MHz is about 3.5 dB, and the resistance of the single layer of W with a thickness of 400 nm is about 300 Ω. The noise figure is about 4.2 dB, and in each case there is a problem that the noise figure is still high. Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a low-noise MOS semiconductor device and a method for manufacturing the same.

[0004]

In order to achieve the above object, a MOS type semiconductor device of the present invention is arranged on a first conductivity type semiconductor substrate via a gate insulating film and contains MoW as a main component. It has a gate electrode made of an alloy film, a source region of the second conductivity type formed on one side of the gate electrode, and a drain region of the second conductivity type formed on the other side of the gate electrode. And

Further, in order to achieve the above object, the present invention
The MOS semiconductor device covers a gate electrode made of an alloy film containing MoW as a main component, which is disposed on a semiconductor substrate of the first conductivity type with a gate insulating film interposed between the gate electrode and at least one of an upper surface and a lower surface of the gate electrode. It is characterized in that it has an impurity blocking film and source and drain regions formed by introducing impurities using the gate electrode as a mask.

Further, in order to achieve the above object, the present invention
The MOS type semiconductor device includes a gate electrode made of an alloy film containing MoW as a main component, which is arranged on a semiconductor substrate of the first conductivity type with a gate insulating film interposed therebetween, and an impurity blocking layer covering the upper and lower surfaces and side surfaces of the gate electrode. CVD Si covering the film, the source and drain regions formed by introducing impurities using the gate electrode as a mask, and the semiconductor substrate including the gate electrode
And an oxide film.

The gate electrode is made of a MoW alloy film having a W content of 20 to 80 atomic%.
Among the above impurity blocking films, the impurity blocking film on the lower surface of the gate electrode is made of conductive amorphous, and the other impurity blocking films are made of insulating amorphous or Si nitride film.

Further, in order to achieve the above object, the present invention
The method of manufacturing a MOS type semiconductor device includes a step of forming a gate oxide film on a semiconductor substrate of the first conductivity type, and a MoW alloy film having a W content of 30 to 50 atomic% on the gate oxide film of 0.3 to 0.
A step of depositing with an argon pressure of 5 Pa, a step of patterning the MoW alloy film to form a gate electrode, and a step of introducing a second conductivity type impurity into the semiconductor substrate using the gate electrode as a mask and then performing a heat treatment. And a step of forming source and drain regions. or,
In order to achieve the above object, a method of manufacturing a MOS semiconductor device according to the present invention comprises a step of forming a gate oxide film on a first conductivity type semiconductor substrate and a step of forming an impurity blocking film on the gate oxide film. A step of forming a MoW alloy film on the impurity blocking film, a step of patterning the MoW alloy film to form a gate electrode, and a step of removing the impurity blocking film using the gate electrode as a mask, After introducing a second conductivity type impurity into the semiconductor substrate using the gate electrode as a mask, heat treatment is performed to form source and drain regions.

The upper surface of the gate electrode is covered with an impurity blocking film before the second conductivity type impurity is introduced. After covering the upper surface of the gate electrode with an impurity blocking film, an impurity blocking film is further deposited on the semiconductor substrate including the gate electrode, and the impurity blocking film is anisotropically etched to remove impurities on the side surface of the gate electrode. The method is characterized by performing a step of depositing a blocking film and leaving the impurity blocking film, and a step of introducing the impurities after this step.

After the step of covering at least one surface of the gate electrode with the impurity blocking film and introducing the impurities,
It is characterized in that a step of forming a CVD Si film on the semiconductor substrate including the gate electrode and a step of heat treating the semiconductor substrate to form source and drain regions are performed after this step.

The W content of the MoW alloy film is 30 to 70 atomic%. Among the above impurity blocking films, a conductive amorphous film is used for the impurity blocking film on the lower surface of the gate electrode, and an insulating amorphous film or a Si nitride film is used for the other impurity blocking films.

[0012]

In the MOS type semiconductor device and the manufacturing method thereof according to the present invention, the MoW alloy film is used for the gate electrode. This allows
The resistance of the gate electrode can be lowered and the noise can be reduced. Especially W
By setting the content to 20 to 80 atomic%, preferably 30 to 70 atomic%, the noise reduction can be further improved.

At least one of the upper surface and the lower surface of the gate electrode made of the MoW alloy film is covered with an impurity blocking film such as an amorphous film. The amorphous film on the lower surface or the upper surface can prevent the impurity ions from penetrating below the gate electrode at the time of implanting the impurity ions for forming the source and drain regions using the gate electrode as a mask. Can be prevented.

Further, during annealing for diffusing impurities,
The lower amorphous film can prevent oxygen molecules from mixing into the gate electrode from the gate oxide film, and the upper amorphous film can suppress oxygen molecules from mixing into the gate electrode from the CVD Si oxide film. Therefore, the increase in the resistivity of the gate electrode due to the oxidation of the gate electrode can be suppressed.
In particular, by covering both sides of the gate electrode with the amorphous film in addition to the upper and lower surfaces, not only leakage current is generated, but also oxygen molecules from the gate electrode and the CVD Si oxide film are almost completely mixed into the gate electrode. It can be suppressed and the resistance of the gate electrode can be maintained at the original low resistance of the MoW alloy film.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A MOS type semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a MOS type FET according to the first embodiment of the present invention. This MOS type
In the FET, a gate electrode 13 made of a MoW alloy film is formed on a P conductivity type Si substrate 10 with a gate oxide film 11 interposed therebetween.
Then, using the gate electrode 13 as a mask, phosphorus ( ³¹ P ⁺ ) ions are introduced and annealed to form a source region 14 and a drain region 15 of N 2 conductivity type. Then, a CVD Si oxide film 16 is formed on the Si substrate 10 including the gate electrode 13 as an interlayer insulating film or a surface stabilizing film, and although not shown, a contact hole provided in the CVD Si oxide film 16 is formed. Source and drain electrodes are formed in the source and drain regions, respectively.

2 (a) to 2 (d) show the manufacturing process of the MOS type FET of the first embodiment described above. P conductive type Si substrate 20
A gate oxide film 21 having a thickness of several tens of nm is formed thereon by a thermal oxidation method (shown in FIG. 2A). A mixed material of Mo and W is deposited up to 400 nm on the gate oxide film 21 by the sputtering method, a resist film 28 is applied on the surface, and patterned into a predetermined shape by an etching process (PEP) (FIG. 2 (b)). (Shown). Using this resist film 28 as a mask, reactive ion etching (RI
The MoW alloy film is etched by E), and the gate electrode 23
After forming, the resist film 28 is removed (shown in FIG. 2 (c)). Next, using this gate electrode 23 as a mask, ³¹ P ⁺
By implanting ions, as an interlayer insulating film or surface stabilizing film,
An oxide film 26 of about 200 to 300 nm is deposited on the entire surface by the CVD method. Then, the semiconductor substrate 20 is heated to about 800 to 900 [deg.] C. and activation annealing is performed to form a source region 24 and a drain region 25 of N conductivity type (shown in FIG. 2D). Finally,
Although not shown, contact holes are formed in the oxide film 26, and source and drain electrodes are formed in the source region 24 and the drain region 25, respectively.

In the MOS type FET of the above-mentioned embodiment, since the gate electrode is formed of the MoW alloy film, the MoW alloy after activation annealing shown in FIG. Alternatively, the resistance is smaller than that of the single W element, so that the noise figure can be reduced as compared with the conventional MOS FET.

FIG. 3 shows a MOS type FET according to the second embodiment of the present invention.
FIG. This MOS type FET is P conductivity type Si
A gate electrode 33 made of a MoW alloy film is formed on the surface of a substrate 30 via a gate oxide film 31. Then, the entire surface of the gate electrode 33 is covered with an impurity blocking film, for example, an amorphous film 37. Further, using the gate electrode 33 as a mask, ³¹ P ⁺ ions are introduced and annealed to form an N 2 conductivity type source region 34 and a gate region 35. Then, a CVD Si oxide film 36 having a role of an interlayer insulating film or a surface stabilizing film is formed on the Si substrate 30 including the gate electrode 33, and a contact hole provided in the CVD Si oxide film 36 (not shown) is formed. Source region 34 and drain region 35
A source electrode and a drain electrode are formed on each of.

FIG. 4 shows the MOS type FE of the second embodiment described above.
The manufacturing process of T is shown. A gate oxide film 41 of several tens nm is formed on a semiconductor substrate 40 made of P-conductivity type Si by a thermal oxidation method. A conductive amorphous film 47 is formed on the gate oxide film 41.
a is deposited to a thickness of about 100 nm and the surface is sputtered with MoW.
Insulating amorphous film after depositing alloy film up to 400 nm
47b is deposited to a thickness of about 100 nm. A resist film is applied on the surface and patterned into a predetermined shape by PEP. Using this resist film as a mask, the amorphous film 47b and the MoW alloy film are etched by RIE to remove the gate electrode 43.
After forming, the resist film is removed (shown in FIG. 4 (a)). Next, an insulating amorphous film 47c is deposited on the entire surface (shown in FIG. 4 (b)). This insulating amorphous film 47
C is removed by RIE, and the amorphous film 47c is left on both side surfaces of the gate electrode 43 (shown in FIG. 4C). Using the insulating amorphous film 47c and the gate electrode 43 as a mask,
³¹ P ⁺ ions are implanted to form an interlayer insulating film or a surface stabilizing film, and a CVD method of about 200 to 300 nm is applied to the entire surface by CVD.
A Si oxide film 46 is deposited. And the semiconductor substrate 40 is about 800
The source region 44 is heated by heating to ~ 900 ° C for activation annealing.
And a drain region 45 are formed (FIG. 4 (d)).

The effects peculiar to the MOS type FET and the manufacturing method thereof according to the second embodiment are as follows. (1) In the MoW alloy film, the atoms are arranged in columns like the single film of Mo or W, and when the impurity ions for forming the source and drain regions are implanted using the gate electrode as a mask, the impurities penetrate through the gate electrode. . Then, the impurities enter the inside of the gate oxide film and induce a surface state between the gate electrode and the gate oxide film or between the gate oxide film and the base substrate, which obstructs device characteristics. Impurities that have entered deeper spread the diffusion region during annealing and conduct between the source and drain to form a resistor. Further, the impurities cause a leak current to flow when crystal defects are generated in the gate oxide film during implantation.

However, in this embodiment, since the entire surface of the gate electrode is covered with an impurity blocking film such as an amorphous film, it is possible to prevent impurities from being introduced into the gate electrode and the gate oxide film during the implantation of impurity ions. You can

Therefore, it was obtained by such a method.
In MOS type FET, almost no leakage current occurs. (2) When the gate electrode is in direct contact with the CVD Si oxide film and the gate oxide film as in the prior art or the above-mentioned first embodiment, the CVD Si oxide film is annealed during the annealing for forming the source and drain regions. In addition, oxygen molecules in the film penetrate into the gate electrode from the gate oxide film, causing oxidation of the gate electrode and increasing the resistance of the gate electrode. However, in this embodiment, since the entire surface of the gate electrode is covered with an impurity blocking film such as an amorphous film, diffusion of oxygen molecules from the CVD Si oxide film and the gate oxide film to the gate electrode is suppressed, and the gate electrode is suppressed. The original low resistance of the MoW alloy film that constitutes (3) As in the prior art and the first embodiment, when impurity ions are implanted using the gate electrode as a mask and then annealed to diffuse the impurities to form the source and drain regions, the impurity ions are annealed. Diffuses laterally, and the source / drain regions spread below the gate,
Overlaps with the gate electrode. When such an overlapping region is formed, the coupling capacitance is increased, the rise of the gate potential is delayed, and the operation characteristics of the circuit are delayed.

However, as in the second embodiment, in the self-alignment by the insulating amorphous film on both side surfaces of the gate electrode, the overlapping region between the source and drain regions and the gate electrode is decreased, and the coupling capacitance is the same as that of the conventional one. Smaller than in one embodiment, the operating characteristics of the circuit are faster.

FIG. 5 shows a MOS type FET according to the third embodiment of the present invention.
FIG. This MOS type FET is P conductivity type Si
A gate electrode 53 made of a MoW alloy film is formed on a substrate 50 with a gate oxide film 51 and an impurity blocking film such as a conductive amorphous Si film 57a interposed therebetween. Furthermore, this gate electrode 53
An amorphous film 57b is formed on the upper surface of the. And
Using this gate electrode 53 as a mask, ³¹ P ⁺ ions are introduced and annealed to form an N 2 conductivity type source region 54 and a gate region.
Form 55. And Si containing this gate electrode 53
CVD such as interlayer insulation film or surface stabilization film on the substrate 50
A Si oxide film 56 is formed, and although not shown, source and drain electrodes are formed in the source and drain regions through the contact holes provided in the CVD Si oxide film 56, respectively.

The method of manufacturing the MOS type FET of the third embodiment will be described below. A gate oxide film 51 of several tens nm is formed on a semiconductor substrate 50 made of P-conductivity type Si by a thermal oxidation method.
A conductive amorphous film 57a 10 is formed on the gate oxide film 51.
Deposit a MoW alloy film up to 400 nm on the surface by sputtering, and deposit an amorphous film 57b on the surface.
Deposit about 00 nm. Apply a resist film on the surface,
Patterning is performed by PEP into a predetermined shape. Using this resist film as a mask, an amorphous film 57 is formed by RIE.
Gate electrode 53 by etching a , 57b and MoW alloy film
To form After forming the gate electrode 53, the resist film is removed.

In this state, ³¹ P ⁺ ions are implanted, and a CVD Si oxide film 56 of about 200 to 300 nm is deposited on the entire surface as an interlayer insulating film or a surface stabilizing film by the CVD method. Then, the semiconductor substrate 50 is heated to about 800 to 900 ° C. to perform activation annealing, and the N conductivity type source region 54 and drain region 55 are formed.
To form Finally, although not shown, this CVD Si oxide film
Contact holes are formed in 56, and source and drain electrodes are formed in the source region 54 and the drain region 55, respectively.

Also in this embodiment, since the upper surface and the lower surface of the gate electrode are covered with the amorphous film, the same effect as that of the second embodiment described above can be obtained. That is, at the time of implanting impurities, the amorphous film on the upper surface of the gate electrode
It is possible to prevent impurities from being introduced into the gate electrode,
In the obtained MOS FET, almost no leakage current occurs. Also, in this embodiment, the side surface of the gate electrode is
Although it is in direct contact with the CVD Si oxide film, this side surface has an extremely small area compared to the top and bottom surfaces of the gate electrode, and it is almost impossible for oxygen molecules to enter the gate electrode from the CVD Si oxide film and the gate oxide film. In addition, the resistance of the gate electrode hardly increases due to the oxidation of the gate electrode. FIG. 6 is a schematic sectional view of a MOS type FET according to the fourth embodiment of the present invention. This MO
In the S-type FET, a gate electrode 63 made of a MoW alloy film is formed on a P-type conductivity Si substrate 60 via a gate oxide film 61. Further, an impurity blocking film such as an amorphous film 67 is formed on the upper surface of the gate electrode 63. Then, using the gate electrode 63 as a mask, ³¹ P ⁺ ions are introduced and annealed to form a source region 64 and a gate region 65. Then, a CVD Si oxide film 66 is formed as an interlayer insulating film or a surface stabilizing film on the Si substrate 60 including the gate electrode 63,
Although not shown, the source and drain electrodes are formed in the source and drain regions via the contact holes provided in the CVD Si oxide film 66, respectively.

The manufacturing method of the MOS type FET of the fourth embodiment will be described below. A gate oxide film 61 having a thickness of several tens of nm is formed on a semiconductor substrate 60 made of P conductivity type Si by a thermal oxidation method.
A MoW alloy film is sputtered on the gate oxide film 61.
Amorphous film 67 of 100n is deposited on the surface up to 400nm.
Deposit about m. A resist film is applied on the surface and PE
P is used to perform patterning into a predetermined shape. Using this resist film as a mask, the amorphous film 67 and the MoW alloy film are etched by RIE to form the gate electrode 63.
After forming the gate electrode 63, the resist film is removed.

In this state, ³¹ P ⁺ ions are implanted, and a CVD Si oxide film 66 of about 200 to 300 nm is deposited on the entire surface by the CVD method. Then, the semiconductor substrate 60 is heated to about 800 to 900 ° C. to perform activation annealing, and the source region 64 and the drain region are
Forming 65. Finally, although not shown, contact holes are formed in the Si oxide film 66, and source and drain electrodes are formed in the source region 64 and the drain region 65, respectively.

Also in this embodiment, since the upper surface of the gate electrode is covered with the amorphous film, similar to the second and third embodiments described above, when the impurity ions are implanted, the amorphous film on the upper surface of the gate electrode prevents impurities from being introduced. Can be prevented from being introduced into the gate electrode, and the obtained MOS type FE
At T, almost no leakage current occurs. Also, the side surface of the gate electrode is in direct contact with the CVD Si oxide film, but this side surface has an extremely small area compared to the upper surface of the gate electrode, and oxygen molecules in the CVD Si oxide film may enter the gate electrode. An increase in the resistance of the gate electrode caused by the oxidation of the gate electrode can be suppressed.

Next, a MOS type FET according to the fifth embodiment of the present invention will be described. Here, description of the same components as those of the above-described embodiment will be omitted, and only different components will be described. That is, in this embodiment, in the MOS type FETs of the first to fourth embodiments, the gate electrode contains W
It is formed of a MoW alloy film of 20 to 80 atomic%, preferably 30 to 70 atomic%.

In the MOS type FET of this embodiment, in addition to the effects of each embodiment, as is clear from FIG. 7, in the dual gate MOS type FET having two gate fingers,
When the effective gate length is 1 μm, the gate width is 600 μm, and the thickness of the gate electrode is 400 nm, and the W content is 20 to 80 atomic%, the gate resistance is about 90 to 110 Ω at the frequency of 800 MHz. Has a noise figure of about 3.1 to 3.3 dB, the gate resistance can be reduced by about 48 to 59%, and the noise figure can be reduced by about 84 to 94% as compared with the case where the gate electrode is Mo. Also
Compared to the case of W, the gate resistance can be reduced by about 30 to 37% and the noise figure can be reduced by about 74 to 79%.

Particularly, when the W content is 30 to 70 atomic%, the gate resistance is about 60 to 83Ω and the noise figure is about 2.8 to.
3.0 dB, the gate resistance can be reduced by about 32 to 44%, the noise figure can be reduced by about 80 to 86% compared to the case of Mo, and the gate resistance can be reduced by about 20 to 28% compared to the case of W. Moreover, the noise figure can be reduced by about 67 to 71%.

A MOS type FET according to a sixth embodiment of the present invention and a method for manufacturing the same will be described. Here, description of the same components as those of the above-described embodiment will be omitted, and only different components will be described. That is, in this embodiment,
In the method for manufacturing the MOS-type FET of the first to fifth embodiments, when the MoW alloy film is deposited by the sputtering method, the W
The content is chosen to be in the range of 30 to 50 atomic%, and the argon pressure is chosen to be in the range of about 0.3 to 0.5 Pa, preferably the argon pressure is to be about 0.4 Pa.

According to the method of manufacturing the MOS type FET of this embodiment, in addition to the effects of the above respective embodiments, there are the following unique effects. FIG. 9 shows the relationship between the argon (Ar) pressure and the stress of the MoW alloy film by changing the mixing ratio of Mo and W. As is clear from this figure, the W content of the MoW alloy film is 30 to 50 atom%.
The argon pressure is 0.3 to 0.
When the MoW alloy film is formed by the sputtering method in the range of 5 Pa, the stress can be relaxed as compared with the case of using a single layer of Mo or W. For example, in a monolayer of Mo or W, the stress cannot be made zero by changing the argon pressure.
The content is in the range of 30 to 50 atom%, and the argon pressure is about 0.4P.
The stress of the MoW film can be made zero by selecting a. Therefore, a MOS type FET manufactured by such a method
In the case, the adhesion between the gate electrode and the gate oxide film is good, and stable device characteristics are obtained.

The present invention is not limited to the above first to sixth embodiments, but may be modified as follows, for example. First, in the second and third embodiments, the lower surface of the gate electrode is required to be a conductive amorphous film, for example, MoSi, TiSi, but in the second to fourth embodiments, the upper surface of the gate electrode or Insulating amorphous film on the side ,
For example, SiN may be used.

The MoW alloy film thickness, the amorphous film thickness or the nitride film thickness, and the interlayer insulating film thickness deposited on the gate oxide film are not limited to those in the above embodiment. Furthermore, MO with high frequency characteristics
Although the N-channel FET is given as an example of the S-type FET, the present invention can be applied to the P-channel FET as a matter of course.

[0038]

According to the present invention, a low noise MOS type semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a MOS type FET according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a MOS type FET according to the first embodiment of the present invention.

FIG. 3 is a schematic sectional view of a MOS type FET according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a MOS type FET according to a second embodiment of the present invention.

FIG. 5 is a schematic sectional view of a MOS type FET according to a third embodiment of the present invention.

FIG. 6 is a schematic sectional view of a MOS type FET according to a fourth embodiment of the present invention.

FIG. 7 is a graph showing the resistivity of a mixed material of Mo and W.

FIG. 8 is a graph showing stress of a mixed material of Mo and W against Ar pressure.

[Explanation of symbols]

 10, 20, 30, 40, 50, 60 Si substrate 11, 21, 31, 41, 51, 61 Gate oxide film 13, 23, 33, 43, 53, 63 Gate electrode 14, 24, 34, 44, 54, 64 Source region 15, 25, 35, 45, 55, 65 Drain region 16, 26, 36, 46, 56, 66 Si oxide film 28, 48 Resist film 47, 57, 67 Amorphous film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsushi Ikeda 33 Shin-Isoko-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside the Toshiba Industrial Technology Institute, Inc. No. 1 Incorporated company Toshiba Research & Development Center

Claims (12)

[Claims] 1. A gate electrode made of an alloy film containing MoW as a main component, which is arranged on a semiconductor substrate of the first conductivity type via a gate insulating film, and a second conductivity formed on one side of the gate electrode. Type semiconductor region, and a second conductivity type drain region formed on the other side of the gate electrode. 2. A gate electrode made of an alloy film containing MoW as a main component, which is disposed on a semiconductor substrate of the first conductivity type via a gate insulating film, and impurities covering at least one of an upper surface and a lower surface of the gate electrode. A MOS-type semiconductor device comprising: a blocking film; and a source and drain region formed by introducing an impurity using the gate electrode as a mask. 3. A gate electrode made of an alloy film containing MoW as a main component, which is disposed on a semiconductor substrate of the first conductivity type via a gate insulating film, and an impurity blocking film covering the upper and lower surfaces and side surfaces of the gate electrode. And a source and drain region formed by introducing impurities using the gate electrode as a mask,
And a CVD Si oxide film covering a semiconductor substrate including the gate electrode. 4. The W content of the gate electrode is 20 to 8
4. The MOS type semiconductor device according to claim 1, wherein the MOS type semiconductor device comprises a MoW alloy film of 0 atomic%. 5. The impurity blocking film on the lower surface of the gate electrode of the impurity blocking film is made of conductive amorphous, and the other impurity blocking films are made of insulating amorphous or Si nitride film. 3. A MOS type semiconductor device according to item 3. 6. A step of forming a gate oxide film on a first conductivity type semiconductor substrate, and a MoW alloy film having a W content of 30 to 50 atomic% is deposited on the gate oxide film at an argon pressure of 0.3 to 0.5 Pa. And a step of patterning the MoW alloy film to form a gate electrode, and using the gate electrode as a mask to introduce a second conductivity type impurity into the semiconductor substrate, followed by heat treatment to form a source and drain region. A method of manufacturing a MOS type semiconductor device, comprising: 7. A step of forming a gate oxide film on a first conductivity type semiconductor substrate, a step of forming an impurity blocking film on the gate oxide film, and a step of forming a MoW alloy film on the impurity blocking film. A step of forming a gate electrode by patterning the MoW alloy film, a step of removing the impurity blocking film using the gate electrode as a mask, and a second conductivity type on the semiconductor substrate using the gate electrode as a mask. And a step of forming a source and drain regions by heat treatment after introducing impurities. 8. Before introducing the second conductivity type impurity,
8. The method of manufacturing a MOS semiconductor device according to claim 7, wherein an upper surface of the gate electrode is covered with an impurity blocking film. 9. After covering the upper surface of the gate electrode with an impurity blocking film, an impurity blocking film is further deposited on the semiconductor substrate including the gate electrode, and the impurity blocking film is anisotropically etched to form the gate electrode. Deposit an impurity blocking film on the side surface,
9. The method for manufacturing a MOS type semiconductor device according to claim 8, wherein a step of leaving the impurity blocking film and a step of introducing the impurities are performed after this step. 10. After the step of covering at least one surface of the gate electrode with the impurity blocking film and introducing the impurities,
10. The step of forming a CVD Si film on the semiconductor substrate including the gate electrode, and the step of heat treating the semiconductor substrate to form source and drain regions after this step. Manufacturing method of MOS type semiconductor device. 11. The method for manufacturing a MOS semiconductor device according to claim 7, wherein the W content of the MoW alloy film is 30 to 70 atomic%. 12. A conductive amorphous film is used as an impurity blocking film on a lower surface of a gate electrode among the impurity blocking films,
Insulating amorphous film or Si for other impurity blocking film
10. The method for manufacturing a MOS semiconductor device according to claim 7, wherein a nitride film is used.