JPH09162399A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09162399A JPH09162399A JP7323073A JP32307395A JPH09162399A JP H09162399 A JPH09162399 A JP H09162399A JP 7323073 A JP7323073 A JP 7323073A JP 32307395 A JP32307395 A JP 32307395A JP H09162399 A JPH09162399 A JP H09162399A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- epitaxial layer
- area
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 28
- 238000002955 isolation Methods 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000008188 pellet Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 38
- 230000003071 parasitic effect Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、パワーデバイス
に係り、特にトレンチを有するトランジスタの保護回路
を備えた半導体装置の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power device, and more particularly to improvement of a semiconductor device including a protection circuit for a transistor having a trench.
【０００２】[0002]
【従来の技術】図２はトレンチを持った代表的な縦型Ｎ
チャネル型の電界効果トランジスタ（以下、ＦＥＴと記
す）の断面図である。図２（ａ）において１はＮ型高濃
度（以下、Ｎ+ 型と記す）シリコン半導体基板、２はＮ
型低濃度（以下、Ｎ- 型と記す）のシリコンエピタキシ
ャル層である。ＦＥＴのドレインは半導体基板１のＮ+
型の部分、Ｎ- 型エピタキシャル層２から成る。３はド
レイン電極である。前記Ｎ- 型エピタキシャル層２内に
Ｐ- 型ベース領域４が形成される。Ｐ+ 型ベース領域５
が前記Ｐ- 型ベース領域４内に形成される。Ｎ+ 型ソー
ス領域６が前記Ｐ+ 型ベース領域５及び前記Ｐ- 型ベー
ス領域４に接して形成される。前記Ｐ- 型ベース領域
４、前記Ｎ+ 型ソース領域６を貫いて、前記Ｎ- 型エピ
タキシャル層２まで達するトレンチ７が形成される。こ
のトレンチ７にゲート酸化膜８、ポリシリコンゲート電
極９が順に形成される。前記トレンチ７の上及びエピタ
キシャル層２の表面には、層間絶縁膜１０が形成され、
エピタキシャル層２上に位置する層間絶縁膜１０上にポ
リシリコンで形成された双方向ツェナーダイオード１８
が形成される。この双方向ツェナーダイオード１８は、
順に隣接して形成されたＮ+ 型領域１８ａ、Ｐ- 型領域
１８ｂ、Ｎ+ 型領域１８ｃ、Ｐ- 型領域１８ｄ、Ｎ+ 型
領域１８ｅからなる。この双方向ツェナーダイオード１
８の上には層間絶縁膜が形成され、前記Ｎ+ 型領域１８
ａと前記Ｎ+ 型ソース領域６及びＰ+ 型ベース領域５は
ソース電極１１により接続される。特に図示していない
が、前記Ｎ+ 型領域１８ｅとポリシリコンゲート電極９
とは、ＦＥＴ及び双方向ツェナーダイオードを含むペレ
ット周辺においてゲート電極１２により接続されてい
る。2. Description of the Related Art FIG. 2 shows a typical vertical N type having a trench.
FIG. 3 is a cross-sectional view of a channel type field effect transistor (hereinafter, referred to as FET). In FIG. 2A, 1 is an N-type high-concentration (hereinafter referred to as N + -type) silicon semiconductor substrate, and 2 is N-type.
It is a low-concentration type silicon epitaxial layer (hereinafter referred to as N − type). The drain of the FET is N + of the semiconductor substrate 1.
The mold portion comprises an N − type epitaxial layer 2. 3 is a drain electrode. A P − type base region 4 is formed in the N − type epitaxial layer 2. P + type base region 5
Are formed in the P − -type base region 4. An N + type source region 6 is formed in contact with the P + type base region 5 and the P − type base region 4. A trench 7 is formed through the P − type base region 4 and the N + type source region 6 to reach the N − type epitaxial layer 2. A gate oxide film 8 and a polysilicon gate electrode 9 are sequentially formed in the trench 7. An interlayer insulating film 10 is formed on the trench 7 and on the surface of the epitaxial layer 2,
Bidirectional Zener diode 18 made of polysilicon on interlayer insulating film 10 located on epitaxial layer 2
Is formed. This bidirectional Zener diode 18 is
It is composed of an N + type region 18a, a P − type region 18b, an N + type region 18c, a P − type region 18d, and an N + type region 18e which are formed adjacently in order. This bidirectional Zener diode 1
And an N + type region 18
The source electrode 11 connects a with the N + type source region 6 and the P + type base region 5. Although not particularly shown, the N + type region 18e and the polysilicon gate electrode 9
Are connected by the gate electrode 12 around the pellet including the FET and the bidirectional Zener diode.
【０００３】上記構成においてゲート酸化膜８を保護す
るための双方向ツェナーダイオード１８はトレンチ７内
のゲート電極９と同時に形成することはできない。すな
わち、これらを同時に形成した場合、双方向ツェナーダ
イオード１８のポリシリコンにはポリシリコンゲート電
極９と同様にリン等が添加されるため、所望の耐圧を得
ることが非常に困難となる。また、双方向ツェナーダイ
オード１８の耐圧を決めるＮ+ 型領域、Ｐ- 型領域はト
レンチ７周辺のＰ+ 型ベース領域、Ｎ+ 型ソース領域と
同時に形成できない。以上のことから、双方向ツェナー
ダイオイード１８の形成の全行程をＦＥＴの形成後に行
うことになり、工程が非常に長くなってしまう。従っ
て、コストも高くなってしまう。In the above structure, the bidirectional Zener diode 18 for protecting the gate oxide film 8 cannot be formed simultaneously with the gate electrode 9 in the trench 7. That is, when these are formed at the same time, since phosphorus or the like is added to the polysilicon of the bidirectional Zener diode 18 like the polysilicon gate electrode 9, it becomes very difficult to obtain a desired breakdown voltage. Further, the N + type region and the P − type region which determine the breakdown voltage of the bidirectional Zener diode 18 cannot be formed simultaneously with the P + type base region and the N + type source region around the trench 7. From the above, the entire process of forming the bidirectional Zener diode 18 is performed after the formation of the FET, resulting in a very long process. Therefore, the cost becomes high.
【０００４】図２（ｂ）は他の従来例を示すものであ
る。同図においてＦＥＴの部分は図２（ａ）の場合と同
じ構造であり、ツェナーダイオード１８の代わりに双方
向トランジスタ１９が形成されている。この双方向トラ
ンジスタ１９は、Ｎ- 型エピタキシャル層２内のＰ型領
域１３と、前記Ｐ型領域１３内に形成された二つのＮ+
型領域１４によって構成される。この双方向トランジス
タ１９の一方のＮ+ 型領域１４と前記ＦＥＴの前記Ｎ+
型ソース領域６及び前記Ｐ+ 型ベース領域５はソース電
極１１により接続される。特に図示していないが、双方
向トランジスタ１９の他方のＮ+ 型領域１４と前記ＦＥ
Ｔのポリシリコンゲート電極９とは、ＦＥＴ及び双方向
トランジスタを含むペレット周辺においてゲート電極１
２により接続されている。FIG. 2 (b) shows another conventional example. In the figure, the FET portion has the same structure as in the case of FIG. 2A, and a bidirectional transistor 19 is formed instead of the Zener diode 18. The bidirectional transistor 19 includes a P-type region 13 in the N − -type epitaxial layer 2 and two N + -type regions formed in the P-type region 13.
It is constituted by the mold region 14. Said one of the N + -type region 14 and the FET of the bidirectional transistor 19 N +
The type source region 6 and the P + type base region 5 are connected by a source electrode 11. Although not particularly shown, the other N + type region 14 of the bidirectional transistor 19 and the FE
The polysilicon gate electrode 9 of T means the gate electrode 1 around the pellet including the FET and the bidirectional transistor.
2 are connected.
【０００５】上記ＦＥＴのゲート、ソース間に過電圧が
印加された場合、前記双方向トランジスタはゲートが開
放でソース、ドレイン間降伏電圧ＶCEO を越えた降伏状
態になり電流が流れる。（以下、この動作をＶCEO モー
ド動作と記す）従って、上記ＦＥＴのゲート酸化膜８は
必要以上の電圧の印加によって破壊されず、双方向トラ
ンジスタ１９によって保護される。When an overvoltage is applied between the gate and source of the FET, the bidirectional transistor is in a breakdown state in which the gate is open and the breakdown voltage V CEO between the source and drain is exceeded, and a current flows. (Hereinafter, this operation will be referred to as V CEO mode operation.) Therefore, the gate oxide film 8 of the FET is not destroyed by application of a voltage higher than necessary, and is protected by the bidirectional transistor 19.
【０００６】上記の双方向トランジスタ１９は、ＦＥＴ
のＰ- 型ベース領域４、Ｎ+ 型ソース領域６と同時に形
成できる。しかし、双方向トランジスタがトレンチ７を
備えたＦＥＴと同一のＮ- 型エピタキシャル層２内に作
られるので、寄生動作等により素子の誤動作や破壊等の
不具合が発生する場合がある。The bidirectional transistor 19 is an FET.
Can be formed simultaneously with the P − type base region 4 and the N + type source region 6. However, since the bidirectional transistor is formed in the same N − type epitaxial layer 2 as the FET provided with the trench 7, malfunction such as device malfunction or destruction may occur due to parasitic operation or the like.
【０００７】[0007]
【発明が解決しようとする課題】上記のように従来の構
造のトレンチを有するＦＥＴの保護回路の場合、保護用
双方向ツェナーダイオードの耐圧を確保しようとすると
製造工程が増加し、保護用双方向トランジスタを用いた
場合寄生動作によるＦＥＴの誤動作が生じるという問題
があった。この発明の目的は、製作工程が少なく、しか
も寄生動作等を起こさない保護回路を内蔵した半導体装
置を提供することにある。As described above, in the case of the FET protection circuit having the conventional trench structure, an attempt to secure the breakdown voltage of the protective bidirectional Zener diode increases the number of manufacturing steps, and the protective bidirectional When a transistor is used, there is a problem that the FET malfunctions due to parasitic operation. An object of the present invention is to provide a semiconductor device which has a small number of manufacturing steps and has a built-in protection circuit which does not cause a parasitic operation or the like.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決し目的を
達成するために、この発明の半導体装置においては以下
の手段を講じた。 （１）請求項１に記載した本発明の半導体装置は、第１
導電型または第２導電型いずれか一方の半導体基板と、
前記半導体基板内に形成された第２導電型の高濃度埋込
み層と、前記半導体基板及び前記込み層上に形成された
前記半導体基板とともにドレインを形成する第１導電型
の低濃度エピタキシャル層とを備えている。前記埋込み
層上の前記エピタキシャル層と前記半導体基板上の前記
エピタキシャル層を分離するように前記エピタキシャル
層を貫いて前記埋込み層に達して形成されたトレンチ構
造の分離部と、前記分離部によって囲まれた前記エピタ
キシャル層内に形成された第２導電型の第１領域と、前
記第１領域内に形成される二つの第１導電型の高濃度第
２領域とからなる双方向トランジスタとを備えている。
前記半導体基板上の前記エピタキシャル層内に形成され
たベース領域としての第２導電型の低濃度第３領域と、
前記第３領域内に形成されたソース領域としての第１導
電型の高濃度第４領域と、前記第４領域と前記第３領域
とを貫いて前記エピタキシャル層に達して形成されたト
レンチ構造のゲートとを備えている。前記ゲートと前記
双方向トランジスタの一方の前記第２領域とを導通させ
る第１電極と、前記第４領域と前記双方向トランジスタ
の他方の前記第２領域とを導通させる第２電極とを備え
ている。In order to solve the above problems and achieve the object, the following means have been taken in the semiconductor device of the present invention. (1) The semiconductor device of the present invention according to claim 1 is the first
A semiconductor substrate of either conductivity type or second conductivity type;
A second conductivity type high-concentration buried layer formed in the semiconductor substrate, and a first conductivity type low-concentration epitaxial layer forming a drain together with the semiconductor substrate and the semiconductor substrate formed on the buried layer. I have it. An isolation portion having a trench structure formed by penetrating the epitaxial layer to reach the embedded layer so as to isolate the epitaxial layer on the embedded layer and the epitaxial layer on the semiconductor substrate, and is surrounded by the isolated portion. And a bidirectional transistor including a first region of the second conductivity type formed in the epitaxial layer and two high-concentration second regions of the first conductivity type formed in the first region. There is.
A second conductivity type low concentration third region as a base region formed in the epitaxial layer on the semiconductor substrate;
A high-concentration fourth region of the first conductivity type as a source region formed in the third region, and a trench structure formed by reaching the epitaxial layer through the fourth region and the third region. It is equipped with a gate. A first electrode for electrically connecting the gate to the second region of one of the bidirectional transistors; and a second electrode for electrically connecting the fourth region to the second region of the other of the bidirectional transistor. There is.
【０００９】上記本発明の半導体装置においては、前記
第１トレンチと前記第２トレンチとは同時に形成され、
前記第１トレンチによって前記ＦＥＴを形成する領域と
分離された前記島状領域が形成される。この島状領域内
にゲート酸化膜保護のための双方向トランジスタを形成
するので、寄生動作が生じない。また、製造工程が長く
ならず、コストが安くなる。In the above semiconductor device of the present invention, the first trench and the second trench are formed simultaneously.
The first trench forms the island-shaped region separated from the region where the FET is formed. Since a bidirectional transistor for protecting the gate oxide film is formed in this island region, parasitic operation does not occur. In addition, the manufacturing process does not become long and the cost is low.
【００１０】また、請求項２に示すように、前記半導体
基板は第１導電型半導体であり、この半導体基板、前記
エピタキシャル層、前記ベース領域、前記ソース領域及
び前記ゲートにより電界効果トランジスタを構成する。According to a second aspect of the present invention, the semiconductor substrate is a first conductivity type semiconductor, and the semiconductor substrate, the epitaxial layer, the base region, the source region and the gate form a field effect transistor. .
【００１１】上記本発明の半導体装置においては、前記
双方向トランジスタと前記ＦＥＴとの間の寄生動作によ
る素子誤動作、破壊等が起こらない。また、請求項３に
示すように、前記半導体基板は第２導電型半導体であ
り、この半導体基板、前記エピタキシャル層、前記ベー
ス領域、前記ソース領域及び前記ゲートにより絶縁ゲー
トバイポーラトランジスタを構成する。In the semiconductor device of the present invention described above, element malfunction or destruction due to parasitic operation between the bidirectional transistor and the FET does not occur. Further, as described in claim 3, the semiconductor substrate is a second conductivity type semiconductor, and the semiconductor substrate, the epitaxial layer, the base region, the source region and the gate form an insulated gate bipolar transistor.
【００１２】上記本発明の半導体装置においては、前記
双方向トランジスタと前記ＩＧＢＴとの間の寄生動作に
よる素子誤動作、破壊等が起こらない。また、請求項４
に示すように、トレンチ構造の前記分離部及びトレンチ
構造の前記ゲートはともにトレンチの側壁に形成された
酸化膜及びトレンチ内に形成されたポリシリコンを備え
ている。In the semiconductor device of the present invention described above, element malfunction or destruction due to parasitic operation between the bidirectional transistor and the IGBT does not occur. Claim 4
As shown in FIG. 3, both the isolation portion of the trench structure and the gate of the trench structure include an oxide film formed on the sidewall of the trench and polysilicon formed in the trench.
【００１３】上記本発明の半導体装置においては、前記
第１トレンチと前記第２トレンチの内部が酸化膜及びポ
リシリコン電極から成っている同一構造なので、前記ゲ
ートと前記分離部が同一工程で形成される。In the semiconductor device of the present invention, since the inside of the first trench and the inside of the second trench are made of an oxide film and a polysilicon electrode and have the same structure, the gate and the isolation portion are formed in the same step. It
【００１４】また、請求項５に示すように、前記分離部
はリング状に形成される。上記本発明の半導体装置にお
いては、第１導電型低濃度エピタキシャル層の分離部を
形成する第１トレンチがリング状をしているので、トレ
ンチを製作しやすい。Further, as described in claim 5, the separating portion is formed in a ring shape. In the above semiconductor device of the present invention, the first trench forming the isolation portion of the first-conductivity-type low-concentration epitaxial layer has a ring shape, so that the trench can be easily manufactured.
【００１５】[0015]
【発明の実施の形態】以下、この発明の実施の形態に係
る半導体装置について図面を参照して説明する。図１は
本発明の実施の形態の断面図である。ＦＥＴ及び双方向
トランジスタ１９の構造については図２（ｂ）の場合と
同じ構造であるので、同一符号を付し説明を省略する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor devices according to the embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention. The structures of the FET and the bidirectional transistor 19 are the same as those in the case of FIG. 2B, so the same reference numerals are given and the description thereof is omitted.
【００１６】Ｎ+ 型（第１導電型）シリコン半導体基板
１内の一部にはＰ+ 型埋込み層（第２導電型の高濃度埋
込み層）１５が形成され、Ｎ- 型エピタキシャル層（第
１導電型の低濃度エピタキシャル層）２が半導体基板１
表面からＰ+ 型埋込み層１５に接して形成されている。A P + type buried layer (second conductivity type high-concentration buried layer) 15 is formed in a part of the N + type (first conductivity type) silicon semiconductor substrate 1, and an N − type epitaxial layer (first layer) is formed. 1 conductivity type low concentration epitaxial layer) 2 is a semiconductor substrate 1
It is formed in contact with the P + type buried layer 15 from the surface.
【００１７】また、前記エピタキシャル層２内には第１
トレンチ１６がエピタキシャル層２の表面からＰ+ 型埋
込み層１５に達するようにリング状に形成されている。
従って、この第１トレンチ１６とＰ+ 型埋込み層１５と
によって囲まれた島状領域１７はＦＥＴを形成する領域
と全く分離される。In the epitaxial layer 2, a first
The trench 16 is formed in a ring shape so as to reach the P + type buried layer 15 from the surface of the epitaxial layer 2.
Therefore, the island region 17 surrounded by the first trench 16 and the P + type buried layer 15 is completely separated from the region forming the FET.
【００１８】前記島状領域１７内にはＰ型第１領域（第
２導電型の第１領域）１３、Ｎ+ 型第２領域（第１導電
型の第２領域）１４からなる双方向トランジスタ１９が
形成されている。A bidirectional transistor having a P-type first region (first region of second conductivity type) 13 and an N + -type second region (second region of first conductivity type) 14 in the island region 17. 19 is formed.
【００１９】島状領域１７以外のＮ- 型エピタキシャル
層２に形成されたＰ- 型ベース領域（第２導電型の低濃
度第３領域）４、Ｐ+ 型ベース領域５、Ｎ+ 型ソース領
域（第１導電型の高濃度第４領域）６、Ｐ- 型ベース領
域４及びＮ+ 型ソース領域６を貫いた第２トレンチ７は
ＦＥＴを構成している。また、ゲート電極１２、ソース
電極１１が形成されている。ここで、特に図示していな
いが、ゲート電極１２は、ＦＥＴ及び双方向トランジス
タを含むペレット周辺において双方向トランジスタ１９
の他方のＮ+ 型領域１４とポリシリコンゲート電極９と
を接続させる。P − type base regions (second conductivity type low concentration third regions) 4, P + type base regions 5 and N + type source regions formed in the N − type epitaxial layer 2 other than the island regions 17 are formed. The second trench 7 penetrating the (high-concentration fourth region of the first conductivity type) 6, the P − type base region 4 and the N + type source region 6 constitutes an FET. Further, the gate electrode 12 and the source electrode 11 are formed. Here, although not shown in particular, the gate electrode 12 is the bidirectional transistor 19 around the pellet including the FET and the bidirectional transistor.
The other N + type region 14 is connected to the polysilicon gate electrode 9.
【００２０】前記第１トレンチ１６内には上記第２トレ
ンチ７内と同じく酸化膜２０、ポリシリコン電極２１が
順に形成されている。すなわち、まず、エピタキシャル
層２と島状領域１７内にＦＥＴのＰ型ベース領域、Ｎ+
型ソース領域と双方向トランジスタ１９のＰ型第１領域
１３とＮ+ 型第２領域１４がそれぞれ同時に形成され
る。次に、ＦＥＴの第２トレンチ７、その第２トレンチ
７内のゲート酸化膜８、ポリシリコンゲート電極９と、
第１トレンチ１６、その第１トレンチ１６内の酸化膜２
０、ポリシリコン電極２１はそれぞれ同時に形成され
る。An oxide film 20 and a polysilicon electrode 21 are sequentially formed in the first trench 16 as in the second trench 7. That is, first, in the epitaxial layer 2 and the island-like region 17, the P-type base region of the FET, N +
The type source region and the P type first region 13 and the N + type second region 14 of the bidirectional transistor 19 are simultaneously formed. Next, the second trench 7 of the FET, the gate oxide film 8 in the second trench 7, the polysilicon gate electrode 9,
First trench 16, oxide film 2 in the first trench 16
0 and the polysilicon electrode 21 are simultaneously formed.
【００２１】上記の双方向トランジスタ１９は、上記Ｆ
ＥＴのゲート、ソース間に過電圧が印加された場合Ｖ
CEO モード動作をし、ＦＥＴのゲート酸化膜８が過電圧
の印加によって破壊されないように保護する。The bidirectional transistor 19 has the F
When an overvoltage is applied between the gate and source of ET V
It operates in the CEO mode and protects the gate oxide film 8 of the FET from being destroyed by the application of overvoltage.
【００２２】本発明の実施の形態においては、製造工程
を削減でき、コストを低廉化できる。また、保護用の双
方向トランジスタ１９のあるＮ- 型エピタキシャル層２
の島状領域１７と、ＦＥＴのあるＮ- 型エピタキシャル
層２の領域とが完全に分離されているため、寄生動作が
生じることがなく、素子の誤動作を防止できる。 （変形例）本発明の実施の形態のＦＥＴをＩＧＢＴに置
き換えることもできる。ＩＧＢＴの構成は、半導体基板
の導電型を変えるだけであり、他は本発明の実施の形態
のＦＥＴと同じ構造である。すなわち、半導体基板１を
Ｐ+ 型半導体基板とすることにより、ＩＧＢＴを構成で
きる。In the embodiment of the present invention, the manufacturing process can be reduced and the cost can be reduced. Further, the N − type epitaxial layer 2 having the bidirectional transistor 19 for protection is provided.
The island-shaped region 17 and the region of the N − type epitaxial layer 2 having the FET are completely separated, so that parasitic operation does not occur and the malfunction of the element can be prevented. (Modification) The FET of the embodiment of the present invention can be replaced with an IGBT. The structure of the IGBT is the same as that of the FET according to the embodiment of the present invention except that the conductivity type of the semiconductor substrate is changed. That is, an IGBT can be formed by using the semiconductor substrate 1 as a P + type semiconductor substrate.
【００２３】この双方向トランジスタを有するＩＧＢＴ
は、本発明の実施の形態の場合と同じように寄生動作が
なく、製造工程が長くなることがなく、ＩＧＢＴのゲー
ト酸化膜８が保護される。IGBT having this bidirectional transistor
In the same manner as in the embodiment of the present invention, there is no parasitic operation, the manufacturing process does not become long, and the gate oxide film 8 of the IGBT is protected.
【００２４】[0024]
【発明の効果】以上説明したように、この発明によれ
ば、製作工程が少なく、しかも寄生動作等を起こさない
保護回路を内蔵した半導体装置を提供できる。As described above, according to the present invention, it is possible to provide a semiconductor device having a small number of manufacturing steps and having a built-in protection circuit which does not cause a parasitic operation.
【図１】本発明の実施の形態に係る半導体装置の断面
図。FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】従来の技術の一例に係る半導体装置の断面図。FIG. 2 is a cross-sectional view of a semiconductor device according to an example of a conventional technique.
１…Ｎ+ 型半導体基板、２…Ｎ- 型エピタキシャル層、
３…ドレイン電極、４…Ｐ- 型ベース領域、５…Ｐ+ 型
ベース領域、６…Ｎ+ 型ソース領域、７…第２トレン
チ、１１…ソース電極、１２…ゲート電極、１３…Ｐ型
第１領域、１４…Ｎ+ 型第２領域、１５…Ｐ+ 型埋込み
層、１６…第１トレンチ、１７…島状領域、２０…酸化
膜、２１…ポリシリコン電極。1 ... N + type semiconductor substrate, 2 ... N − type epitaxial layer,
3 ... Drain electrode, 4 ... P - type base region, 5 ... P + type base region, 6 ... N + type source region, 7 ... Second trench, 11 ... Source electrode, 12 ... Gate electrode, 13 ... P type 1 region, 14 ... N + type second region, 15 ... P + type buried layer, 16 ... First trench, 17 ... Island region, 20 ... Oxide film, 21 ... Polysilicon electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 上月 繁雄 兵庫県姫路市余部区上余部50番地 株式会 社東芝姫路半導体工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeo Kamitsuki, No. 50, Kamimaru, Himeji City, Himeji City, Hyogo Prefecture Stock Company Toshiba Himeji Semiconductor Factory
Claims (5)
の半導体基板と、 前記半導体基板内に形成された第２導電型の高濃度埋込
み層と、 前記半導体基板及び前記埋込み層上に形成された前記半
導体基板とともにドレインを形成する第１導電型の低濃
度エピタキシャル層と、 前記埋込み層上の前記エピタキシャル層と前記半導体基
板上の前記エピタキシャル層を分離するように前記エピ
タキシャル層を貫いて前記埋込み層に達して形成された
トレンチ構造の分離部と、 前記分離部によって囲まれた前記エピタキシャル層内に
形成された第２導電型の第１領域と、前記第１領域内に
形成される二つの第１導電型の高濃度第２領域とからな
る双方向トランジスタと、 前記半導体基板上の前記エピタキシャル層内に形成され
たベース領域としての第２導電型の低濃度第３領域と、 前記第３領域内に形成されたソース領域としての第１導
電型の高濃度第４領域と、 前記第４領域と前記第３領域とを貫いて前記エピタキシ
ャル層に達して形成されたトレンチ構造のゲートと、 前記ゲートと前記双方向トランジスタの一方の前記第２
領域とを導通させる第１電極と、 前記第４領域と前記双方向トランジスタの他方の前記第
２領域とを導通させる第２電極とを備えたことを特徴と
する半導体装置。1. A semiconductor substrate of either the first conductivity type or the second conductivity type, a high-concentration buried layer of the second conductivity type formed in the semiconductor substrate, and the semiconductor substrate and the buried layer. A low-concentration first-conductivity-type epitaxial layer that forms a drain together with the formed semiconductor substrate; and the epitaxial layer on the semiconductor substrate so as to separate the epitaxial layer on the buried layer from the epitaxial layer. An isolation portion having a trench structure formed to reach the buried layer, a second conductivity type first region formed in the epitaxial layer surrounded by the isolation portion, and formed in the first region. A bidirectional transistor including two high-concentration second regions of the first conductivity type, and a base region formed in the epitaxial layer on the semiconductor substrate. Penetrating the second conductivity type low concentration third region, the first conductivity type high concentration fourth region as a source region formed in the third region, the fourth region and the third region. A gate having a trench structure formed to reach the epitaxial layer, the gate and the second one of the bidirectional transistors
A semiconductor device comprising: a first electrode for electrically connecting to a region; and a second electrode for electrically connecting the fourth region and the second region of the other of the bidirectional transistors.
り、この半導体基板、前記エピタキシャル層、前記ベー
ス領域、前記ソース領域及び前記ゲートにより電界効果
トランジスタを構成することを特徴とする請求項１記載
の半導体装置。2. The semiconductor substrate is a first conductivity type semiconductor, and the semiconductor substrate, the epitaxial layer, the base region, the source region and the gate form a field effect transistor. The semiconductor device described.
り、この半導体基板、前記エピタキシャル層、前記ベー
ス領域、前記ソース領域及び前記ゲートにより絶縁ゲー
トバイポーラトランジスタを構成することを特徴とする
請求項１記載の半導体装置。3. The semiconductor substrate is a second conductivity type semiconductor, and the semiconductor substrate, the epitaxial layer, the base region, the source region and the gate form an insulated gate bipolar transistor. 1. The semiconductor device according to 1.
造の前記ゲートはともにトレンチの側壁に形成された酸
化膜及びトレンチ内に形成されたポリシリコンを備えた
ことを特徴とする請求項１記載の半導体装置。4. The isolation portion of the trench structure and the gate of the trench structure both include an oxide film formed on a sidewall of the trench and polysilicon formed in the trench. Semiconductor device.
特徴とする請求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein the isolation portion is formed in a ring shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7323073A JPH09162399A (en) | 1995-12-12 | 1995-12-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7323073A JPH09162399A (en) | 1995-12-12 | 1995-12-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09162399A true JPH09162399A (en) | 1997-06-20 |
Family
ID=18150790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7323073A Pending JPH09162399A (en) | 1995-12-12 | 1995-12-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09162399A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000065646A1 (en) | 1999-04-22 | 2000-11-02 | Williams Richard K | A super-self-aligned trench-gate dmos with reduced on-resistance |
| JP2002026325A (en) * | 2000-06-23 | 2002-01-25 | Fairchild Korea Semiconductor Kk | Mos semiconductor element containing diode for preventing static electricity between gate and emitter |
| JP2003264289A (en) * | 2003-01-27 | 2003-09-19 | Hitachi Ltd | Insulated gate semiconductor device |
| JP2004528719A (en) * | 2001-05-22 | 2004-09-16 | ゼネラル セミコンダクター，インク． | Double diffused metal oxide semiconductor transistor with zener diode for electrostatic discharge protection |
| JP2009512999A (en) * | 2005-09-21 | 2009-03-26 | インターナショナル レクティファイアー コーポレイション | Semiconductor package |
| JP2009289791A (en) * | 2008-05-27 | 2009-12-10 | Nec Electronics Corp | Semiconductor device |
| US8283697B2 (en) | 2009-12-04 | 2012-10-09 | Fuji Electric Co., Ltd. | Internal combustion engine igniter semiconductor device |
| JP2015015329A (en) * | 2013-07-04 | 2015-01-22 | 三菱電機株式会社 | Wide-gap semiconductor device |
-
1995
- 1995-12-12 JP JP7323073A patent/JPH09162399A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000065646A1 (en) | 1999-04-22 | 2000-11-02 | Williams Richard K | A super-self-aligned trench-gate dmos with reduced on-resistance |
| EP1186023A4 (en) * | 1999-04-22 | 2007-02-21 | Richard K Williams | A super-self-aligned trench-gate dmos with reduced on-resistance |
| JP2002026325A (en) * | 2000-06-23 | 2002-01-25 | Fairchild Korea Semiconductor Kk | Mos semiconductor element containing diode for preventing static electricity between gate and emitter |
| JP2004528719A (en) * | 2001-05-22 | 2004-09-16 | ゼネラル セミコンダクター，インク． | Double diffused metal oxide semiconductor transistor with zener diode for electrostatic discharge protection |
| JP2003264289A (en) * | 2003-01-27 | 2003-09-19 | Hitachi Ltd | Insulated gate semiconductor device |
| JP2009512999A (en) * | 2005-09-21 | 2009-03-26 | インターナショナル レクティファイアー コーポレイション | Semiconductor package |
| JP2009289791A (en) * | 2008-05-27 | 2009-12-10 | Nec Electronics Corp | Semiconductor device |
| US8283697B2 (en) | 2009-12-04 | 2012-10-09 | Fuji Electric Co., Ltd. | Internal combustion engine igniter semiconductor device |
| JP2015015329A (en) * | 2013-07-04 | 2015-01-22 | 三菱電機株式会社 | Wide-gap semiconductor device |
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