JPH09148897A - Pn pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a PN pattern even when a clock has a high speed by reducing the number of output per circuit. SOLUTION: This device has a code generation part generating n-parallel PN(pseudo random) codes and a parallel-serial conversion circuit 37 serializing the generated n-parallel PN codes. In this case, the code generation part has plural code generation circuits 311, 321, 331 and 341 generating n-parallel PN codes and selection parts 312, 322, 332 and 342 provided for each code generation circuit 311, 321, 331 and 341. Each selection part 312, 322, 332 and 342 specifies each column of a prescribed number which is smaller than the n from the n- parallel code generated in each code generation circuit 311, 321, 331 and 341 and inputs each column in the parallel-serial conversion circuit 37. In the parallel-serial conversion circuit 37, the n-parallel PN codes are generated and these n-parallel PN code are serialized by bundling the parallel PN codes of each prescribed number from each selection part 312, 322, 332 and 342.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN pattern generator in which, for example, a plurality of PN code (pseudo random code) generating circuits having the same structure operate simultaneously in parallel.

[0002]

2. Description of the Related Art Conventionally, P is used for a confirmation test of normality of a transmission line.
An N pattern generator is used. In this test, a PN code is generated, the PN code is inserted into a transmission line to be detected, and it is judged from the detection result whether the transmission line is normal.

FIG. 3 shows an example of a conventional PN pattern generator. Here, an example of a 23-stage code generator will be given. The PN pattern generator having the configuration shown in FIG.
This is a serial processing PN23 stage code generator, which is composed of 23 (# 1 to # 23) flip-flops 10 and one exclusive OR 12.

In this figure, the output of each flip-flop is input to the next flip-flop, and the output 14 of the 23rd flip-flop (# 23) and the 18th flip-flop (# 18). The result 16 of the exclusive OR with the output 15) is input to the first stage (first stage) flip-flop (# 1). This PN
The output of the pattern generator is an output 13 of the 23-stage flip-flop (final stage) (# 23), a PN23 stage code according to the code generating polynomial X ²³ + X ⁵ +1.
The PN code generated in this way is output in the cycle of the CLK signal 11.

However, in such a serial processing PN pattern generator, the output signal speed thereof depends on the speed of the input CLK signal 11. Therefore, in the PN code generation circuit by serial processing, it is difficult to realize the circuit when the speed of the CLK signal 11 is very high.
Further, when the total number of outputs when the serial pattern output is replaced with the parallel pattern output is large, the number of output pins in one LSI or the like is limited, so that it becomes difficult to output the required total number of signals.

In view of the above, there is known a PN pattern generator that performs parallel processing, in contrast to the above-described PN pattern generator that performs serial processing. An example is shown in FIG. This parallel processing PN pattern generator is an n-parallel version of the PN23-stage code generator shown in FIG. 3, and is composed of an exclusive OR combination circuit 21 and 23 flip-flops 25. The exclusive OR combination circuit 21 inputs the outputs of the 23 flip-flops 25 and outputs n parallel PNs.
Output the code. At this time, as indicated by reference numeral 23 in the figure, any 23 of the n-parallel outputs are not only output to the parallel-serial conversion 24, but also input to the flip-flop 25. This flip-flop 25 is
The CLK signal 27 and any of the above 23 PN codes are input, and the output is an exclusive OR combination circuit 2
1 is connected to the input section.

Of the PN codes of the exclusive OR combination circuit 21, the other (n-23) lines are directly output to the parallel-serial conversion unit 24. Parallel-serial conversion 24
Then, the n-parallel PN code thus input is converted into the serial signal 28 and output. In this way, in the n parallel processing PN pattern generator, the CLK signal 27 is
It is input to the flip 25 at a speed of 1 / n.

In such a configuration, parallel-to-serial converter 24 must operate at the same speed as the circuit of FIG.
It must be implemented by an LSI different from the low speed circuit 2A. However, the operation speed of the circuit 2A other than the parallel-serial conversion 24 is 1 / n of that of the circuit of FIG.
It is possible to realize a circuit by a process LSI such as MOS).

[0009]

However, in the PN pattern generator for n parallel processing shown in FIG. 4, the low speed circuit 2A is used.
The number of signal outputs of n is n, and it is necessary to increase the parallelization number n as the signal speed increases. On the other hand, since the number of output pins is limited, when n is large, it is difficult to realize n outputs with one LSI. Therefore, an object of the present invention is to obtain a PN pattern generation device capable of generating a PN pattern even when the clock is high speed by reducing the number of outputs per circuit.

[0010]

In order to solve the above problems, the present invention provides a code generator for generating an n-parallel PN code and a parallel-serial conversion for serializing the generated n-parallel PN code. In the PN pattern generator including a circuit, the code generation unit is provided for each of the code generation circuits that generate the n-parallel PN code, and is generated by the code generation circuit. a selection unit that specifies a predetermined number of columns smaller than n from the n parallel codes and inputs the columns to the parallel-serial conversion circuit, and the parallel-serial conversion circuit is configured to connect a predetermined number of parallel lines from the selection unit. The PN code is bundled to generate an n-parallel PN code, and the generated n-parallel PN code is serialized.

With this configuration, the output of each PN code generation circuit becomes a value smaller than n, and the number of outputs of the PN code generation circuit can be reduced. Therefore, when implementing a circuit with an LSI or the like, the number of pins can be suppressed. For example, when m code generation circuits are provided, the number of outputs required for PN code output in the PN code generation circuit is n / m. If n is not divisible by m, it is necessary to output as many lines as n / m is rounded up.

Further, a configuration may be provided in which a reset circuit for returning each of the code generation circuits to a desired operation state and synchronizing each code generation circuit is further provided. With such a configuration, the code generation circuits can be easily synchronized.

By using this PN pattern generator, it is possible to generate a PN pattern even when the clock signal has a high speed. Therefore, by sending out the obtained PN pattern to the transmission line and separating and examining the signal from the transmission line, it is possible to perform a test for confirming the normality of the transmission line even when the clock signal is high speed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an n parallel processing PN23 stage code pattern generator according to an embodiment of the present invention. In this embodiment, m PN generator circuits having the same configuration are used to generate a PN23 stage code by n parallel processing. Each of these m PN generation circuits has a function of n in FIG.
A circuit similar to the parallel PN code generation circuit 2A is used, and its output is n / m selected from n, that is, n.
/ M columns. By appropriately selecting the value of n so that the value of n / m is equal to or less than the limit number of output pins,
The number of outputs for each circuit is kept within the limit of the number of output pins.

Specifically, the first PN generating circuit is N
Select the signal line of No. 1 to No. (n / m) among the signal lines of o. 1 to No. n to be the output signal. The second PN generation circuit selects the No. [(n / m) +1] to No. (2n / m) signal lines as output signals. Thus, the i-th circuit (i =
1, 2, 3, ... M) are output signals by selecting n / m signal lines represented by the following equation from the n signal lines.

[0016]

[Equation 1] [(n / m) × (i−1) +1] to (n / m) × i (i = 1, 2, 3 ... m) where i, n, and m are natural numbers

The signal line is selected by an external setting. In this case, since the period of the PN code of each circuit is taken,
Reset required. This is because at the start of circuit operation,
Each circuit may be reset once at the same time. In this way, n / m outputs from m identical circuits, that is, n / m
The m parallel signals are bundled into n columns. The m number of circuits thus obtained can provide an output substantially equal to that of one n-parallel PN pattern generating circuit. Then, as in the conventional case, the n-parallel outputs are parallel-serial converted to obtain a serial PN code.

FIG. 1 shows a concrete example of a PN pattern generator for generating n parallel PN codes in 23 stages of PN when m = 4. In this PN pattern generator, four code generation circuits 31 to 34, which have the same configuration, are simultaneously operated.

In each of the code generation circuits 31 to 34, reference numerals 311, 321, 331 and 341 denote input clocks (C
These are the same code generation circuits that generate n parallel PN codes for each cycle of LK), and the internal circuit configuration is the same as the PN code generation circuit for n parallel processing shown in FIG. The basic configuration of each code generation circuit 31-34 is shown in FIG.
4 is the same as the n-parallel PN code generation circuit 2A shown in FIG. 4 except that a reset circuit 41 and its input are provided.
This is different from the n parallel PN code generation circuit 2A.

These code generation circuits 311, 321, 33
Since 1, 341 takes the cycle of the PN code to be output, it is reset by the reset signal 35 at the start of the circuit operation. The output signal is the external setting signals 314, 3
24, 332, 344 through the n-pair (n / 4) selection circuits 312, 322, 332, 342, respectively.
(N / 4) books are selected in order from the top of the books. The output signals 313, 323, 333, 343 of the n-pair (n / 4) selection circuits 312, 322, 332, 342 are n / 4 parallel signals composed of n / 4 signal lines, respectively. Then, an n-parallel PN code is obtained, and this is converted into a serial code 36 by a parallel-serial conversion 37.

As described above, the four code generation circuits 311 and
Since all of 321, 331, and 341 can be the same circuit, when realizing a high-speed PN code generation circuit, the components other than the parallel-serial conversion circuit can be replaced by a low-speed LSI.
Therefore, the manufacturing cost can be reduced. In addition, each code generation circuit 311, 321, 3
It is possible to suppress the number of pins required for 31, 341 to a predetermined manufacturable value or less.

[0022]

As is apparent from the above description, according to the present invention, the PN pattern output can be easily obtained even when the clock signal has a high speed. Further, since the number of outputs required in each PN code generation circuit is reduced, it is possible to easily obtain a multi-parallel PN pattern output. Further, all the constituent elements other than the parallel-serial conversion circuit can be realized by a low-speed LSI, which is very advantageous in manufacturing.

[Brief description of the drawings]

FIG. 1 is a PN2 of n parallel processing according to an embodiment of the present invention.
The block diagram of a 3-stage code pattern generator.

FIG. 2 is a detailed configuration diagram of the code generation circuit according to the present embodiment.

FIG. 3 is a configuration diagram of a serial processing PN23 stage code pattern generator according to a conventional technique.

FIG. 4 is a detailed configuration diagram of a code generation circuit for n parallel processing according to a conventional technique.

[Explanation of symbols]

31-32 PN generation circuit 311, 321, 331, 341 Code generation circuit 312x, 322, 332, 342 n pairs (n / 4)
Selection circuit 37 Series-parallel conversion circuit

Claims (2)

[Claims] 1. A PN pattern generation device comprising a code generation unit for generating an n-parallel PN code and a parallel-serial conversion circuit for serializing the generated n-parallel PN code. The unit specifies a plurality of code generation circuits that generate the n-parallel PN code and a predetermined number of columns smaller than n from the n parallel codes that are provided for each code generation circuit and are generated by the code generation circuit. And inputting to the parallel-serial conversion circuit, the parallel-serial conversion circuit generates an n-parallel PN code by bundling a predetermined number of parallel PN codes from the selection unit. , A PN pattern generator which serializes the generated n parallel PN codes. 2. The PN pattern generator according to claim 1, further comprising a reset circuit for returning the plurality of code generation circuits to a desired operation state and synchronizing each code generation circuit.