JPH09148284A - Method and apparatus for chemical-mechanical polishing and manufacture of semiconductor substrate - Google Patents
Method and apparatus for chemical-mechanical polishing and manufacture of semiconductor substrateInfo
- Publication number
- JPH09148284A JPH09148284A JP31019195A JP31019195A JPH09148284A JP H09148284 A JPH09148284 A JP H09148284A JP 31019195 A JP31019195 A JP 31019195A JP 31019195 A JP31019195 A JP 31019195A JP H09148284 A JPH09148284 A JP H09148284A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- chemical
- insulating film
- substrate
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体集積回路等
を製造するための基板上に形成される絶縁膜、金属膜等
の表面を平坦に化学的・機械的な研磨加工する研磨加工
方法及びその装置並びに半導体集積回路等を有する半導
体基板を製造する半導体基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing method for flattening a surface of an insulating film, a metal film or the like formed on a substrate for manufacturing a semiconductor integrated circuit or the like by chemical / mechanical polishing. The present invention relates to a semiconductor substrate manufacturing method for manufacturing a semiconductor substrate having the device and a semiconductor integrated circuit.
【0002】[0002]
【従来の技術】例えば、半導体集積回路等を有する半導
体基板を製造する際の平坦化技術としては、従来、プラ
ズマ酸化膜(P−SiO2)を形成し、その表面の微小
凹凸を無くすべく表面上に液体状のガラスを塗布、加熱
することによって塗布絶縁膜(SOG)を形成し、絶縁
膜の膜厚を減少させるためにエッチバックを行うことの
組合せによって行われてきた。しかしこの平坦化技術に
おいては、大きな段差は残ってしまうことになる。更
に、配線幅の減少に伴って、段差被覆性の向上の必要性
から、Bias−ECRCVD技術及びリフロー効果を
有する有機ソース(TEOS)などの開発が行われてき
た。しかしながら、超高集積化に伴う配線幅の減少に対
して十分段差被覆性の向上が図れることが得られない状
況であった。他方、半導体チップ、セラミックパッケー
ジ、多層セラミックパッケージ及び他の電子部品の表面
を平坦に研磨する化学的・機械的な研磨(CMP:Chem
icalMechanical Polishing)技術について、米国特許第
4954142号の明細書及び図面において知られてい
る。この従来技術は、研磨定盤上に支持され、研磨剤を
塗布した研磨布に上記電子部品の表面を押付けて化学的
・機械的な研磨加工するCMP(Chemical Mechanical
Polishing)である。2. Description of the Related Art For example, as a flattening technique for manufacturing a semiconductor substrate having a semiconductor integrated circuit or the like, conventionally, a plasma oxide film (P-SiO 2 ) is formed and the surface thereof is formed so as to eliminate fine irregularities. This has been performed by a combination of forming a coated insulating film (SOG) by applying liquid glass on the glass and heating it, and performing etch back to reduce the thickness of the insulating film. However, in this flattening technique, a large step remains. Further, as the wiring width decreases, the need for improvement of step coverage has led to the development of Bias-ECRCVD technology and an organic source (TEOS) having a reflow effect. However, it has not been possible to sufficiently improve the step coverage with respect to the reduction of the wiring width accompanying the ultra-high integration. On the other hand, chemical and mechanical polishing (CMP: Chem) for flatly polishing the surfaces of semiconductor chips, ceramic packages, multilayer ceramic packages and other electronic components.
The mechanical mechanical polishing technique is known in the specification and drawings of US Pat. No. 4,954,142. This conventional technique is a CMP (Chemical Mechanical) which is supported on a polishing surface plate and presses the surface of the electronic component against a polishing cloth coated with an abrasive to chemically and mechanically polish the surface.
Polishing).
【0003】[0003]
【発明が解決しようとする課題】上記従来技術(CM
P)では、化学的・機械的な研磨加工中の被加工物の変
形に伴う、研磨圧力の変動に対する配慮がなされていな
いため、被加工物の表面内の絶縁膜等の研磨量を制御で
きず、絶縁膜等の厚さを均一にできないという課題を有
していた。The above prior art (CM)
In P), since the fluctuation of the polishing pressure due to the deformation of the workpiece during the chemical / mechanical polishing is not taken into consideration, the polishing amount of the insulating film on the surface of the workpiece can be controlled. Therefore, there is a problem that the thickness of the insulating film or the like cannot be made uniform.
【0004】本発明の目的は、上記課題を解決すべく、
基板上に形成された絶縁膜等の厚さを均一に研磨加工を
実現できるようにした化学的・機械的な研磨加工方法及
びその装置を提供することにある。また本発明の目的
は、半導体基板上における層間絶縁膜の表面に微小凹凸
がなく、しかも大きな段差を有しない平坦な化学的・機
械的な研磨加工を施してその上に例えば0.35μm以
下の極微細配線を形成できるようにした化学的・機械的
な研磨加工方法及びその装置を提供することにある。ま
た本発明の目的は、配線幅が、例えば0.35μm以下
の極微細配線を有する多層配線層を形成した半導体基板
を簡略化して製造できるようにした半導体基板の製造方
法を提供することになる。[0004] An object of the present invention is to solve the above problems.
It is an object of the present invention to provide a chemical / mechanical polishing method and apparatus capable of achieving uniform polishing of the thickness of an insulating film or the like formed on a substrate. Another object of the present invention is to carry out a flat chemical / mechanical polishing process on the surface of the interlayer insulating film on the semiconductor substrate, which has no fine irregularities and has no large steps, and which is, for example, 0.35 μm or less. It is an object of the present invention to provide a chemical / mechanical polishing method and apparatus capable of forming ultrafine wiring. Another object of the present invention is to provide a method of manufacturing a semiconductor substrate, which can simplify the manufacturing of a semiconductor substrate having a multilayer wiring layer having an ultrafine wiring having a wiring width of 0.35 μm or less. .
【0005】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、基板面内の複数の2次元領域の各々にお
ける研磨圧力を制御して上記基板面に対して化学的・機
械的な研磨加工を行うことを特徴とする化学的・機械的
な研磨加工方法である。また本発明は、基板面内の複数
の2次元領域の各々における研磨圧力の分布をインプロ
セスで測定し、この測定された2次元領域の各々におけ
る研磨圧力の分布に応じて2次元領域の各々における研
磨圧力を制御して上記基板面の化学的・機械的な研磨加
工を行うことを特徴とする化学的・機械的な研磨加工方
法である。また本発明は、基板面内の複数の2次元領域
の各々における研磨圧力を制御して上記基板上の絶縁膜
表面の化学的・機械的な研磨加工を行うことを特徴とす
る化学的・機械的な研磨加工方法である。In order to achieve the above object, the present invention controls the polishing pressure in each of a plurality of two-dimensional regions in the surface of a substrate to chemically or mechanically act on the surface of the substrate. It is a chemical / mechanical polishing method characterized by performing various polishing processes. Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions in the substrate surface is measured by in-process, and each of the two-dimensional regions is determined according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform the chemical / mechanical polishing of the substrate surface. Further, the present invention is characterized in that the polishing pressure in each of a plurality of two-dimensional regions in the surface of the substrate is controlled to chemically and mechanically polish the surface of the insulating film on the substrate. Polishing method.
【0006】また本発明は、基板面内の複数の2次元領
域の各々における研磨圧力の分布をインプロセスで測定
し、この測定された2次元領域の各々における研磨圧力
の分布に応じて2次元領域の各々における研磨圧力を制
御して上記基板上の絶縁膜表面の化学的・機械的な研磨
加工を行うことを特徴とする化学的・機械的な研磨加工
方法である。また本発明は、基板面内の複数の2次元領
域の各々における研磨圧力を制御して上記基板上の金属
膜表面の化学的・機械的な研磨加工を行うことを特徴と
する化学的・機械的な研磨加工方法である。また本発明
は、基板面内の複数の2次元領域の各々における研磨圧
力の分布をインプロセスで測定し、この測定された2次
元領域の各々における研磨圧力の分布に応じて2次元領
域の各々における研磨圧力を制御して上記基板上の金属
膜表面の化学的・機械的な研磨加工を行うことを特徴と
する化学的・機械的な研磨加工方法である。Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions on the surface of the substrate is measured by in-process, and the two-dimensional calculation is performed according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure in each region is controlled to perform the chemical / mechanical polishing process on the surface of the insulating film on the substrate. Further, the present invention is characterized in that the polishing pressure in each of a plurality of two-dimensional regions in the surface of the substrate is controlled to chemically and mechanically polish the surface of the metal film on the substrate. Polishing method. Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions in the substrate surface is measured by in-process, and each of the two-dimensional regions is determined according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform chemical / mechanical polishing of the surface of the metal film on the substrate.
【0007】また本発明は、基板面内の複数の2次元領
域の各々における研磨圧力を制御して上記基板上の絶縁
膜表面の研磨量ばらつきを±5%以下で、該絶縁膜表面
の凹凸を0.2μm以下で化学的・機械的な研磨加工を
行うことを特徴とする化学的・機械的な研磨加工方法で
ある。また本発明は、基板面内の複数の2次元領域の各
々における研磨圧力の分布をインプロセスで測定し、こ
の測定された2次元領域の各々における研磨圧力の分布
に応じて2次元領域の各々における研磨圧力を制御して
上記基板上の絶縁膜表面の研磨量ばらつきを±5%以下
で、該絶縁膜表面の凹凸を0.2μm以下で化学的・機
械的な研磨加工を行うことを特徴とする化学的・機械的
な研磨加工方法である。また本発明は、上記化学的・機
械的な研磨加工方法において、上記2次元領域は、実質
的に同心状の領域であることを特徴とする。Further, according to the present invention, the polishing pressure in each of a plurality of two-dimensional regions in the substrate surface is controlled so that the variation in the polishing amount on the surface of the insulating film on the substrate is ± 5% or less, and the unevenness of the surface of the insulating film is controlled. Is 0.2 μm or less, and a chemical / mechanical polishing process is performed. Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions in the substrate surface is measured by in-process, and each of the two-dimensional regions is determined according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The polishing pressure is controlled to control the polishing amount variation of the insulating film surface on the substrate to be ± 5% or less, and the unevenness of the insulating film surface to be 0.2 μm or less for chemical / mechanical polishing. Is a chemical / mechanical polishing method. Further, the present invention is characterized in that, in the above-mentioned chemical / mechanical polishing method, the two-dimensional region is a substantially concentric region.
【0008】また本発明は、基板上の下層配線上に層間
絶縁膜を形成する層間絶縁膜形成工程と、該層間絶縁膜
形成工程で形成された層間絶縁膜上の複数の2次元領域
の各々における研磨圧力を制御して上記層間絶縁膜表面
の化学的・機械的な研磨加工を行って平坦化する化学的
・機械的な研磨加工工程と、該化学的・機械的な研磨加
工工程で平坦された上記層間絶縁膜上に所望の上層配線
を形成する上層配線形成工程とを有することを特徴とす
る半導体基板の製造方法である。また本発明は、基板上
の下層配線上に層間絶縁膜を形成する層間絶縁膜形成工
程と、該層間絶縁膜形成工程で形成された層間絶縁膜上
の複数の2次元領域の各々における研磨圧力を制御して
上記層間絶縁膜表面に対して化学的・機械的な研磨加工
を行って平坦化する化学的・機械的な研磨加工工程と、
該化学的・機械的な研磨加工工程で平坦化された層間絶
縁膜に対してコンタクトホールを形成するコンタクトホ
ール形成工程と、該コンタクトホール形成工程で形成さ
れたコンタクトホールに導電材を埋め込んでコンタクト
スタッドを形成するコンタクトスタッド形成工程と、該
コンタクトスタッド形成工程の後、上記層間絶縁膜上に
所望の上層配線を形成する上層配線形成工程とを有する
ことを特徴とする半導体基板の製造方法である。Further, according to the present invention, an interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step, respectively. And polishing by controlling the polishing pressure at the surface of the interlayer insulating film to be planarized by chemical / mechanical polishing, and the step of flattening by the chemical / mechanical polishing Upper layer wiring forming step of forming a desired upper layer wiring on the above-described interlayer insulating film, and a method of manufacturing a semiconductor substrate. The present invention also provides an interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. And a chemical / mechanical polishing step of performing flattening by performing chemical / mechanical polishing on the surface of the interlayer insulating film,
A contact hole forming step of forming a contact hole in the interlayer insulating film flattened in the chemical / mechanical polishing step, and a contact by filling a conductive material in the contact hole formed in the contact hole forming step. A method for manufacturing a semiconductor substrate, comprising: a contact stud forming step of forming a stud; and an upper layer wiring forming step of forming a desired upper layer wiring on the interlayer insulating film after the contact stud forming step. .
【0009】また本発明は、基板上の下層配線上に層間
絶縁膜を形成する層間絶縁膜形成工程と、該層間絶縁膜
形成工程で形成された層間絶縁膜上の複数の2次元領域
の各々における研磨圧力を制御して上記層間絶縁膜表面
の化学的・機械的な研磨加工を行う化学的・機械的な研
磨加工工程と、該化学的・機械的な研磨加工工程で平坦
された上記層間絶縁膜上にSiO2膜をCVDによって
形成するSiO2膜形成工程と、該SiO2膜形成工程で
形成されたSiO2膜上に上層配線を形成する上層配線
形成工程とを有することを特徴とする半導体基板の製造
方法である。また本発明は、基板の裏面から付与する流
体圧力を制御して上記基板面内の複数の2次元領域の各
々における研磨圧力を制御する制御手段を備え、上記基
板の表面を平坦に化学的・機械的な研磨加工を施すよう
に構成したことを特徴とする化学的・機械的な研磨加工
装置である。Further, according to the present invention, an interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step, respectively. Chemical / mechanical polishing step of controlling the polishing pressure in the step of chemically / mechanically polishing the surface of the interlayer insulating film, and the interlayer flattened by the chemical / mechanical polishing step. and characterized in that it comprises a SiO 2 film forming step of forming by CVD a SiO 2 film on the insulating film, an upper layer wiring forming step of forming an upper layer wiring on the SiO 2 film formed by the SiO 2 film forming step And a method for manufacturing a semiconductor substrate. Further, the present invention comprises a control means for controlling the fluid pressure applied from the back surface of the substrate to control the polishing pressure in each of the plurality of two-dimensional regions in the surface of the substrate, and chemically controls the surface of the substrate to be flat. The chemical / mechanical polishing apparatus is characterized by being configured to perform mechanical polishing processing.
【0010】また本発明は、基板面内における複数の2
次元領域の各々における研磨圧力の分布をインプロセス
で測定する測定手段と、該測定手段で測定された2次元
領域の各々における研磨圧力の分布に応じて上記基板の
裏面から付与する流体圧力を制御して上記2次元領域の
各々における研磨圧力を制御する制御手段とを備え、上
記基板の表面を化学的・機械的な研磨加工を施すように
構成したことを特徴とする化学的・機械的な研磨加工装
置である。以上説明したように本発明によれば、例えば
半導体装置における層間絶縁膜の厚さを均一にすること
ができるので、半導体装置の高信頼度と高集積化を実現
することができる。即ち、半導体集積回路は多層配線層
を形成するため、下層配線と上層配線の間に層間絶縁層
が存在し、この層間絶縁膜の表面を、たとえば研磨量ば
らつきを±5%以下の精度で、しかも微小凹凸を0.2
μm以下を実現することができ、その結果層間絶縁膜の
上に均一な厚さの配線膜を形成でき、しかも露光におけ
る焦点マージンが拡大して容易に配線幅が0.35μm
以下の配線を形成することができる。また研磨前に層間
絶縁膜の表面に存在した1μm程度の段差を、研磨後に
0.1μm以下の微小凹凸にすることができ、その結果
該層間絶縁層の表面に配線幅が0.25μm以下の配線
を容易に形成することができる。The present invention also provides a plurality of two in-plane substrates.
Measuring means for in-process measuring the distribution of the polishing pressure in each of the two-dimensional areas, and controlling the fluid pressure applied from the back surface of the substrate according to the distribution of the polishing pressure in each of the two-dimensional areas measured by the measuring means. And a control means for controlling the polishing pressure in each of the two-dimensional regions, and the chemical and mechanical polishing is performed on the surface of the substrate. It is a polishing device. As described above, according to the present invention, for example, the thickness of the interlayer insulating film in the semiconductor device can be made uniform, so that high reliability and high integration of the semiconductor device can be realized. That is, since the semiconductor integrated circuit forms a multilayer wiring layer, an interlayer insulating layer exists between the lower layer wiring and the upper layer wiring, and the surface of this interlayer insulating film has, for example, a polishing amount variation of ± 5% or less with accuracy. Moreover, the fine unevenness is 0.2
A wiring film having a uniform thickness can be formed on the interlayer insulating film, and a focus margin in exposure can be expanded to easily form a wiring width of 0.35 μm.
The following wiring can be formed. Further, a step of about 1 μm existing on the surface of the interlayer insulating film before polishing can be made into a minute unevenness of 0.1 μm or less after polishing, and as a result, a wiring width of 0.25 μm or less can be formed on the surface of the interlayer insulating layer. Wiring can be easily formed.
【0011】また本発明によれば、層間絶縁層に形成さ
れたコンタクトホールにタングステン等の導電体をコン
タクトスタンドとして選択CVDで形成する際、上記層
間絶縁膜上の微小な欠陥を核として成長したタングステ
ン等の導電膜が完全に除去することができ、層間絶縁膜
上に高信頼度を有する配線を形成することができる効果
を奏する。また本発明によれば、絶縁膜または金属膜の
表面において高い平坦度を得ることができるので、例え
ば露光工程において焦点ずれを防止して精度の高い解像
度の露光を実現し、高集積化を達成することができる。Further, according to the present invention, when a conductor such as tungsten is formed as a contact stand in the contact hole formed in the interlayer insulating layer by selective CVD, the fine defects on the interlayer insulating film grow as nuclei. There is an effect that the conductive film such as tungsten can be completely removed, and the wiring having high reliability can be formed on the interlayer insulating film. Further, according to the present invention, since high flatness can be obtained on the surface of the insulating film or the metal film, for example, defocusing can be prevented in the exposure process, exposure with high resolution can be realized, and high integration can be achieved. can do.
【0012】[0012]
【発明の実施の形態】本発明の実施の形態について図面
を用いて説明する。本発明に係る化学的・機械的な研磨
加工装置の一実施形態を示す全体構成および研磨加工要
領を、図1を参照して説明する。図1は化学的・機械的
な研磨加工装置の概念図である。図1において、被加工
物1(ウエハ(半導体基板)等の基板)は、チャック2
に取り付けられている。研磨定盤4の上に、平坦化を良
くするために酸とかアルカリに強く耐摩耗性に優れた例
えば硬質発泡ポリウレタン系の研磨パッド5が取り付け
られている。研磨パッド5の上に、アルカリを含む溶液
にSiO2の砥粒を入れたコロイダルシリカや、酸を含
む溶液にアルミナや酸化セリウムの砥粒を入れた研磨液
6が供給される。研磨定盤4に設置された荷重センサ7
は信号線a8、スリップリング9及び信号線b10を介
して制御装置11に接続している。圧力制御弁14は、
信号線c12を介して制御装置11に接続している。流
体13は、流量制御弁14、流体供給管15及びロータ
リージョイント16を介してチャック2に供給される。
モータ3は信号線d17を介して制御装置11に接続し
ている。2は、モータ3によって回転可動なチャックで
ある。Embodiments of the present invention will be described with reference to the drawings. An overall configuration and a polishing procedure showing an embodiment of a chemical / mechanical polishing apparatus according to the present invention will be described with reference to FIG. FIG. 1 is a conceptual diagram of a chemical and mechanical polishing apparatus. In FIG. 1, a workpiece 1 (a substrate such as a wafer (semiconductor substrate)) is a chuck 2
Attached to. On the polishing platen 4, a polishing pad 5 made of, for example, a hard polyurethane foam, which is resistant to acids and alkalis and has excellent wear resistance, is attached to improve the flatness. On the polishing pad 5, colloidal silica containing SiO 2 abrasive grains in a solution containing alkali, and polishing liquid 6 containing alumina or cerium oxide abrasive grains in a solution containing acid are supplied. Load sensor 7 installed on the polishing surface plate 4
Is connected to the control device 11 via a signal line a8, a slip ring 9 and a signal line b10. The pressure control valve 14 is
It is connected to the control device 11 via a signal line c12. The fluid 13 is supplied to the chuck 2 via the flow rate control valve 14, the fluid supply pipe 15 and the rotary joint 16.
The motor 3 is connected to the control device 11 via a signal line d17. Reference numeral 2 is a chuck that is rotatable by a motor 3.
【0013】化学的・機械的な研磨加工は、図1に示す
ように回転する研磨パッド5上に研磨液6を供給しなが
ら、チャック2で支持した被加工物1を研磨パッド5の
上に接触させ、さらにモータ3によって回転するチャッ
ク2に研磨荷重を加えて矢印43で示すように研磨定盤
4の半径方向に研磨定盤4との間で相対的に往復移動し
ながら、上記研磨液6に含まれる例えばアルカリ溶液と
の化学反応による化学的研磨と、SiO2等の砥粒とに
よる機械的な研磨との併用による化学的・機械的な研磨
加工(CMP:Chemical Mechanical Polishing)が被
加工物(例えばウエハ等の半導体基板における絶縁膜の
表面)1に対して行われる。即ち、被加工物1が、半導
体基板における絶縁膜(例えばプラズマTEOS膜等)
である場合、回転する研磨パッド5上に研磨液6を供給
しながら、チャック2で支持した半導体基板における絶
縁膜を研磨パッド5の上に接触させ、さらにモータ3に
よって回転するチャック2に研磨荷重を加えて矢印43
で示すように研磨定盤4の半径方向に研磨定盤4との間
で相対的に往復移動させると、絶縁膜の表面は上記研磨
液6に含まれるアルカリ溶液との間で化学的反応が行わ
れながら上記研磨液6に含まれるSiO2等の砥粒とに
よって機械的な研磨が行われて化学的・機械的な研磨加
工が進行し、微小凹凸が0.01μm以下の平坦化され
た、研磨量のばらつきが±5%以下の所望の膜厚を有す
る層間絶縁膜を得ることができる。なお金属膜に対する
化学的・機械的な研磨加工の場合には、研磨液6として
はアルカリを含む溶液にSiO2の砥粒を入れたコロイ
ダルシリカや、酸を含む溶液にアルミナや酸化セリウム
等の砥粒を入れたものが用いられる。In the chemical / mechanical polishing process, the workpiece 1 supported by the chuck 2 is placed on the polishing pad 5 while supplying the polishing liquid 6 onto the rotating polishing pad 5 as shown in FIG. When the polishing load is applied to the chuck 2 which is brought into contact with the chuck 2 and is rotated by the motor 3, the polishing liquid is relatively reciprocated relative to the polishing platen 4 in the radial direction of the polishing platen 4 as shown by an arrow 43. Chemical mechanical polishing (CMP: Chemical Mechanical Polishing) is performed by a combination of chemical polishing by a chemical reaction with an alkaline solution contained in 6 and mechanical polishing by abrasive grains such as SiO 2. It is performed on a workpiece (for example, the surface of an insulating film on a semiconductor substrate such as a wafer) 1. That is, the workpiece 1 is an insulating film (for example, a plasma TEOS film) on the semiconductor substrate.
When the polishing liquid is supplied to the rotating polishing pad 5, the insulating film on the semiconductor substrate supported by the chuck 2 is brought into contact with the polishing pad 5 and the polishing load is applied to the rotating chuck 2 by the motor 3. Add arrow 43
When the polishing platen 4 is reciprocally moved relative to the polishing platen 4 in the radial direction, the surface of the insulating film undergoes a chemical reaction with the alkaline solution contained in the polishing liquid 6. While being carried out, mechanical polishing was carried out by the abrasive grains such as SiO 2 contained in the polishing liquid 6 to proceed with chemical / mechanical polishing processing, and fine irregularities were flattened to 0.01 μm or less. Thus, it is possible to obtain an interlayer insulating film having a desired film thickness with a variation in polishing amount of ± 5% or less. In the case of chemical / mechanical polishing for a metal film, the polishing liquid 6 may be colloidal silica obtained by adding SiO 2 abrasive grains to a solution containing alkali, or alumina or cerium oxide in a solution containing acid. Those containing abrasive grains are used.
【0014】そして化学的・機械的な研磨加工中にチャ
ック2と一緒に被加工物1が矢印43で示すごとく研磨
定磐4の半径方向に相対的に往復移動して荷重センサ7
が設置された箇所に到達して荷重センサ7に接触するこ
とになる。このように被加工物1が荷重センサ7と接触
した状態になると荷重センサ7から荷重が検出されて荷
重信号が信号線8を介してスリップリング9に入力され
る。スリップリング9から出力された荷重信号は、信号
線10を介して制御装置11に入力される。制御装置1
1は、荷重センサ7から検出された荷重の値を、キーボ
ード等の入力手段40によって入力された既知の値であ
る荷重センサ7の面積で除することにより、被加工物1
の面内の研磨圧力の分布P1ないしPnを算出する。求
めた研磨圧力の分布P1ないしPnが均一になるよう
に、流体13の圧力を流体制御弁14で制御したのち、
各領域1〜nに対応して設けられた流体供給管15によ
ってロータリージョイント16を介してチャック2に各
領域に対応させて設けられた流体供給口20に導入し、
流体13を被加工物1の裏面の各領域1〜nに供給す
る。なお、荷重センサ7が被加工物1の上を通過する間
に、制御装置11から信号線17を介してモータ3に停
止信号を送り、チャック2の回転を停止して被加工物
(ウエハ等の基板)1の面内の圧力を測定してもよい。
また41は、制御装置11に設けられたディスプレイ等
の表示手段であり、荷重センサ7から検出される荷重の
値、算出された研磨圧力の分布P1ないしPn、および
流体制御弁14で制御される各領域に対応した流体供給
口20への流体圧力等を表示するものである。この表示
手段41には、平均的な研磨圧力Paveに応じて算出
される研磨時間を表示したり、研磨の終点を表示するこ
ともできる。42は、制御装置11に設けられた記憶装
置であり、後述する各種データを記憶するものである。
制御用のプログラムを制御装置11内のメモリに記憶さ
せておく代わりに、記憶装置42に記憶させても良い。During the chemical / mechanical polishing process, the workpiece 1 together with the chuck 2 reciprocates in the radial direction of the polishing table 4 as indicated by an arrow 43, and the load sensor 7 is moved.
Will reach the place where is installed and will contact the load sensor 7. When the workpiece 1 comes into contact with the load sensor 7 in this way, the load is detected by the load sensor 7 and the load signal is input to the slip ring 9 via the signal line 8. The load signal output from the slip ring 9 is input to the control device 11 via the signal line 10. Control device 1
1 is the workpiece 1 obtained by dividing the value of the load detected by the load sensor 7 by the area of the load sensor 7 which is a known value input by the input means 40 such as a keyboard.
The in-plane polishing pressure distributions P1 to Pn are calculated. After controlling the pressure of the fluid 13 with the fluid control valve 14 so that the obtained distributions P1 to Pn of the polishing pressure become uniform,
The fluid supply pipes 15 provided corresponding to the respective regions 1 to n introduce the fluid into the chuck 2 via the rotary joint 16 to the fluid supply ports 20 provided corresponding to the respective regions,
The fluid 13 is supplied to each region 1 to n on the back surface of the workpiece 1. While the load sensor 7 passes over the workpiece 1, the control device 11 sends a stop signal to the motor 3 via the signal line 17 to stop the rotation of the chuck 2 to stop the workpiece (wafer or the like). The in-plane pressure of the substrate 1) may be measured.
Reference numeral 41 denotes display means such as a display provided in the control device 11, which is controlled by the load value detected by the load sensor 7, the calculated polishing pressure distributions P1 to Pn, and the fluid control valve 14. The fluid pressure to the fluid supply port 20 corresponding to each area is displayed. The display means 41 can display the polishing time calculated according to the average polishing pressure Pave, or can display the polishing end point. A storage device 42 is provided in the control device 11 and stores various data described later.
The control program may be stored in the storage device 42 instead of being stored in the memory in the control device 11.
【0015】次にチャック2による研磨圧力制御につい
て図2を用いて説明する。図2(a)はチャック2の断
面構造図であり、図2(b)はチャック2による研磨圧
力を制御する領域を説明するための平面図である。チャ
ック2において、18は研磨加工中に被加工物(ウエハ
等の基板)1がチャック2から外れることを防止する基
板押え、19は研磨加工中に被加工物(ウエハ等の基
板)1を支持する弾性体で形成された支持体、20は流
体供給口、21は流体排気口である。22は研磨圧力を
制御する2次元領域である円環帯状領域1、23は2次
元領域である円環帯状領域2、24は2次元領域である
円環帯状領域nを示す。なお、これらの領域は、円環で
なくても正多角形からなる帯状領域であってもよい。こ
れらの領域1ないし領域nは、実質的にほぼ同心状に配
置されている。圧力Ps1ないしPsnの流体が流体供
給口20に供給され、被加工物1の裏面に圧力P1ない
しPnの流体が供給される。研磨圧力を制御する領域と
領域との間には、それぞれ流体排気口21が設けられ
て、これにより流体供給口20によりそれぞれの領域に
供給された流体が他の領域に流入することを防止するこ
とができる。即ち、流体供給口20によってそれぞれの
領域に供給された流体は被加工物(ウエハ等の基板)1
の裏面に対して押圧して研磨圧力を付与すると共に、領
域の内周及び外周に設けられた流体排気口21から排気
されて流れることになる。なお、最外周には、流体排気
口21が形成されていなくても、流体供給口20によっ
て領域nに供給された流体は被加工物1の外周と基板押
え18との間の隙間から逃げて流すことができる。Next, the control of the polishing pressure by the chuck 2 will be described with reference to FIG. 2A is a sectional structural view of the chuck 2, and FIG. 2B is a plan view for explaining a region where the chuck 2 controls the polishing pressure. In the chuck 2, 18 is a substrate retainer for preventing the workpiece (substrate such as wafer) 1 from coming off the chuck 2 during polishing, and 19 supports the workpiece (substrate such as wafer) 1 during polishing. Is a support formed of an elastic body, 20 is a fluid supply port, and 21 is a fluid exhaust port. Reference numeral 22 denotes an annular belt-shaped area 1 which is a two-dimensional area for controlling the polishing pressure, 23 denotes an annular belt-shaped area 2 which is a two-dimensional area, and 24 denotes an annular belt-shaped area n which is a two-dimensional area. It should be noted that these regions may be band-shaped regions formed of regular polygons instead of being circular. These regions 1 to n are arranged substantially concentrically. The fluid having the pressures Ps1 to Psn is supplied to the fluid supply port 20, and the fluid having the pressures P1 to Pn is supplied to the back surface of the workpiece 1. A fluid exhaust port 21 is provided between the regions where the polishing pressure is controlled to prevent the fluid supplied to each region by the fluid supply port 20 from flowing into another region. be able to. That is, the fluid supplied to each region by the fluid supply port 20 is a workpiece (substrate such as wafer) 1
While being pressed against the back surface of No. 1 to give a polishing pressure, the fluid is exhausted from the fluid exhaust ports 21 provided at the inner and outer peripheries of the region and flows. Even if the fluid exhaust port 21 is not formed on the outermost periphery, the fluid supplied to the region n by the fluid supply port 20 escapes from the gap between the outer periphery of the workpiece 1 and the substrate retainer 18. Can be flushed.
【0016】図3は、被加工物1の支持部の断面拡大図
である。支持体19には各領域に対応させて流体供給口
20につながった穴26および環状の窪み25と流体排
気口21につながった環状の溝27とが設けられてお
り、流体供給口20から各領域に導入された供給圧力P
s1ないしPsnの流体は、穴26を通って被加工物1
の裏面と弾性体である支持体19のと間の環状の窪み2
5に供給され、各領域において被加工物(ウエハ等の基
板)1に対して押圧力P1ないしPnを付与して研磨圧
力P1’ないしPn’を得ると共に、被加工物(ウエハ
等の基板)1の裏面に供給された流体は、各領域に対応
して設けられた環状の窪み25の内周及び外周に形成さ
れた突出部28と被加工物1の裏面との間に形成される
極微小な間隙を通して環状の溝27内に流れ、流体排気
口21から排気されることになる。FIG. 3 is an enlarged cross-sectional view of the support portion of the work piece 1. The support 19 is provided with a hole 26 and an annular recess 25 connected to the fluid supply port 20 and an annular groove 27 connected to the fluid exhaust port 21 corresponding to each region. Supply pressure P introduced into the area
The fluid of s1 to Psn passes through the hole 26 and the workpiece 1
Annular recess 2 between the back surface of the base and the support 19 which is an elastic body
5, the pressing force P1 to Pn is applied to the workpiece (substrate such as wafer) 1 in each region to obtain the polishing pressure P1 ′ to Pn ′, and the workpiece (substrate such as wafer) The fluid supplied to the back surface of No. 1 is an extremely small amount formed between the back surface of the workpiece 1 and the projections 28 formed on the inner and outer circumferences of the annular recess 25 provided corresponding to each region. It flows through the small gap into the annular groove 27 and is exhausted from the fluid exhaust port 21.
【0017】ここで、流体供給口20の面積aは、次に
示す(数1)式により決められる値である。 a=πd2/4 ・・・(数1) 但し、dは流体供給口20の直径である。またオリフィ
スの流出速度係数φは、流体の断熱指数κから次に示す
(数2)から決められる値である。但し、gは重力加速
度である。Here, the area a of the fluid supply port 20 is a value determined by the following equation (1). a = πd 2/4 ··· (Equation 1) where, d is the diameter of the fluid supply port 20. Further, the outflow velocity coefficient φ of the orifice is a value determined from the adiabatic index κ of the fluid from the following (Equation 2). However, g is gravitational acceleration.
【0018】[0018]
【数2】 (Equation 2)
【0019】従って、被加工物(ウエハ等の基板)1の
裏面の各領域に供給された流体の圧力Po(P1ないし
Pnの各々)は、各領域に流体供給口20から供給され
る流体の供給圧力Ps(Ps1ないしPsnの各々)と
の間に次に示す(数3)式の関係を有する。Accordingly, the pressure Po (each of P1 to Pn) of the fluid supplied to each region on the back surface of the workpiece (substrate such as wafer) 1 is equal to that of the fluid supplied from the fluid supply port 20 to each region. The relationship between the supply pressure Ps (each of Ps1 to Psn) and the expression (3) shown below is established.
【0020】[0020]
【数3】 (Equation 3)
【0021】但し、Paは大気圧、μは流体の粘性係
数、γaは大気圧・常温における流体の比重量、Coは
オリフィスの流量係数、Rはガス定数、Toは流体の温
度、2Roは各領域の内周と外周とに設けられた流体排
気口21の間の距離、2Riは液体供給口20に接続さ
れた支持体19に形成された穴26の径、hは環状の窪
み25の最大深さである。これら各種データを入力手段
40に用いて入力して例えば記憶装置42に記憶させて
おくことにより、制御装置11は、上記(数3)式に基
づいて、流量制御弁14によって制御する各領域に流体
供給口20から供給される流体の供給圧力Ps(Ps1
ないしPsnの各々)を算出することができる。Where Pa is the atmospheric pressure, μ is the viscosity coefficient of the fluid, γa is the specific weight of the fluid at atmospheric pressure and room temperature, Co is the flow coefficient of the orifice, R is the gas constant, To is the temperature of the fluid, and 2Ro is each. The distance between the fluid exhaust ports 21 provided on the inner and outer circumferences of the region, 2Ri is the diameter of the hole 26 formed in the support 19 connected to the liquid supply port 20, and h is the maximum of the annular recess 25. Depth. By inputting these various types of data using the input means 40 and storing them in the storage device 42, for example, the control device 11 causes each region controlled by the flow rate control valve 14 to be based on the equation (3). Supply pressure Ps of the fluid supplied from the fluid supply port 20 (Ps1
To Psn) can be calculated.
【0022】上記(数3)式から明らかなように、各領
域に流体供給口20から供給される流体の供給圧力Ps
(Ps1ないしPsnの各々)が大きくなれば、被加工
物(ウエハ等の基板)1の裏面の各領域に供給された流
体の圧力Po(P1ないしPnの各々)も大きくなり、
上記各領域の流体の供給圧力Psの値を流量制御弁14
によって制御することにより、上記各領域に供給された
流体の圧力Po(被加工物1の各領域に付与される押付
け力)の値を制御することができる。弾性体19と被加
工物(ウエハ等の基板)1の間の各領域に供給された流
体の圧力は、図中に示すように同心円状の独立した圧力
P1ないしPnとなり、各領域に流体供給口20から供
給される流体の供給圧力の分布Ps1ないしPsnを流
量制御弁14によって制御することによって研磨圧力の
分布P1ないしPnを制御することができる。この場
合、研磨中に、弾性体19と被加工物1の間の各領域に
供給された流体の圧力P1ないしPnの値に応じた研磨
圧力が被加工物1の各領域に対して付与されることにな
る。As is clear from the equation (3), the supply pressure Ps of the fluid supplied from the fluid supply port 20 to each region.
As (Ps1 to Psn) increases, the pressure Po (P1 to Pn) of the fluid supplied to each region on the back surface of the workpiece (substrate such as wafer) 1 also increases,
The value of the supply pressure Ps of the fluid in each of the above regions is set to the flow control valve 14
The value of the pressure Po of the fluid supplied to each of the above regions (the pressing force applied to each region of the workpiece 1) can be controlled by controlling by the above. The pressure of the fluid supplied to each region between the elastic body 19 and the workpiece (substrate such as wafer) 1 becomes concentric and independent pressures P1 to Pn as shown in the figure, and the fluid is supplied to each region. By controlling the distribution Ps1 to Psn of the supply pressure of the fluid supplied from the port 20 by the flow rate control valve 14, the distributions P1 to Pn of the polishing pressure can be controlled. In this case, during polishing, a polishing pressure corresponding to the values of the pressures P1 to Pn of the fluid supplied to each region between the elastic body 19 and the workpiece 1 is applied to each region of the workpiece 1. Will be.
【0023】図4は、図1で示した荷重センサ7の詳細
図である。29は研磨パッド5の裏面に接触するように
取り付けられた、荷重センサ7の接触子である。研磨加
工中に被加工物(ウエハ(半導体基板)等の基板)1が
荷重センサ7の上を通過すると、研磨パッド5が変形し
て接触子29の位置が変位し、研磨圧力に応じた電圧信
号が信号線8を介して出力される。次に、研磨圧力の測
定方法と研磨圧力の制御方法を以下に述べる。図5は、
被加工物1(ウエハ)の面内における研磨圧力の分布の
説明図である。30は荷重センサ7の軌跡、31は研磨
圧力の分布である。化学的・機械的な研磨加工中に、荷
重センサ7の軌跡30が被加工物1の中心を通過する場
合の研磨圧力の分布を被加工物1の端部点Aから端部点
A’まで測定し、領域1ないし領域nにおいて測定され
た研磨圧力をそれぞれ研磨圧力P1’ないしPn’とす
る。次に、領域の数をnとしたとき、研磨圧力P1’な
いしPn’の平均値Paveは次に示す(数4)式の関
係から制御装置11において算出することができる。FIG. 4 is a detailed view of the load sensor 7 shown in FIG. Reference numeral 29 is a contact of the load sensor 7, which is attached so as to contact the back surface of the polishing pad 5. When the workpiece (substrate such as a wafer (semiconductor substrate)) 1 passes over the load sensor 7 during the polishing process, the polishing pad 5 is deformed and the position of the contact 29 is displaced, resulting in a voltage corresponding to the polishing pressure. The signal is output via the signal line 8. Next, a method for measuring the polishing pressure and a method for controlling the polishing pressure will be described below. FIG.
It is an explanatory view of distribution of polishing pressure in a field of work piece 1 (wafer). Reference numeral 30 is the locus of the load sensor 7, and 31 is the distribution of the polishing pressure. The distribution of the polishing pressure when the locus 30 of the load sensor 7 passes through the center of the workpiece 1 during the chemical / mechanical polishing process is measured from the end point A to the end point A ′ of the work piece 1. The polishing pressures measured and measured in the regions 1 to n are defined as polishing pressures P1 ′ to Pn ′, respectively. Next, assuming that the number of regions is n, the average value Pave of the polishing pressures P1 ′ to Pn ′ can be calculated by the control device 11 from the relationship of the following (Formula 4).
【0024】 Pave=(P1’+P2’+・・・+Pn’)/n・・・(数4) 制御装置11は、例えば、領域1において荷重センサ7
で測定された研磨圧力P1’が研磨圧力の測定値の平均
値Paveよりも小さい場合には、圧力制御弁14を調
節(制御)して、領域nに供給する流体の供給圧力Ps
1を増加させ、被加工物(ウエハ等の基板)1の裏面に
供給する流体の圧力P1を増加させたのち、再びP1’
とPaveを測定し、P1’とPaveとを比較してP
1’がPaveよりも小さい場合には、さらにPs1を
増加させ、P1’がPaveよりも大きい場合には、P
s1を減少させることにより、P1’とPaveが等し
くした。同様にして、制御装置11は、圧力制御弁14
を制御して各領域2ないしnに供給する流体の供給圧力
Ps2ないしPsnを制御して荷重センサ7で測定され
るP2’ないしPn’をPaveと等しくした。なお、
荷重センサ7で各領域1ないしnについて測定される研
磨圧力P1’ないしPn’と上記説明した被加工物(ウ
エハ等の基板)1の裏面の各領域1ないしnに供給され
た流体の圧力P1ないしPnとの間は比例関係にあるた
め、制御装置11は、荷重センサ7で各領域1ないしn
について測定される研磨圧力P1’ないしPn’から上
記(数3)式等に基づいて、圧力制御弁14で制御する
各領域1ないしnに供給する流体の供給圧力Ps1ない
しPsnを算出することができる。Pave = (P1 ′ + P2 ′ + ... + Pn ′) / n ... (Equation 4) The control device 11 controls the load sensor 7 in the area 1, for example.
When the polishing pressure P1 ′ measured in step S4 is smaller than the average value Pave of the measured values of the polishing pressure, the pressure control valve 14 is adjusted (controlled) to supply pressure Ps of the fluid supplied to the region n.
1 is increased to increase the pressure P1 of the fluid supplied to the back surface of the workpiece (substrate such as wafer) 1 and then P1 ′ is increased again.
And Pave are measured, P1 'and Pave are compared, and P
When 1 ′ is smaller than Pave, Ps1 is further increased, and when P1 ′ is larger than Pave, Ps1 is increased.
By reducing s1, P1 'and Pave were made equal. Similarly, the control device 11 controls the pressure control valve 14
Is controlled to control the supply pressures Ps2 to Psn of the fluid supplied to the respective regions 2 to n so that P2 ′ to Pn ′ measured by the load sensor 7 are equal to Pave. In addition,
The polishing pressures P1 ′ to Pn ′ measured by the load sensor 7 for the respective regions 1 to n and the pressure P1 of the fluid supplied to the respective regions 1 to n on the back surface of the workpiece (substrate such as wafer) 1 described above. Since there is a proportional relationship between the load sensor 7 and each of the regions 1 to n.
The supply pressures Ps1 to Psn of the fluid supplied to the respective regions 1 to n controlled by the pressure control valve 14 can be calculated from the polishing pressures P1 ′ to Pn ′ measured with respect to it can.
【0025】[0025]
【実施例】次に本発明に係る化学的・機械的な研磨加工
を半導体基板上に形成されたプラズマTEOS膜(1.
5μm堆積)からなる層間絶縁膜に適用した場合につい
て説明する。主な化学的・機械的な研磨加工条件は、研
磨圧力:30〜40kPa、研磨液6:アルカリ溶液か
らなるコロイダルシリカ(粒径約30nm)、研磨パッ
ド5:硬質発泡ポリウレタン系(硬度約60度)厚さ
0.95mm、半導体基板の支持体19には、チャック
表面に形成した厚さ約0.5mmのスウェードタイプの
弾性体を用いた。弾性体19に形成した穴26の直径は
2mm、流体供給口と流体排気口の直径は0.8mmと
した。次に示す(表1)は、層間絶縁膜に対する化学的
・機械的な研磨加工において、研磨圧力の制御なし(チ
ャックの支持体に半導体基板を固定した)の場合の比較
例と本発明に係る研磨圧力分布を制御する場合の実施例
とを研磨後の絶縁膜厚さと研磨量ばらつきとについて比
較したものである。EXAMPLES Next, a plasma TEOS film (1.
The case of application to an interlayer insulating film formed of 5 μm deposition) will be described. The main chemical / mechanical polishing conditions are: polishing pressure: 30-40 kPa, polishing liquid 6: colloidal silica made of an alkaline solution (particle size: about 30 nm), polishing pad 5: hard polyurethane foam (hardness: about 60 degrees). A suede type elastic body having a thickness of 0.95 mm and a thickness of about 0.5 mm formed on the surface of the chuck is used as the support 19 of the semiconductor substrate. The diameter of the hole 26 formed in the elastic body 19 was 2 mm, and the diameter of the fluid supply port and the fluid exhaust port was 0.8 mm. The following (Table 1) relates to the comparative example and the present invention in the case where the polishing pressure is not controlled (the semiconductor substrate is fixed to the support of the chuck) in the chemical / mechanical polishing process for the interlayer insulating film. FIG. 6 is a comparison between an example of controlling a polishing pressure distribution and an insulating film thickness after polishing and a variation in polishing amount.
【0026】[0026]
【表1】 [Table 1]
【0027】(表1)中、比較1ないし比較3は、研磨
圧力の制御なし(チャックの支持体に半導体基板を固定
した)の場合の比較例としての実験結果を示す。比較1
と3は、プラズマTEOS膜(1.5μm堆積)に対し
て残膜厚さが0.5μmまで化学的・機械的な研磨加工
を施したところ、研磨量のばらつきが±8%、±7%で
あったことを示す。比較2は、プラズマTEOS膜
(1.5μm堆積)に対して残膜厚さが0.45μmま
で化学的・機械的な研磨加工を施したところ、研磨量の
ばらつきが±12%であったことを示す。(表1)中、
実施1ないし3は、本発明に係る研磨圧力分布を制御す
る場合の実施例としての実験結果を示す。実施1は研磨
圧力分布の制御が不良で、プラズマTEOS膜(1.5
μm堆積)に対して残膜厚さが0.45μmまで化学的
・機械的な研磨加工を施したところ、研磨量のばらつき
が±6%であったことを示す。実施2と3は研磨圧力分
布の制御が良好で、プラズマTEOS膜(1.5μm堆
積)に対して残膜厚さが0.5μmまで化学的・機械的
な研磨加工を施したところ、研磨量のばらつきが±5%
以下の±2%、±3%であったことを示す。化学的・機
械的な研磨加工特性は、研磨後の絶縁膜の研磨量のばら
つきによって評価した。評価は光干渉式の薄膜厚さ計を
用いて半導体基板(ウエハ)面内49箇所の絶縁膜の厚
さを測定した。そして、絶縁膜の厚さの最大値をTma
x、最小値をTmin、平均値をTaveとしたとき、
膜厚ばらつきVを、次に示す(数5)から算出した。In Table 1, Comparative Examples 1 to 3 show experimental results as comparative examples when the polishing pressure is not controlled (the semiconductor substrate is fixed to the support of the chuck). Comparison 1
In Nos. 3 and 3, when the plasma TEOS film (1.5 μm deposited) was chemically and mechanically polished to a residual film thickness of 0.5 μm, the variation in polishing amount was ± 8%, ± 7%. It was shown that. In Comparative Example 2, when the plasma TEOS film (1.5 μm deposited) was chemically and mechanically polished to a residual film thickness of 0.45 μm, the variation in polishing amount was ± 12%. Indicates. (Table 1),
Examples 1 to 3 show experimental results as examples when controlling the polishing pressure distribution according to the present invention. In Example 1, the control of the polishing pressure distribution was poor, and the plasma TEOS film (1.5
When chemical / mechanical polishing is applied to the residual film thickness of 0.45 μm, the variation in polishing amount is ± 6%. In Examples 2 and 3, the polishing pressure distribution was well controlled, and the plasma TEOS film (1.5 μm deposition) was chemically and mechanically polished to a residual film thickness of 0.5 μm. Variation of ± 5%
It is shown that the following values were ± 2% and ± 3%. The chemical / mechanical polishing characteristics were evaluated by the variation in the polishing amount of the insulating film after polishing. For the evaluation, the thickness of the insulating film was measured at 49 points in the plane of the semiconductor substrate (wafer) using a light interference type thin film thickness meter. Then, the maximum value of the thickness of the insulating film is set to Tma
x, the minimum value is Tmin, and the average value is Tave,
The film thickness variation V was calculated from the following (Equation 5).
【0028】 V=±100(Tmax−Tmin)/2Tave (数5) これらの各実験結果を示す(表1)から分かるように、
比較例に比べて本発明の如く研磨圧力分布を制御するこ
とによって層間絶縁膜の膜厚さばらつきを低減できる効
果が得られたことを確認することができた。さらに、本
発明の如く研磨圧力分布を制御することによって研磨前
に絶縁膜の表面に存在した1μmの段差を、研磨後に
0.1μm以下にすることができた。この値は、この層
間絶縁膜上に0.25μm以下の配線幅を有する配線を
形成することを可能にする値である。 次に、本発明に
係る研磨圧力分布を制御して行う化学的・機械的な研磨
加工方法を適用して、6インチのシリコン基板上に2層
のアルミ配線構造を持つ半導体装置を製造した実施例に
ついて、図6を用いて説明する。V = ± 100 (Tmax-Tmin) / 2Tave (Equation 5) As can be seen from Table 1 showing the results of each of these experiments,
It was confirmed that the effect of reducing the variation in film thickness of the interlayer insulating film was obtained by controlling the polishing pressure distribution as in the present invention as compared with the comparative example. Further, by controlling the polishing pressure distribution as in the present invention, the step difference of 1 μm existing on the surface of the insulating film before polishing could be reduced to 0.1 μm or less after polishing. This value is a value that enables formation of a wiring having a wiring width of 0.25 μm or less on this interlayer insulating film. Next, a semiconductor device having a two-layer aluminum wiring structure on a 6-inch silicon substrate was manufactured by applying a chemical / mechanical polishing method of controlling the polishing pressure distribution according to the present invention. An example will be described with reference to FIG.
【0029】即ち、61は半導体基板(6インチのシリ
コン基板)上に半導体素子を形成した後に1層目のアル
ミ配線を形成する工程である。62は工程61で形成さ
れた1層目のアルミ配線上にプラズマTEOS膜(層間
絶縁膜)をCVDにより1.5μm程度の厚さに堆積
(成膜)する工程である。63は工程62で成膜された
例えば1.5μm厚さのプラズマTEOS膜の表面を、
前記本発明の実施の形態で説明したとおり、研磨圧力分
布を制御して化学的・機械的な研磨加工を行って表面を
平坦化する工程である。この工程63で1μm研磨加工
した結果、プラズマTEOS膜の厚さ分布を光干渉式の
薄膜厚さ測定器を用いて測定したところ、厚さが0.5
μm±0.02μm(膜厚さのばらつきが±4%)であ
ることを確認した。このとき、プラズマTEOS膜を堆
積した後にプラズマTEOS膜の表面に存在した1μm
の段差について、触針式の段差測定器による測定とウエ
ハの断面のSEM観察を行い、段差が1μmから0.1
μm以下に低減されたことを確認した。また、接触式の
表面粗さ測定器及び原子間力顕微鏡を用いて、研磨した
プラズマTEOS膜の表面粗さを測定し、プラズマTE
OS膜の表面粗さが0.2ないし0.3nmRmaxで
あることを確認した。That is, reference numeral 61 is a step of forming a first layer of aluminum wiring after forming a semiconductor element on a semiconductor substrate (6 inch silicon substrate). Step 62 is a step of depositing (depositing) a plasma TEOS film (interlayer insulating film) on the first-layer aluminum wiring formed in step 61 by CVD to a thickness of about 1.5 μm. 63 indicates the surface of the plasma TEOS film having a thickness of, for example, 1.5 μm formed in the step 62,
As described in the embodiment of the present invention, it is a step of controlling the polishing pressure distribution and performing chemical / mechanical polishing to planarize the surface. As a result of polishing processing by 1 μm in this step 63, the thickness distribution of the plasma TEOS film was measured using an optical interference type thin film thickness measuring device, and the thickness was 0.5.
It was confirmed that it was μm ± 0.02 μm (the variation of the film thickness was ± 4%). At this time, 1 μm existing on the surface of the plasma TEOS film after depositing the plasma TEOS film
The step difference is measured by a stylus type step measuring device and the cross section of the wafer is observed by SEM.
It was confirmed that the thickness was reduced to μm or less. In addition, the surface roughness of the polished plasma TEOS film was measured using a contact type surface roughness measuring device and an atomic force microscope, and plasma TEOS was measured.
It was confirmed that the surface roughness of the OS film was 0.2 to 0.3 nm Rmax.
【0030】64は研磨したプラズマTEOS膜の表面
に厚さ0.1μmのSiO2膜をCVDで堆積(成膜)
する工程である。65は工程64で表面が平坦化され、
所望の膜厚に研磨されたプラズマTEOS膜に対して下
層アルミ配線と電気的接続をとるためのコンタクトホー
ルをエッチングによって形成する工程である。66は工
程65で形成されたコンタクトホールにタングステン等
からなる導電体のコンタクトビアを形成する工程であ
る。67は工程64で成膜されたSiO2膜の表面に幅
0.25μmのアルミ上層配線を形成する工程である。
以上説明した工程61〜67によって6インチのシリコ
ン基板上に2層のアルミ配線構造を持つ半導体装置を製
造することができる。このように半導体装置を製造し、
コンタクトビア抵抗及び配線抵抗を測定した結果、コン
タクト抵抗不良及び配線不良がないことが分かり、信頼
性の高い半導体装置を製造することができた。Reference numeral 64 denotes a SiO 2 film having a thickness of 0.1 μm deposited on the surface of the polished plasma TEOS film by CVD (deposition).
This is the step of performing The surface of 65 is flattened in step 64,
This is a step of forming a contact hole for electrical connection with the lower aluminum wiring on the plasma TEOS film polished to a desired thickness by etching. Step 66 is a step of forming a contact via of a conductor made of tungsten or the like in the contact hole formed in the step 65. 67 is a step of forming aluminum upper layer wiring having a width of 0.25 μm on the surface of the SiO 2 film formed in step 64.
Through the steps 61 to 67 described above, a semiconductor device having a two-layer aluminum wiring structure on a 6-inch silicon substrate can be manufactured. The semiconductor device is manufactured in this way,
As a result of measuring the contact via resistance and the wiring resistance, it was found that there were no contact resistance defects and wiring defects, and a highly reliable semiconductor device could be manufactured.
【0031】次に本発明に係る研磨圧力分布を制御して
行う化学的・機械的な研磨加工方法を適用して、半導体
基板上に2層の配線構造を持つ半導体装置を製造した実
施例について、図7を用いて説明する。即ち、71は半
導体基板上に下層配線を形成する工程である。72は工
程71で形成された下層配線上に例えばプラズマTEO
S膜をCVDにより1.5μm程度の厚さに堆積(成
膜)する工程である。73は工程72で成膜された例え
ば1.5μm厚さのプラズマTEOS膜(層間絶縁膜)
の表面を、前記本発明の実施の形態で説明したとおり、
研磨圧力分布を制御して化学的・機械的な研磨加工を行
って表面を平坦化する工程である。この工程73で1μ
m研磨加工した結果、図6に示す実施例と同様に、厚さ
が0.5μm±0.02μm(膜厚さのばらつきが±4
%)で膜厚さのばらつきを±5%以下にして、段差(微
小凹凸)を0.1μm以下に低減させて平坦化すること
ができる。プラズマTEOS膜の表面粗さを0.2ない
し0.3nmRmaxにすることができる。Next, an example of manufacturing a semiconductor device having a two-layer wiring structure on a semiconductor substrate by applying the chemical / mechanical polishing method of controlling the polishing pressure distribution according to the present invention , FIG. 7 will be described. That is, 71 is a step of forming a lower layer wiring on the semiconductor substrate. 72 is, for example, plasma TEO on the lower layer wiring formed in step 71.
In this step, the S film is deposited (formed) by CVD to a thickness of about 1.5 μm. Reference numeral 73 denotes a plasma TEOS film (interlayer insulating film) having a thickness of, for example, 1.5 μm formed in step 72
The surface of, as described in the embodiment of the present invention,
This is a step of controlling the polishing pressure distribution and performing chemical / mechanical polishing to planarize the surface. 1μ in this step 73
As a result of the polishing process, the thickness is 0.5 μm ± 0.02 μm (the variation in the film thickness is ± 4, as in the embodiment shown in FIG. 6).
%), The unevenness of the film thickness can be controlled to ± 5% or less, and the level difference (fine irregularities) can be reduced to 0.1 μm or less for planarization. The surface roughness of the plasma TEOS film can be 0.2 to 0.3 nm Rmax.
【0032】74は工程73で表面が平坦化され、所望
の膜厚に研磨されたプラズマTEOS膜に対して下層配
線と電気的接続をとるためのコンタクトホールをエッチ
ングによって形成する工程である。75は工程74で形
成されたコンタクトホールに対して選択CVDによりタ
ングステン等からなる導電体のコンタクトスタッドを形
成する工程である。76は工程63と同様に研磨圧力分
布を制御して化学的・機械的な研磨加工を行って表面に
成長したタングステン等の金属膜を除去する工程であ
る。77はプラズマTEOS膜(層間絶縁膜)の表面に
上層配線を形成する工程である。以上説明した工程71
〜77によって半導体基板上に多層配線構造を持つ半導
体装置を製造することができる。このように半導体装置
を製造し、コンタクトスタッド抵抗及び配線抵抗を測定
した結果、コンタクト抵抗不良及び配線不良がないこと
が分かり、信頼性の高い半導体装置を製造することがで
きる。Step 74 is a step in which a contact hole for electrically connecting to the lower layer wiring is formed by etching in the plasma TEOS film whose surface is flattened in step 73 and which is polished to a desired thickness. Step 75 is a step of forming a contact stud made of a conductor such as tungsten by selective CVD with respect to the contact hole formed in step 74. Similarly to step 63, step 76 is a step of controlling the polishing pressure distribution and performing chemical / mechanical polishing to remove the metal film such as tungsten grown on the surface. Reference numeral 77 is a step of forming an upper wiring on the surface of the plasma TEOS film (interlayer insulating film). Step 71 described above
Through 77, it is possible to manufacture a semiconductor device having a multilayer wiring structure on a semiconductor substrate. As a result of manufacturing the semiconductor device and measuring the contact stud resistance and the wiring resistance as described above, it is found that there is no contact resistance defect or wiring defect, and a highly reliable semiconductor device can be manufactured.
【0033】また本発明は、薄膜多層配線基板を製造す
るのに適用することができる。The present invention can also be applied to manufacture a thin film multilayer wiring board.
【0034】[0034]
【発明の効果】本発明によれば、化学的・機械的な研磨
加工において、研磨中に基板面内の研磨圧力の分布を制
御して、絶縁膜や金属膜などの厚さを均一に、しかも平
坦に(例えば膜厚さのばらつきを±5%以下で、しかも
微小凹凸を0.2μm以下)加工できるため、例えば半
導体装置の高信頼化及び高集積化を図ることができる効
果を奏する。According to the present invention, in the chemical / mechanical polishing process, the distribution of the polishing pressure in the surface of the substrate is controlled during polishing to make the thickness of the insulating film, the metal film, etc. uniform. Moreover, since it can be processed flatly (for example, the variation of the film thickness is ± 5% or less and the fine unevenness is 0.2 μm or less), the semiconductor device can be highly reliable and highly integrated.
【図1】本発明に係る化学的・機械的な研磨加工装置の
一実施の形態を示す概念図である。FIG. 1 is a conceptual diagram showing an embodiment of a chemical / mechanical polishing apparatus according to the present invention.
【図2】図1に示す被加工物を支持するチャック部の説
明図であリ、(a)はチャックの断面を示す構造図、
(b)はチャックによる研磨圧力を制御する領域を説明
するための平面図である。FIG. 2 is an explanatory view of a chuck portion supporting the workpiece shown in FIG. 1, (a) is a structural view showing a cross section of the chuck,
(B) is a plan view for explaining a region for controlling the polishing pressure by the chuck.
【図3】図2に示す被加工物の支持するチャック部の拡
大断面図である。FIG. 3 is an enlarged cross-sectional view of a chuck portion that supports the workpiece shown in FIG.
【図4】本発明に係る研磨定盤上に設置された研磨圧力
を検出する荷重センサを示す断面図である。FIG. 4 is a cross-sectional view showing a load sensor installed on a polishing platen for detecting a polishing pressure according to the present invention.
【図5】本発明に係る荷重センサで研磨圧力分布を測定
する方法を説明するための図である。FIG. 5 is a diagram for explaining a method of measuring a polishing pressure distribution with a load sensor according to the present invention.
【図6】本発明に係る半導体装置を製造するための一実
施例である工程フローを示す図である。FIG. 6 is a diagram showing a process flow which is one embodiment for manufacturing a semiconductor device according to the present invention.
【図7】本発明に係る半導体装置を製造するための他の
一実施例である工程フローを示す図である。FIG. 7 is a diagram showing a process flow of another embodiment for manufacturing a semiconductor device according to the present invention.
1…被加工物(ウエハ等の基板)、2…チャック、3…
モータ、4…研磨定盤 5…研磨パッド、6…研磨液、7…荷重センサ、9…ス
リップリング 11…制御装置、13…流体、14…圧力制御弁、15
…流体供給管 16…ロータリージョイント、18…ウエハ押え、19
…支持体(弾性体) 20…流体供給口、21…流体排気口、22…領域1、
23…領域2 24…領域n、25…環状の窪み、27…環状の溝、2
9…接触子 30…荷重センサの軌跡、31…研磨圧力の分布、40
…入力手段 41…表示手段、42…記憶装置1 ... Workpiece (substrate such as wafer), 2 ... Chuck, 3 ...
Motor, 4 ... Polishing surface plate 5 ... Polishing pad, 6 ... Polishing liquid, 7 ... Load sensor, 9 ... Slip ring 11 ... Control device, 13 ... Fluid, 14 ... Pressure control valve, 15
... Fluid supply pipe 16 ... Rotary joint, 18 ... Wafer holder, 19
... Support (elastic body) 20 ... Fluid supply port, 21 ... Fluid exhaust port, 22 ... Region 1,
23 ... Region 2 24 ... Region n, 25 ... Annular recess, 27 ... Annular groove, 2
9 ... Contactor 30 ... Load sensor locus, 31 ... Polishing pressure distribution, 40
Input means 41 Display means 42 Storage device
Claims (14)
る研磨圧力を制御して上記基板面に対して化学的・機械
的な研磨加工を行うことを特徴とする化学的・機械的な
研磨加工方法。1. A chemical / mechanical polishing method in which a polishing pressure in each of a plurality of two-dimensional regions in a substrate surface is controlled to perform a chemical / mechanical polishing process on the substrate surface. Polishing method.
る研磨圧力の分布をインプロセスで測定し、この測定さ
れた2次元領域の各々における研磨圧力の分布に応じて
2次元領域の各々における研磨圧力を制御して上記基板
面の化学的・機械的な研磨加工を行うことを特徴とする
化学的・機械的な研磨加工方法。2. A polishing pressure distribution in each of a plurality of two-dimensional regions on a substrate surface is measured by in-process, and each of the two-dimensional regions is measured according to the measured distribution of polishing pressure in each of the two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform the chemical / mechanical polishing processing of the substrate surface.
る研磨圧力を制御して上記基板上の絶縁膜表面の化学的
・機械的な研磨加工を行うことを特徴とする化学的・機
械的な研磨加工方法。3. A chemical / mechanical device characterized in that the polishing pressure in each of a plurality of two-dimensional regions within a substrate surface is controlled to perform chemical / mechanical polishing of the surface of an insulating film on the substrate. Polishing method.
る研磨圧力の分布をインプロセスで測定し、この測定さ
れた2次元領域の各々における研磨圧力の分布に応じて
2次元領域の各々における研磨圧力を制御して上記基板
上の絶縁膜表面の化学的・機械的な研磨加工を行うこと
を特徴とする化学的・機械的な研磨加工方法。4. A polishing pressure distribution in each of a plurality of two-dimensional regions on a surface of a substrate is measured by in-process, and each of the two-dimensional regions is measured according to the measured distribution of polishing pressure in each of the two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform the chemical / mechanical polishing of the surface of the insulating film on the substrate.
る研磨圧力を制御して上記基板上の金属膜表面の化学的
・機械的な研磨加工を行うことを特徴とする化学的・機
械的な研磨加工方法。5. A chemical / mechanical device, characterized in that a polishing pressure in each of a plurality of two-dimensional regions in a substrate surface is controlled to perform a chemical / mechanical polishing process on a surface of a metal film on the substrate. Polishing method.
る研磨圧力の分布をインプロセスで測定し、この測定さ
れた2次元領域の各々における研磨圧力の分布に応じて
2次元領域の各々における研磨圧力を制御して上記基板
上の金属膜表面の化学的・機械的な研磨加工を行うこと
を特徴とする化学的・機械的な研磨加工方法。6. A polishing pressure distribution in each of a plurality of two-dimensional regions on a substrate surface is measured by in-process, and each of the two-dimensional regions is measured according to the measured polishing pressure distribution in each of the two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform chemical / mechanical polishing of the surface of the metal film on the substrate.
る研磨圧力を制御して上記基板上の絶縁膜表面の研磨量
ばらつきを±5%以下で、該絶縁膜表面の凹凸を0.2
μm以下で化学的・機械的な研磨加工を行うことを特徴
とする化学的・機械的な研磨加工方法。7. A polishing pressure in each of a plurality of two-dimensional regions within a substrate surface is controlled so that variation in polishing amount on the surface of the insulating film on the substrate is ± 5% or less, and unevenness on the surface of the insulating film is reduced to 0. Two
A chemical / mechanical polishing method characterized by performing a chemical / mechanical polishing process with a size of μm or less.
る研磨圧力の分布をインプロセスで測定し、この測定さ
れた2次元領域の各々における研磨圧力の分布に応じて
2次元領域の各々における研磨圧力を制御して上記基板
上の絶縁膜表面の研磨量ばらつきを±5%以下で、該絶
縁膜表面の凹凸を0.2μm以下で化学的・機械的な研
磨加工を行うことを特徴とする化学的・機械的な研磨加
工方法。8. A polishing pressure distribution in each of a plurality of two-dimensional regions in a substrate surface is measured by in-process, and each of the two-dimensional regions is measured according to the measured polishing pressure distribution in each of the two-dimensional regions. The polishing pressure is controlled to control the polishing amount variation of the insulating film surface on the substrate to be ± 5% or less, and the unevenness of the insulating film surface to be 0.2 μm or less for chemical / mechanical polishing. Chemical and mechanical polishing processing method.
であることを特徴とする請求項1又は2又は3又は4又
は5又は6又は7又は8記載の化学的・機械的な研磨加
工方法。9. The chemical / mechanical structure according to claim 1, wherein the two-dimensional region is a substantially concentric region. Polishing method.
する層間絶縁膜形成工程と、 該層間絶縁膜形成工程で形成された層間絶縁膜上の複数
の2次元領域の各々における研磨圧力を制御して上記層
間絶縁膜表面の化学的・機械的な研磨加工を行って平坦
化する化学的・機械的な研磨加工工程と、 該化学的・機械的な研磨加工工程で平坦された上記層間
絶縁膜上に所望の上層配線を形成する上層配線形成工程
とを有することを特徴とする半導体基板の製造方法。10. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. Controlling the surface of the interlayer insulating film to perform a chemical / mechanical polishing process to planarize the surface, and a chemical / mechanical polishing process for planarizing the surface. And a step of forming a desired upper layer wiring on the interlayer insulating film, the method of manufacturing a semiconductor substrate.
する層間絶縁膜形成工程と、 該層間絶縁膜形成工程で形成された層間絶縁膜上の複数
の2次元領域の各々における研磨圧力を制御して上記層
間絶縁膜表面に対して化学的・機械的な研磨加工を行っ
て平坦化する化学的・機械的な研磨加工工程と、 該化学的・機械的な研磨加工工程で平坦化された層間絶
縁膜に対してコンタクトホールを形成するコンタクトホ
ール形成工程と、 該コンタクトホール形成工程で形成されたコンタクトホ
ールに導電材を埋め込んでコンタクトスタッドを形成す
るコンタクトスタッド形成工程と、 該コンタクトスタッド形成工程の後、上記層間絶縁膜上
に所望の上層配線を形成する上層配線形成工程とを有す
ることを特徴とする半導体基板の製造方法。11. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. Of the above-mentioned interlayer insulating film by performing a chemical / mechanical polishing process on the surface of the interlayer insulating film to planarize it, and a planarizing process on the chemical / mechanical polishing process. A contact hole forming step of forming a contact hole in the formed interlayer insulating film, a contact stud forming step of forming a contact stud by burying a conductive material in the contact hole formed in the contact hole forming step, and the contact stud After the forming step, an upper layer wiring forming step of forming a desired upper layer wiring on the interlayer insulating film is provided.
する層間絶縁膜形成工程と、 該層間絶縁膜形成工程で形成された層間絶縁膜上の複数
の2次元領域の各々における研磨圧力を制御して上記層
間絶縁膜表面の化学的・機械的な研磨加工を行う化学的
・機械的な研磨加工工程と、 該化学的・機械的な研磨加工工程で平坦された上記層間
絶縁膜上にSiO2膜をCVDによって形成するSiO2
膜形成工程と、 該SiO2膜形成工程で形成されたSiO2膜上に上層配
線を形成する上層配線形成工程とを有することを特徴と
する半導体基板の製造方法。12. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. A chemical / mechanical polishing process for controlling the surface of the interlayer insulating film by chemical / mechanical polishing, and the interlayer insulating film flattened by the chemical / mechanical polishing process. SiO 2 film is formed by CVD on SiO 2
A film forming step, the manufacturing method of a semiconductor substrate and having an upper layer wiring forming step of forming an upper layer wiring on the SiO 2 film forming step SiO 2 film formed by.
して上記基板面内の複数の2次元領域の各々における研
磨圧力を制御する制御手段を備え、上記基板の表面を平
坦に化学的・機械的な研磨加工を施すように構成したこ
とを特徴とする化学的・機械的な研磨加工装置。13. A control means for controlling a fluid pressure applied from the back surface of the substrate to control a polishing pressure in each of a plurality of two-dimensional regions in the surface of the substrate, the surface of the substrate being chemically and flattened. A chemical / mechanical polishing device characterized by being configured to perform mechanical polishing.
々における研磨圧力の分布をインプロセスで測定する測
定手段と、該測定手段で測定された2次元領域の各々に
おける研磨圧力の分布に応じて上記基板の裏面から付与
する流体圧力を制御して上記2次元領域の各々における
研磨圧力を制御する制御手段とを備え、上記基板の表面
を化学的・機械的な研磨加工を施すように構成したこと
を特徴とする化学的・機械的な研磨加工装置。14. A measuring means for measuring in-process the distribution of polishing pressure in each of a plurality of two-dimensional areas on a substrate surface, and a polishing pressure distribution in each of the two-dimensional areas measured by the measuring means. And a control means for controlling the fluid pressure applied from the back surface of the substrate to control the polishing pressure in each of the two-dimensional regions, and to chemically and mechanically polish the surface of the substrate. A chemical / mechanical polishing machine characterized by the above.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31019195A JP3345536B2 (en) | 1995-11-29 | 1995-11-29 | Chemical / mechanical polishing method and apparatus, and method of manufacturing semiconductor substrate |
PCT/JP1996/003502 WO1997020343A1 (en) | 1995-11-29 | 1996-11-29 | Semiconductor device manufacturing method, chemical-mechanical polishing method, and device used for the polishing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31019195A JP3345536B2 (en) | 1995-11-29 | 1995-11-29 | Chemical / mechanical polishing method and apparatus, and method of manufacturing semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09148284A true JPH09148284A (en) | 1997-06-06 |
JP3345536B2 JP3345536B2 (en) | 2002-11-18 |
Family
ID=18002275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31019195A Expired - Fee Related JP3345536B2 (en) | 1995-11-29 | 1995-11-29 | Chemical / mechanical polishing method and apparatus, and method of manufacturing semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3345536B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1066925A2 (en) * | 1999-07-09 | 2001-01-10 | Applied Materials, Inc. | Closed loop control of wafer polishing in a chemical mechanical polishing system |
JP2001334454A (en) * | 2000-05-29 | 2001-12-04 | Shin Etsu Handotai Co Ltd | Work polishing method, work holding plate and work polishing device |
US7097534B1 (en) | 2000-07-10 | 2006-08-29 | Applied Materials, Inc. | Closed-loop control of a chemical mechanical polisher |
CN102756323A (en) * | 2011-04-27 | 2012-10-31 | 中国科学院微电子研究所 | Chemical mechanical polishing equipment and chemical mechanical polishing method |
-
1995
- 1995-11-29 JP JP31019195A patent/JP3345536B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1066925A2 (en) * | 1999-07-09 | 2001-01-10 | Applied Materials, Inc. | Closed loop control of wafer polishing in a chemical mechanical polishing system |
EP1066925A3 (en) * | 1999-07-09 | 2003-09-17 | Applied Materials, Inc. | Closed loop control of wafer polishing in a chemical mechanical polishing system |
JP2001334454A (en) * | 2000-05-29 | 2001-12-04 | Shin Etsu Handotai Co Ltd | Work polishing method, work holding plate and work polishing device |
US7097534B1 (en) | 2000-07-10 | 2006-08-29 | Applied Materials, Inc. | Closed-loop control of a chemical mechanical polisher |
CN102756323A (en) * | 2011-04-27 | 2012-10-31 | 中国科学院微电子研究所 | Chemical mechanical polishing equipment and chemical mechanical polishing method |
Also Published As
Publication number | Publication date |
---|---|
JP3345536B2 (en) | 2002-11-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11552041B2 (en) | Chemical mechanical polishing for hybrid bonding | |
US5558563A (en) | Method and apparatus for uniform polishing of a substrate | |
US6837774B2 (en) | Linear chemical mechanical polishing apparatus equipped with programmable pneumatic support platen and method of using | |
US20070037486A1 (en) | Polishing pad, method of manufacturing the polishing pad, and chemical mechanical polishing apparatus comprising the polishing pad | |
JPH0513389A (en) | Polishing device | |
US6245193B1 (en) | Chemical mechanical polishing apparatus improved substrate carrier head and method of use | |
JPH0997772A (en) | Polishing pad, polishing device and method | |
US6722949B2 (en) | Ventilated platen/polishing pad assembly for chemcial mechanical polishing and method of using | |
WO2020185463A1 (en) | Chemical mechanical polishing using time share control | |
JP2870537B1 (en) | Polishing apparatus and method for manufacturing semiconductor device using the same | |
US6340434B1 (en) | Method and apparatus for chemical-mechanical polishing | |
JP3345536B2 (en) | Chemical / mechanical polishing method and apparatus, and method of manufacturing semiconductor substrate | |
JPH1158218A (en) | Abrasive pad and polishing device | |
KR20010071353A (en) | Dual cmp pad conditioner | |
JPH09167745A (en) | Method and device for chemical/mechanical polishing and manufacture of semiconductor substrate | |
US6686284B2 (en) | Chemical mechanical polisher equipped with chilled retaining ring and method of using | |
JP3575944B2 (en) | Polishing method, polishing apparatus, and method of manufacturing semiconductor integrated circuit device | |
US11772228B2 (en) | Chemical mechanical polishing apparatus including a multi-zone platen | |
JP3610676B2 (en) | Chemical and mechanical polishing method and apparatus, and semiconductor device manufacturing method | |
US20220388117A1 (en) | Polishing pad surface cooling by compressed gas | |
JP2001219364A (en) | Abrasive pad, polishing method and method of manufacturing work piece by using abrasive pad | |
JPH097984A (en) | Manufacture of semiconductor device and polishing apparatus used therefore | |
JP2000153447A (en) | Chemical and mechanical polishing device | |
JP2002305201A (en) | Method of manufacturing semiconductor device | |
JPH0811049A (en) | Polishing device and polishing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070830 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080830 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080830 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090830 Year of fee payment: 7 |
|
LAPS | Cancellation because of no payment of annual fees |