JPH09130636A - Correction waveform generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a high-accuracy waveform for correction by dividing a correction waveform into plural blocks for each X clock with a clock as a reference, dividing it within one word and storing it as correction waveform data for the relevant block. SOLUTION: When a change amount D of data in a certain block is defined as D=(AX+B) while using a code F and positive integers A and B, a variable S of one bit showing the code F and the integers A and B are dividedly stored in the data of one word at the correspondent address of a memory 1. This information is stored in the memory 1 while being divided into the amount to be changed per clock without fail and the remainder. A 1st arithmetic circuit 2 calculates timing to add the remainder component and a 2nd arithmetic circuit 3 decides the quantity to be really added corresponding to the output result of the circuit 2. An integration circuit 4 successively integrates the output data from the circuit 3 synchronously with the clock. Since the waveform is linearly interpolated for each block by this corrected waveform generating circuit, the capacity of the memory required for waveform accuracy is reduced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a cathode ray tube (hereinafter,
The present invention relates to a correction waveform generating circuit used for correcting image focus, distortion, etc. in an image display device using a CRT.

[0002]

2. Description of the Related Art Conventionally, a display device using a CRT displays an image by repeatedly scanning an electron beam in the horizontal direction and moving the scanning line in the vertical direction. Generally, in these display devices, in order to correct the distortion of deflection, misconvergence, focus, etc., correction waveforms such as parabolic waves and sawtooth waves of horizontal and vertical periods are generated by an analog signal processing circuit for correction. It was

In recent years, display monitors for computers have been required to have particularly high definition, large screen, and flattened screen, and more accurate correction is required. Therefore, waveforms are written from a memory in which waveform data is written using an address counter. In many cases, a digital waveform generating circuit for reading out is used.

A conventional correction waveform generating circuit will be described below.

FIG. 8 is a block diagram showing a conventional horizontal synchronizing correction waveform generating circuit. 81 is a memory, 82 is a clock generating circuit for generating a clock synchronized with the horizontal synchronizing signal, and 83.
Is an address counter, 84 is D / A (digital / analog)
It is a conversion circuit.

Generally, the address counter 83 outputs an address signal corresponding to the horizontal scanning position of the display device to the memory 81 from the clock and the horizontal synchronizing signal. In many cases, a flyback pulse, a so-called flyback pulse, is used instead of the horizontal synchronizing signal. The memory 81 outputs correction waveform data written in advance for each address, and this output is converted into an analog value by the D / A conversion circuit 84 and output to the subsequent correction circuit.

[0007]

However, in the above-mentioned conventional circuit configuration, in order to improve the accuracy of correction, it is necessary to have waveform data at many circuit points, so that the memory which occupies most of the circuit cost is memorized. Had the problem of increasing the capacity.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a correction waveform generating circuit capable of significantly reducing the memory capacity required for the accuracy of the correction waveform.

[0009]

In order to achieve the above object, the correction waveform generating circuit of the present invention time-divides a desired correction waveform into a plurality of blocks for each X clock with a clock as a reference, and for each block. The waveform data of the first block is stored in one word of the memory as it is with respect to the sampled waveform data, and the waveform data of the subsequent blocks is the change amount D with respect to the waveform data of the immediately previous block.
= F (AX + B) (F is a code and a 1-bit variable,
A and B are 0 or a positive integer), the 1-bit variable indicating the code F and A and B
Is divided into one word of a memory and stored as correction waveform data of the block. With this configuration, in one block period of a waveform time-divided into a plurality of blocks every X clocks. , First
A is not output from the arithmetic circuit of (X-B) times, A
However, the pulse output B times (A + 1) is synchronized with the clock by the integrating circuit and sequentially added or subtracted, so that any change amount for each block indicated by (AX + B) The block period is linearly interpolated, and the accuracy of the output waveform can be maintained.

That is, for the correction waveform time-divided into a plurality of blocks, only the amount of change in each block is stored in the memory, and since the block is linearly interpolated only by hardware processing, the accuracy of the output waveform is improved. It is possible to significantly reduce the required memory capacity while maintaining the above. On the contrary, if the memory capacity is the same, the accuracy of the waveform is greatly improved as compared with the conventional correction waveform generating circuit.

Further, as a concrete configuration of the correction waveform generating circuit of the present invention, a memory storing the correction waveform data, an input B to which the output of the memory is connected, and an input X to which a constant X is input are provided. And a 1-bit input S to which the output of the memory is connected, and a first arithmetic circuit configured to generate the pulse P of B times substantially uniformly during the X clock period.
An input A to which an output of the memory is connected, and the first A
A second arithmetic circuit which has an input P to which the output of the arithmetic circuit is connected, outputs (A + P) when the input S is 0, and outputs-(A + P) when the input S is 1 An integrating circuit for sequentially integrating the input output of the second arithmetic circuit with the initial waveform data, the memory, the integrating circuit, and the first circuit.
And a control means for controlling the arithmetic circuit.

The first arithmetic circuit includes a register, a subtracter for subtracting an output of externally input data from an output of the register, and a gate circuit for outputting a constant X during a carry-down output period of the subtractor. And an adder that receives the output of the subtracter and the output of the gate circuit, an output of the adder, and a value obtained by halving the constant X by an external control signal to switch the register. And a selector for outputting to.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, in which 1 is a memory, 2 is a first arithmetic circuit, 3 is a second arithmetic circuit, 4 is an integrating circuit, and 5 is timing. A generation circuit, 6 is a D / A conversion circuit.

In this example, the memory 1 is 16 bytes,
A correction waveform having a horizontal period and 6-bit resolution is generated. The timing generation circuit 5 is a logic circuit for generating a first control signal, a second control signal, and an address signal of the memory 1 from the input horizontal synchronizing signal, clock and constant X. The first control signal is a waveform start pulse that controls the phase of the waveform, and is output as a pulse for one clock in the horizontal cycle. The second control signal is a block start pulse for controlling the block division of the waveform, and is a pulse having a one-clock width output every X clocks from the first control signal.

The address signal sequentially designates an address corresponding to a block for every X clock.
The specific address is designated only during the period when the control signal is output. For example, 40 clocks per horizontal cycle,
When the constant X is “7”, as shown in FIG. 2, one pulse of the first control signal is output in one horizontal cycle, and the second control signal is output every seven clocks from the first control signal. Is output to. The address signal in this example is incremented when the code F is output during the period in which the first control signal is output, and is incremented every time the second control signal is output in order from “0” thereafter. It is a thing. In addition,
The constant X is specified by a horizontal frequency from a CPU (central processing unit) not shown, but may be a fixed value that does not depend on the horizontal frequency.

A series of data of correction waveforms is written in the memory 1 from the CPU. Depending on the constant X,
Since the waveform is divided into blocks in units of X clocks as described above, the data to be written in the memory 1 is determined from the amount of change in the waveform data in each block period.

The amount of change D of data in a block is D = using a sign F and “0” or positive integers A and B.
1-bit variable S (+ is “0”, − is “1”) indicating the code F when F (AX + B) is set, and the integers A and B are 1 word of the corresponding address of the memory 1. The data is divided and stored in the data. In this example, 8 bits per word are S for bit 7, A for bits 6 to 4, and bits 3 to 0.
B is divided into

Specifically, a constant X indicating the block width is shown in FIG.
Is “7”, waveform data sampled for each block is 30, 3
The following shows the case of generating a waveform that changes in sequence such as 8, 40, 30, ....

In FIG. 3, since the amount of change in data in block 0 is "8", 8 = (1 × 7 + 1) and S =
0, A = 1, B = 1. That is, at address 0 of the memory 1, 1-bit data S, 3-bit data A,
4-bit data B is arranged in order (00010001),
That is, "11" is written in hexadecimal, and the address 1,
In address 2, write "02" and "93" in hexadecimal notation. The same applies to addresses 3 and later. The initial value "30" (hexadecimal "1E") of the waveform is written in the address F designated by the timing generation circuit 5 when outputting the first control signal.

FIG. 4 is a block diagram showing a specific structure of the integrating circuit 4 of FIG. 1, which is composed of an adder 41, a selector 42 and a register 43, and the first control signal is H.
During the period of (High), the initial value of the waveform output from the memory 1 is fetched, and then the data output from the second arithmetic circuit 3 is sequentially integrated and output to the D / A conversion circuit 6.

FIG. 5 is a block diagram showing a specific configuration of the first arithmetic circuit 2 of FIG. 1, which is composed of a subtractor 51, an adder 52, a gate circuit 53, a register 54 and a selector 55. The subtracter 51 subtracts the output of the data of the integer B output from the memory 1 with respect to the data stored in the register 54, and outputs it to the adder 52. When the subtraction result becomes a negative number, a subtraction signal is output from the subtractor 51, and during that period,
The adder 52 receives a constant X indicating the block width from the gate circuit 53.
Is entered. Further, the data in which the constant X is halved is taken into the register 54 via the selector 55 by the second control signal.

The above-mentioned configuration uses the DDA (digital differential analysis) method used in a graphic processing terminal or the like. The carry-down output signal of the subtractor 51, that is, the output P of the first arithmetic circuit 2 is B during the X clock period. Outputs the pulse of times almost evenly.

FIG. 6 is a diagram showing the output of the first arithmetic circuit 2 when X = 7, in which the H level period for B clocks is evenly output during the 7 clocks in the block.

The second arithmetic circuit 3 is a simple decoder circuit, which decodes the S, A and P data output from the memory 1 and outputs the decoded data to the integrating circuit 4. FIG. 7 shows the truth table. When S is "0", (A + P) is output,
When S is "1", it is the complement of (A + P), that is,-(A + P)
Is output and the result of addition by the integrating circuit 4 in the subsequent stage is
It is similar to the one obtained by subtracting (A + P).

In the waveform generating circuit configured as above, when the waveform data increases by "24" in a certain block having a block width of 10 clocks, 24 = (2 × 10 + 4)
Therefore, by storing S = 0, A = 2, B = 4 in the memory 1, normally, the integrating circuit 4 integrates “2” for each clock, but at the timing of four times in the middle, The output P of the first arithmetic circuit 2 controls the second arithmetic circuit 3, and "3" is integrated.

That is, for the correction waveform divided into a plurality of blocks, when the number of clocks per block is X, the amount of data change during the block period is (the maximum value of A + 1).
If it is within × X, the inside of the block is automatically linearly interpolated by hardware.

According to this example, one block of the waveform divided into blocks with only 1 byte of data is linearly interpolated, so that the memory capacity can be significantly reduced while maintaining the accuracy of the waveform. Further, the accuracy of the waveform is greatly improved as compared with the conventional correction waveform generating circuit having the same memory capacity. Also, since interpolation is performed by simple logic,
It is also effective for high-speed waveform generation.

Further, for example, 100 to 200 per horizontal cycle
In the case of a clock, when a horizontal dynamic focus waveform is generated, a 16-byte memory capable of dividing the waveform into a maximum of 15 blocks is used as the memory 1, and the waveform resolution is set to 6 bits. Although it is possible to realize more accurate correction than the conventional analog waveform generation method, the waveform resolution is
A wider range of waveforms can be generated by allocating data to the memory 1 and changing the resolution of the output waveform. Needless to say, this can also be used for waveform generation in the vertical cycle.

As described above, according to the configuration of this embodiment,
For a waveform that is time-divided into a plurality of blocks, the amount of change in each block is divided into an amount that always changes per clock and its remainder, the result is stored in the memory 1, and the timing for adding the remainder is calculated. Second operation circuit 2 and a second operation circuit 2 which determines the amount to be actually added based on the output result of the first operation circuit 2.
Of the waveform by linearly interpolating the waveform for each block by the correction waveform generating circuit having the arithmetic circuit 3 and the integrating circuit 4 that sequentially integrates the output data from the second arithmetic circuit 3 in synchronization with the clock. The capacity of the memory 1 required for accuracy can be significantly reduced.

[0031]

As described above, the correction waveform generating circuit of the present invention described in each claim can generate a highly accurate correction waveform with a small memory capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a corrected waveform generating circuit of the present invention.

FIG. 2 is a timing chart of the timing generation circuit in FIG.

FIG. 3 is a diagram showing a method of creating data in the memory in FIG.

FIG. 4 is a block diagram showing a specific configuration of an integrating circuit in FIG.

5 is a block diagram showing a specific configuration of a first arithmetic circuit in FIG.

6 is a timing chart showing the operation of the first arithmetic circuit in FIG.

FIG. 7 is a truth table of the second arithmetic circuit in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional correction waveform generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory, 2 ... 1st arithmetic circuit, 3 ... 2nd arithmetic circuit, 4 ... Accumulation circuit, 5 ... Timing generation circuit, 6
... D / A conversion circuit, 41, 52 ... Adder, 42, 55 ... Selector, 43, 54 ... Register, 51 ... Subtractor, 53 ... Gate circuit.

Claims (3)

[Claims] 1. A desired correction waveform is time-divided into a plurality of blocks for each X clock based on a clock, and the waveform data of the first block is sampled for each block, and the waveform data of the first block is directly stored in the memory. The waveform data of the following block is stored in a word, and the amount of change D with respect to the waveform data of the immediately preceding block is D = F (AX + B) (F is a code and is a 1-bit variable, A and B are 0 or positive. 1-bit variable indicating the code F and A and B when expressed in the form of (an integer) are divided into one word of the memory and stored as correction waveform data of the block. A correction waveform generating circuit characterized by: 2. A memory storing correction waveform data, an input B to which an output of the memory is connected, and an input X to which a constant X is input, the pulse P being B times in an X clock period.
A first arithmetic circuit configured to generate substantially evenly, a 1-bit input S to which the output of the memory is connected, an input A to which the output of the memory is connected, and the first arithmetic circuit Has an input P connected to it, said input S being 0
Output (A + P) when the input S is 1
A second arithmetic circuit that outputs (A + P); an integrating circuit that sequentially integrates the input output of the second arithmetic circuit to initial waveform data; a memory, the integrating circuit, and the first arithmetic circuit. A correction waveform generating circuit comprising: a control unit for controlling. 3. The first arithmetic circuit, a register, a subtractor for subtracting an output of externally input data from an output of the register, and a gate circuit for outputting a constant X during a carry-down output period of the subtractor. An adder which receives the output of the subtracter and the output of the gate circuit as input, an output of the adder, and a value obtained by halving the constant X by an external control signal to switch the register. 3. The corrected waveform generating circuit according to claim 2, further comprising a selector for outputting to.