JPH0882808A - Production of liquid crystal display substrate - Google Patents

Abstract

PURPOSE: To make it possible to extremely easily repair disconnection or shorting with good reliability by executing connection to wiring layers of a conductive material on the peripheries of the notched parts of the wiring layers. CONSTITUTION: The point to be connected by using a connecting layer jr of a scanning signal line GL is removed by using, for example, a laser beam 60, by which the notched part 50 is formed in this scanning signal line GL when the scanning signal line GL is confined to be disconnected. A connecting layer jn is thereafter formed from the point of the notched part 50 of the one scanning signal line GL across the disconnected point to the point of the notched part 50 of the other scanning signal line GL. The connecting layer jn formed in such a manner is so formed as not to form the superposed part with the scanning signal line GL and to be connected to the scanning signal line GL at its side end face. Then, the disconnection is repaired with the extremely good reliability as compared to the case the superposed part of the connecting layer jn for the scanning signal line GL is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display substrate, for example, a method of manufacturing an active matrix type liquid crystal display substrate using thin film transistors and the like.

[0002]

2. Description of the Related Art For example, in an active matrix type liquid crystal display substrate, scanning signal lines extending in the column (horizontal) direction are arranged side by side in the row (vertical) direction and extend in the row (vertical) direction. The existing video signal lines are juxtaposed in the column (horizontal) direction.

Pixels having switching elements made of, for example, thin film transistors are formed in the respective regions surrounded by the scanning signal lines and the video signal lines.

Each switching element arranged in parallel in the same column direction is turned on by a voltage applied via an adjacent scanning signal line, and at this time, a signal voltage from the video signal line passes through the switching element. It is adapted to be applied to the corresponding pixel.

An active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-309921, "12.5 type active matrix type color liquid crystal display with redundant configuration", Nikkei. Electronics, pages 193-2
10, published December 15, 1986, published by Nikkei McGraw-Hill, Inc.

The liquid crystal display substrate having such a structure is
In recent years, there is a tendency for screens to become larger and smaller,
Along with this, the probability of disconnection of the scanning signal line or the video signal line in the manufacture increases.

Therefore, in manufacturing the liquid crystal display substrate,
Inspection is performed to determine whether or not the scan signal line and the video signal line are broken.

[0008]

However, when it is inspected as described above whether or not the scanning signal line and the video signal line are broken, and as a result, it is revealed that the disconnection occurs, The disconnection could not be repaired and the entire board was treated as a defective product.

The reason for this is that, first of all, it was not possible to repair the disconnection by a simple method. Further, even if the disconnection was repaired by some method, the reliability of the repaired part was poor. Furthermore, there is a problem in that the repaired portion adversely affects the liquid crystal and, for example, uneven brightness occurs in this portion.

Therefore, the present invention has been made under such circumstances, and an object of the present invention is to manufacture a liquid crystal display substrate capable of extremely easily and reliably repairing a disconnection or a short circuit. To provide a method.

Information on the technique for repairing the disconnection includes Information Display 11 /
91 p. 9-p. 11 "The color TFT
-LCD: if it's not perfect,
"fix it".

[0012] In this method, the protective film is laminated, and a connection hole is formed in the disconnection wiring of the completed substrate, and the connection wire is laminated so as to cover the portion.

In such a conventional technique, the correction rate depends on the film to be laminated and the film material of the ground, and in order to avoid it, the protective film must be corrected after laminating, and the number of steps is increased. I have a problem.

[0014]

In order to achieve such an object, the present invention comprises the following means.

Means 1. In a method for manufacturing a liquid crystal display substrate, which includes a step of inspecting a wiring layer formed on a liquid crystal side surface of at least one transparent substrate among transparent substrates arranged to face each other via a liquid crystal, the wiring layer is broken. The method further comprises a step of adhering a conductive material to a portion to repair the disconnection, and a step of previously forming a cutout by cutting out a portion of the wiring layer which is a superposed area of the conductive material,
The connection of the conductive material to the wiring layer is performed around the cutout portion of the wiring layer.

Means 2. In the structure according to the means 1, the cutout portion of the wiring layer in the overlapping region of the conductive material is a part of the overlapping region, whereby one of the outer portions of the conductive material formed with the disconnection point therebetween. The part is overlapped with the wiring layer.

Means 3. In the structure according to means 1 or 2, the method for manufacturing a liquid crystal display substrate is characterized in that the conductive material is deposited by a photo-CVD method.

Means 4. The connection angle defined by the connection side of the wiring layer and the long side direction of the conductive material is 60 ° or less, or 30
It is characterized in that it is not more than °.

[0019]

According to the structure of the means 1, when the conductive material is attached to the disconnection point of the wiring layer, the conductive material is not formed on the wiring layer in the vicinity of the notch formed in the wiring layer. The disconnection is repaired by connecting the conductive material.

It has been found that in such a case, the disconnection can be repaired with extremely high reliability as compared with the case where the conductive material overlaps the wiring layer.

When the disconnection is repaired by forming the overlapping portion of the conductive material on the wiring layer, the disconnection of the conductive material in the overlapping portion is often found after the passage of time thereafter. . Although the reason for this is not exactly known, it is considered that the heat required for forming the conductive material cannot be accumulated in the conductive material and is immediately conducted to the wiring layer.

According to the structure of the means 2, the effect of ensuring reliable connection with the conductive material around the notch formed in the wiring layer can be obtained.

This is because a part of the conductive material is formed so as to overlap the wiring layer, so that the conductive material adheres sufficiently in the periphery of the cutout.

In this case, the superposed portion is located on the outer side of the conductive material formed with the disconnection point in between, and the superposed portion is provided in the substantially effective connecting path portion of the conductive material which connects each wiring layer. Since the portion does not exist, the disconnection of the conductive material in the overlapping portion described above does not cause any particular problem.

According to the constitution of the means 3, the conductive material is changed to the optical CV.
The effect is great when it is formed by the D method.

That is, when the conductive material is formed to overlap the wiring layer, a relatively large number of wire breakages of the conductive material are likely to occur as compared with other methods, and when the means 1 or 2 is taken, the adverse effect is caused. Turned out to be almost empty.

According to the construction of the means 4, there is an effect that the disconnection correction rate is improved as compared with the connection angle of 90 °. Especially the connection angle is 30
If it is less than °, the disconnection correction rate becomes 80% or more, which is a practically sufficient level.

[0028]

The invention, further objects of the invention and further features of the invention will be apparent from the following description with reference to the drawings.

<< Active Matrix Liquid Crystal Display Device >>
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

<< Outline of Matrix Section >> FIG. 2 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device to which the present invention is applied, and FIG.
-3 is a view showing a section taken along a cutting line, and FIG.
It is sectional drawing in a cutting line.

As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And an adjacent two video signal lines (drain signal line or vertical signal line) DL are intersected with each other (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction. Video signal line DL
Extend in the up-down direction and are arranged in the left-right direction.

As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and a color filter FIL and a light-shielding film are provided on the upper transparent glass substrate SUB2 side. A black matrix pattern BM is formed. Silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2.

On the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

<< Outline of Matrix Periphery >> FIG. 5 is a plan view of a main part around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2, and FIG. 7 is a diagram showing an enlarged plane near the seal portion SL corresponding to the upper left corner of the panel in FIGS. 5 and 6. Further, FIG. 8 is a diagram showing a cross section taken along a cutting line 8a-8a in FIG. 7 on the left side and a cross section near the external connection terminal DTM to which the video signal drive circuit is to be connected on the right side with the cross section of FIG. 3 as the center. is there. Similarly, FIG. 9 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side and a cross section near the seal portion where there is no external connection terminal on the right side.

[0035] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared In each type of product, a standardized glass substrate is processed, and then the size is reduced to a size suitable for each product. In each case, the glass is cut after going through one step. 5 to 7 show an example of the latter case. In both of FIGS. 5 and 6, the upper and lower substrates SUB1 and SUB are shown.
2 shows the state after cutting, and FIG. 7 shows the state before cutting. LN is the edge of both substrates before cutting, and CT1 and CT2 are the substrate SU.
The positions where B1 and SUB2 should be cut are shown. In either case, in the completed state, the external connection terminal groups Tg, Td (subscripts omitted)
Are present (on the upper and lower sides and the left side in the figure), the size of the upper substrate SUB2 is such that the lower substrate SUB2 is exposed.
It is restricted to the inside of 1. The terminal groups Tg and Td are a tape carrier package TC in which a scanning circuit connection terminal GTM, a video signal circuit connection terminal DTM, and their lead-out wiring portions, which will be described later, are mounted on an integrated circuit chip CHI.
A plurality of Ps (FIGS. 18 and 19) are collectively named. The lead wiring from the matrix portion of each group to the external connection terminal portion is inclined toward both ends. This is due to the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP on the display panel PN.
This is for matching the L terminals DTM and GTM.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal sealing port INJ, the liquid crystal LC
A seal pattern SL is formed so as to seal the. The sealing material is made of epoxy resin, for example. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to at least one of the lead wirings INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.

The orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2, and the respective layers are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are lower transparent glass substrates SUB, respectively.
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is enclosed in a region partitioned by a seal pattern SL between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed on top of SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and the seal pattern SL is applied to the substrate SUB2.
Formed on the side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, the liquid crystal LC is injected from the opening INJ of the sealing material SL, and the injection port INJ is sealed with epoxy resin or the like to form the upper and lower substrates. It is assembled by cutting.

<< Thin Film Transistor TFT >> Next, referring to FIG.
Returning to FIG. 3, the configuration on the TFT substrate SUB1 side will be described in detail.

The thin film transistor TFT has a gate electrode G
When a positive bias is applied to T, the channel resistance between the source and the drain decreases, and when the bias is zero, the channel resistance increases.

A plurality of (two) thin film transistors TFT1 and TFT2 are redundantly provided in each pixel. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same), and has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic,
intrinsic, conductivity type determination impurities are not doped)
It has an i-type semiconductor layer AS made of amorphous silicon (Si), a pair of source electrodes SD1 and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

<< Gate Electrode GT >> The gate electrode GT is formed in a shape protruding in the vertical direction from the scanning signal line GL (branched into a T shape). The gate electrode GT projects so as to extend beyond the respective active regions of the thin film transistors TFT1 and TFT2. Thin film transistor TFT
The gate electrodes GT of the TFT 1 and the TFT 2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2. An aluminum (Al) film formed by sputtering, for example, is used as the second conductive film g2, and an Al anodic oxide film AOF is provided thereon.

The gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below), and is devised so that the i-type semiconductor layer AS is not exposed to outside light or backlight light. .

<< Scanning Signal Line GL >> The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Also, an Al anodic oxide film AOF is provided on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS in the thin film transistors TFT1 and TFT2 together with the gate electrode GT. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected and is formed to a thickness of 1200 to 2700Å (in this embodiment, about 2000Å). As shown in FIG. 7, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI is a scanning signal line G
It also contributes to the electrical insulation between L and the video signal line DL.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
In this example, each of the thin film transistors TFT1 and TFT2 is formed as an independent island, and is made of amorphous silicon and has a thickness of 200 to 2200Å (2 in this example.
The film thickness is about 000Å). The layer d0 is a phosphorus (P) -doped N (+)-type amorphous silicon semiconductor layer for ohmic contact, the i-type semiconductor layer AS exists on the lower side, and the conductive layer d2 (d3) exists on the upper side. It is left only where you do.

The i-type semiconductor layer AS is also provided between both the crossing portions (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor operates normally. You can leave it alone because it does. The transparent pixel electrode ITO1 is composed of the first conductive film d1.
Is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film), 1000-200
With a thickness of 0Å (in this embodiment, a film thickness of about 1400Å)
It is formed.

<< Source Electrode SD1, Drain Electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a second conductive film d2 in contact with the N (+) type semiconductor layer d0 and a third conductive film d3 formed thereon.

The second conductive film d2 is a chromium (Cr) film formed by sputtering, and is formed to a thickness of 500 to 1000 Å (in this embodiment, about 600 Å). If the Cr film is formed thicker, the stress increases.
It is formed within a range not exceeding the film thickness of 0Å. Cr film is N
It is used for the purpose of improving adhesion to the (+) type semiconductor layer d0 and preventing Al of the third conductive film d3 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). Second
As the conductive film d2, in addition to the Cr film, refractory metal (Mo, T
i, Ta, W) film, refractory metal silicide (MoS
An i ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The third conductive film d3 is formed by sputtering Al to a thickness of 3000 to 5000Å (400 in this embodiment).
0 Å) formed. The Al film has less stress than the Cr film and can be formed to have a large film thickness, and the source electrode SD1, the drain electrode SD2 and the video signal line DL can be formed.
Of the gate electrode GT and the i-type semiconductor layer AS are ensured (step coverage is improved).

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

<Video Signal Line DL> The video signal line DL is composed of a second conductive film d2 and a third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2.

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 7, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the common electrode of the upper substrate side SUB2. COM to the lower substrate SUB
Silver paste A on the lead wire INT for connecting the external connection terminal 1
The part connected by GP is also removed. Protective film PSV1
Regarding the thickness relationship between the gate insulating film GI and the gate insulating film GI, the former is made thicker in consideration of the protection effect, and the latter is made thin in the transconductance gm of the transistor. Therefore, as shown in FIG.
The protective film PSV1 having a high protective effect is formed so as to be larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, external light or backlight is exposed to the i-type semiconductor layer A.
A light shielding film BM is provided so as not to enter S. Figure 2
The closed polygonal contour line of the light-shielding film BM shown in (3) indicates an opening inside which the light-shielding film BM is not formed. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300Å.

Therefore, the thin film transistors TFT1 and TF
The i-type semiconductor layer AS of T2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT,
External natural light or backlight does not hit. The light-shielding film BM is formed in a lattice shape around each pixel (so-called black matrix), and the effective display area of one pixel is partitioned by this lattice. Therefore, the outline of each pixel is the light-shielding film BM.
Improves clarity and contrast. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Since the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (the lower right portion in FIG. 2) is also shielded by the light shielding film BM, even if a domain occurs in the above portion, the domain cannot be seen. The display characteristics do not deteriorate.

As shown in FIG. 6, the light-shielding film BM is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. 2 in which a plurality of dots-like openings are provided. There is. As shown in FIGS. 6 to 9, the light-shielding film BM in the peripheral portion is extended to the outside of the seal portion SL to prevent leak light such as reflected light caused by a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, the light-shielding film BM is retained inside about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe pattern by repeating red, green and blue at positions facing the pixels. The color filter FIL is formed to have a large size so as to cover all of the transparent pixel electrode ITO1, and the light shielding film BM overlaps with the edge portions of the color filter FIL and the transparent pixel electrode ITO1.
It is formed inside the peripheral portion of TO1.

The color filter FIL can be formed as follows. First, a dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

<< Protective Film PSV2 >> The protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this embodiment, the common voltage Vcom is the minimum level drive voltage Vdmin and the maximum level drive voltage V applied to the video signal line DL.
Although it is set to an intermediate DC potential with respect to dmax, an AC voltage may be applied if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half. For the planar shape of the common transparent pixel electrode ITO2, see FIGS. 6 and 7.

<< Structure of Storage Capacitance Element Cadd >> The transparent pixel electrode ITO1 is formed at the end opposite to the end connected to the thin film transistor TFT so as to overlap the adjacent scanning signal line GL. In this superposition, as is clear from FIG. 4, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd which is 1 is configured. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I and the anodic oxide film AOF.

The storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 is broken at the step portion of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 formed so as to cross the step.
The defect is compensated by the island region formed of the conductive film d3.

<< Gate Terminal Portion >> FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM. (A) is a plane and (B) is B of (A). -B shows a cross section taken along the line B. It should be noted that the figure corresponds to the lower part of FIG. 7, and the diagonal wiring portions are shown in a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. Anodized A
The oxide Al ₂ O ₃ film AOF is formed on the surface of the L layer g2, and the volume of the conductive portion therebelow is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect with the scanning line GL by a single straight line, but is bent in a crank shape and intersects.

In the figure, the AL layer g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this example, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM has a Cr layer g1 having a good adhesiveness to the silicon oxide SIO layer and a higher electric contact resistance than Al or the like.
Further, the surface thereof is protected and is composed of a transparent conductive layer d1 of the same level (same layer, simultaneously formed) as the pixel electrode ITO1.
In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end.
Are exposed from them to allow electrical contact with external circuitry. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically as shown in FIG. 7 to form the terminal group Tg (FIGS. 6 and 7). In the manufacturing process, the left end of the gate terminal is extended beyond the cutting region CT1 of the substrate to form the wiring SH.
shorted by g. Such a short-circuit line SHg in the manufacturing process is useful for supplying power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1.

<< Drain Terminal DTM >> FIG. 11 is a diagram showing the connection from the video signal line DL to the external connection terminal DTM thereof. (A) shows the plane thereof, and (B) shows B of (A).
-B shows a cross section taken along the line B. 7 corresponds to the vicinity of the upper right of FIG. 7, and although the orientation of the drawing is changed for convenience, the right end direction corresponds to the upper end (or lower end) of the substrate SUB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than the wiring portion so that a probe needle or the like can come into contact therewith. Similarly, the drain terminal D
The width of the TM is wider than that of the wiring portion so that the TM can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure, but the drain terminal DTM.
7 further extend beyond the cutting line CT1 of the substrate SUB1 to form a terminal group Td (subscripts omitted) as shown in FIG. 7, all of which are interconnected to each other to prevent electrostatic breakdown during the manufacturing process.
Shorted by Hd. The drain connection terminal is connected to the opposite side of the matrix of the video signal lines DL in which the inspection terminals TSTd are present, and conversely the inspection terminal is placed on the opposite side of the matrix of the video signal lines DL in which the drain connection terminals DTM are present. Are connected.

The drain connection terminal DTM has the Cr layer g1 and the ITO layer d1 for the same reason as the above-mentioned gate terminal GTM.
Is formed of two layers, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. The protective film PSV1 is, of course, removed on the terminal DTM to connect to an external circuit. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask, but the layer g2 is covered in the part not covered in this figure. This pattern is not directly relevant as it does not exist.

As shown in FIG. 8C, the lead wiring from the matrix portion to the drain terminal portion DTM is provided with the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal portion DTM. Although the layers d2 and d3 of the same level are laminated part way up to the middle of the seal pattern SL, this minimizes the probability of disconnection and facilitates electrical contact.
The purpose is to protect the l layer d3 as much as possible with the protective film PSV1 and the seal pattern SL.

<< Equivalent Circuit of Entire Display Device >> FIG. 12 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscript omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device for displaying information for a CRT (cathode ray tube) from a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source and a host (upper processing unit). It is a circuit including a circuit for exchanging information for use.

<< Function of Storage Capacitance Element Cadd >> The storage capacity element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and source electrode SD1, C
pix is a capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM), ΔV
lc represents a change amount of the pixel electrode potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. Further, the storage capacitor element Cadd also has the function of prolonging the discharge time, and thus the thin film transistor TFT
Accumulates video information for a long time after is turned off. The reduction of the direct current component applied to the liquid crystal LC improves the life of the liquid crystal LC,
It is possible to reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, so that the parasitic capacitance Cgs is increased. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, this demerit can be eliminated by providing the storage capacitor element Cadd.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

The first stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is the common transparent pixel electrode ITO2.
Set to the same potential as (Vcom). In the example of FIG. 7, the scanning signal line at the first stage is short-circuited to the common electrode COM through the terminal GT0, the lead wire INT, the terminal DT0 and the external wiring. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is the scanning signal line Ye in the last stage.
It may be connected to nd, connected to a DC potential point (AC ground point) other than Vcom, or connected to receive one extra scanning pulse Y ₀ from the vertical scanning circuit V.

<< Manufacturing Method >> Next, a manufacturing method of the substrate SUB1 side of the above-described liquid crystal display device will be described with reference to FIGS.
Will be described with reference to. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 3, and the right side shows the processing flow as seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage after the photo process is finished and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 After forming a silicon oxide film SIO on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg connecting the gate terminal GTM, the bus line SHd shorting the drain terminal DTM, and the anodized pad (not shown) connected to the anodized bus line SHg. To form.

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C, FIG. 13: After photographic processing (after forming the above-described anodic oxidation mask AO), 3
Substrate SUB1 is immersed in an anodizing solution consisting of a solution prepared by diluting 1% of tartaric acid with ammonia to pH 6.25 ± 0.05 with ethylene glycol solution, and the formation current density is 0.5 mA / cm. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized,
An anodic oxide film AOF having a film thickness of 1800Å is formed on scanning signal line GL, gate electrode GT and electrode PL1.

Step C ', FIG. 13 It is inspected whether or not the scanning signal line GL formed of the second conductive film g2 thus formed is normally connected and no disconnection occurs.

The inspection in this case is performed by bringing probes into contact with the gate terminal portions electrically connected to both ends of each scanning signal line GL and measuring the electrical resistance of the scanning signal line GL.

In this case, the repair when it is found that a disconnection has occurred in a part of the scanning signal line GL will be described with reference to FIGS. 21 (a) to 21 (c).

21 (a) and 21 (c) show a cross section of a portion along line 2-2 in FIG. 2, for example. This cross-section point is shown visually, for example, and its position information is obtained by some means. For example, the lower glass substrate SUB is placed on the XY stage arranged facing the microscope, and the position of the XY stage when a disconnection is found through the microscope corresponds to the position information. It can be done by This position information serves as information to be used in the later restoration.

21A, a platinum (Pt) layer is formed by irradiating a laser beam in a specific atmosphere on the broken portion of the scanning signal line GL shown in FIG. The disconnection is repaired by the connecting layer jn formed of the Pt layer.

FIG. 22 is a schematic block diagram showing an embodiment of an apparatus for repairing this disconnection.

In FIG. 1, there is a bell jar 2 having an XY stage 1 built-in, and a microscope / laser lens barrel 3 arranged facing the XY stage 1 is attached to the bell jar 2. There is. On the XY stage 1, a lower glass substrate SUB1 to be the target of disconnection inspection is arranged.

By driving the XY stage 1, the processed surface of the lower glass substrate SUB1 can be opposed to the microscope / laser barrel 3 over its entire area. The XY stage 1 is an XY stage controller 4
The drive is controlled by the input of the position information described above so that the disconnection point can face the microscope / laser barrel 3. In this case, it can be determined whether or not they are surely opposed to each other by using the microscope in the microscope / laser barrel 3.

The microscope / laser barrel 3 is adapted to guide the laser light from the laser source 5 and irradiate it to the broken portion of the scanning signal line GL. This laser light may be, for example, an Ar laser, a YLF laser, or a YAG laser. In the case of Ar laser, its wavelength is 0.55
In case of YLF laser, the wavelength is 1.05 μm, Y
In the case of an AG laser, its wavelength is 1.06 μm (second harmonic: 0.53 μm), and in each case, the power is about 200 mW, and the beam diameter is preferably 5 to 10 μm.

In the bell jar 2, as the material gas 7, (P
A mixed gas composed of tCl ₂ ) ₂ (CO) ₃ gas and Ar gas is supplied.

As a result, a chemical reaction occurs in the portion irradiated with the laser beam 6 to form a platinum (Pt) layer, which is a material for producing the same, and the Pt layer is used as the connecting layer jn to disconnect the scanning signal line. The GL will be rendered conductive.

As a pre-stage of forming the Pt layer, it is preferable to clean the region where the Pt layer is formed by performing so-called annealing with the laser beam 6. Also, when forming the Pt layer, a disconnection region is formed. By scanning the laser beam 6 from one side to the other side of the scanning signal line existing with the Pt in between, as shown in FIG.
It has been confirmed that the layer jn is easily formed.

Although the above description shows that the Pt layer is used for repair, the present invention is not limited to this, and Cr, Mo, W or the like may be used. In this case, the material gas 7 is Cr (CO) ₆
+ H ₂ etc., MoCl ₅ + H ₂ or Mo (CO) ₆ + Ar
Etc., WCl ₆ + H ₂ or WF ₆ + H ₂ is used.

FIG. 1 shows a more effective embodiment for repairing the disconnection of the scanning signal line GL.

First, in FIG. 10A, the scanning signal line G
It has been confirmed that L is disconnected. FIG. 11A is a sectional view taken along the line a′-a ′ of FIG.

Then, as shown in FIG. 10B, the portion of the scanning signal line GL which is to be connected using the coupling layer jn is removed by using, for example, the laser beam 60, whereby the scanning signal line GL is removed. A notch 50 is formed in the. The same figure (b ')
FIG. 4B is a sectional view taken along line b′-b ′ of FIG.

Thereafter, as shown in FIG. 7C, the connection extends from the cutout portion 50 of one scanning signal line GL to the cutout portion 50 of the other scanning signal line GL with the disconnection portion therebetween. Form the layer jn.

The connection layer jn in this case is formed through the same steps as shown in FIG. The coupling layer jn formed in this manner forms an overlapping portion with the scanning signal line GL, as shown in FIG. 1C, which is a sectional view taken along line c′-c ′ of FIG. Without scanning, the scanning signal line G
It is formed so as to be connected to L.

It is confirmed that such a structure can repair the disconnection extremely reliably as compared with the case where the overlapping portion of the coupling layer jn with respect to the scanning signal line GL is formed as shown in FIG. It is based on what was done.

When the disconnection is repaired by forming the overlapping portion of the coupling layer jn on the scanning signal line GL,
After the subsequent passage of time, the disconnection of the coupling layer jn in the overlapping portion was often found. Although the reason for this is not exactly known, it is considered that the heat required for forming the coupling layer jn cannot be accumulated in the scanning signal line GL and is immediately conducted to the scanning line signal line GL.

The same effect can be obtained by directly drawing In or the like by using a focused ion beam method without using the laser beam 7.

Step D, FIG. 14 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a 2000 Å-thickness Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to obtain the film thickness. After forming an i-type amorphous Si film having a thickness of 2000Å, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+)-type amorphous Si film having a film thickness of 300Å.

Here, the broken portion of the scanning signal line GL is formed as shown in FIG. 21 (c).

Step E, FIG. 14 After photo processing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F, FIG. 14 After the photographic processing, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 15 A second conductive film d2 made of Cr and having a film thickness of 600 Å is provided by sputtering.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into the dry etching apparatus, N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step H ', FIG. 15 The second conductive film d2 and the third conductive film d3 thus formed.
Then, it is inspected whether the video signal line DL formed of the laminated body of No. 1 is normally connected and no disconnection occurs.

In this case, the inspection is carried out in the same manner as described in step C ', with the probe being brought into contact with the drain terminal portions electrically connected to both ends of each video signal line DL.

Then, with respect to the repair when it is found that a part of the video signal line DL is broken, FIG.
Shown in (a) to (c).

23 (a) to 23 (c) show a cross section taken along line 22-22 in FIG. 2, for example. This figure 2
The disconnection in 3 (b) is repaired in the same manner as in step C '.

Step I, FIG. 15 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

Here, the broken portion of the video signal line DL is formed as shown in FIG. 23 (c).

Step I ', FIG. 15 It is inspected whether or not the scanning signal line GL and the video signal line DL already formed are short-circuited at the intersection.

Here, FIG. 24 shows a configuration in which, when the scanning signal line GL and the video signal line DL are short-circuited, the video signal line DL can be repaired by disconnecting a part thereof. The figure shows a scanning signal line GL and a video signal line D.
FIG. 3 is a plan view of an intersection portion of L, which is an enlarged view of that portion of FIG. 2 in more detail.

The video signal line DL is constructed such that a through hole HJ extending in the longitudinal direction is provided in the central portion at the intersection with the scanning signal line GL.

If a short circuit due to a pinhole or the like in the interlayer insulating film occurs at the portion marked with X in the figure,
A part of the video signal line DL including this portion is connected to the through hole H.
A cut portion indicated by reference numeral CUT in the figure together with J separates the video signal line DL from other portions. As a result, the repair can be achieved by using the video signal lines DL of other portions as they are.

FIGS. 25A to 25C are views showing such a process. First, FIG. 25A shows 2 of FIG.
It is sectional drawing in the 4-24 line. A portion CUT to be cut in FIG. 24 is irradiated with, for example, a laser beam, and as shown in FIG. 25B, the protective film PSV1 and the third conductive film d.
3, the second conductive film d2 and the N (+) type semiconductor layer d0 are removed to perform cutting.

After that, the protective film PSVj is formed at the cut portion by using the laser beam 6 as in the step C '.
In this case, the material gas 7 shown in FIG.
iH ₄ + NH ₅ + N ₂ is selected.

In the manufacturing process described above, the repair of the disconnection of the scanning signal line GL or the video signal line DL is performed after its formation, that is, before the protective film PSV or the like is deposited on the upper surface, but it is not always necessary. It is needless to say that the present invention is not limited to this, and may be performed after the protective film PSV is deposited.

In this case, the disconnection is exposed by removing the protective film PSV with laser light, and then the continuous layer jn is formed as shown in step C ′ or step H ′, and further shown in step I ′. Thus, the protective film PSVj can be formed. The continuous layer jn and the protective film PSVj can be sequentially formed by using the apparatus shown in FIG. 22 as they are, and only by exchanging the material gas 7 supplied to the bell jar 2.

The present invention is not limited to the embodiments described above, and various improvements will make it possible to repair the disconnection more easily and reliably.

For example, the method of scanning the laser beam 6 shown in FIG. 26 is the same as that shown in FIG.
As shown in (3), when the disconnection point is scanned at the shortest distance, the connection layer jn is formed on the foreign matter, which is a reliability problem.

Therefore, when foreign matter is present in the disconnection portion, as shown in FIG. 26B, the foreign matter can be reliably repaired by scanning while avoiding the foreign matter.

When the disconnection repairing method shown in FIG. 26B is performed in the pixel portion, the pixel electrode IT where the coupling layer jn is adjacent to the pixel electrode IT.
Since O1 is covered or contacted, there is a problem that point defects occur. However, since point defects are less noticeable than line defects due to disconnection, the embodiment of FIG. 25 (b) is very effective as a simple and reliable method for repairing disconnection.

Also in this case, if the connection portion between the scanning signal line GL and the coupling layer jn is as shown in FIG.
As a matter of course, the same effect as that shown in is obtained.

That is, in FIG. 27A, both ends of the coupling layer jn are positioned in the notches 50 formed in the scanning signal line GL, respectively, and are sectional views taken along line bb in FIG. As shown in FIG. 27B, the coupling layer jn is connected to the scanning signal line GL at its side end face without overlapping the scanning signal line GL.

The coupling layer jn may be formed by scanning the laser beam 6 a plurality of times. FIG. 28 shows laser light 6
Is an example in which the connecting layer is formed by scanning a plurality of times. In the embodiment shown in FIG. 28, the first connection layer jn1 is formed by the first scanning, and the second connection layer jn1 is formed by the second scanning in the portion over the wiring (in this example, the video signal line DL).
To form the connection layer jn2. Therefore, according to the embodiment of FIG. 28, by increasing the thickness of the connection layer jn in the step portion formed of DL as shown in FIG. 28 (b),
The disconnection of the connecting layer jn is prevented and reliability is improved.

Further, the shape of the bell jar 2 which forms the space for reacting the material gas 7 with the laser light 6 is not limited to the one covering the whole substrate SUB1 as shown in FIG. 22, but also a part of the substrate SUB1 as shown in FIG. It may be covered.
According to the embodiment shown in FIG. 29, only the portion of the substrate SUB1 needs to be covered with the bell jar (2a, 2b, 2c), so that the disconnection can be easily repaired, the device can be downsized, and the entire substrate can be taken in and out. Since it is easier than the one covered, it is characterized by good mass productivity.

The airtightness in the bell jar 2 becomes more problematic in the type that covers a part of the substrate than in the type that covers the entire substrate. Therefore, in the embodiment of FIG. 29, in order to maintain the airtightness inside the bell jar 2, the bell jar 2 is provided with a plurality of bell jars 2a, 2
b, 2c, with a large number of spaces between each bell jar,
Evacuate or flow an inert gas such as N ₂
Maintains airtightness with the atmosphere.

Further, in the embodiment shown in FIG. 29, a replaceable window is provided at the inlet of the laser light 6. It is preferable that the window material has good transparency, and quartz glass is used in the embodiment of FIG.

Generally, in the method of forming a film by using a laser beam, a film is also formed at the laser beam intake port, and there is a problem that the transmittance of the intake port decreases during long-term use.
In the embodiment of FIG. 29, the problem that the transparency of the quartz glass is lowered can be solved by making the quartz glass replaceable.

Note that, as shown in FIG. 1 or FIG. 27, when the connecting layer jn is formed, the connecting layer jn does not form an overlapping region with the wiring layer.
In such a case, it may be possible that the connection between the connection layer jn and the wiring layer may not be well connected. FIG. 30 shows a further improvement in consideration of this.

That is, FIGS. 30 (a), 30 (b) and 30 (c)
In any of the above, the coupling layer jn is positioned in the cutout portion 50 formed in the scanning signal line GL, but the outer portion of the substantial and effective connection path portion of the coupling layer jn is a partial scanning signal. It is superimposed on the line GL.

In this case, there is an effect that the connection with the coupling layer jn around the notch formed in the wiring layer is surely made.

This is because a part of the connection layer jn is formed so as to overlap the wiring layer, so that the connection layer jn is sufficiently attached around the cutout portion.

In this case, the overlapping portion is located on the outer side of the connecting layer jn formed with the disconnection point in between, and in the substantially effective connecting path portion of the connecting layer jn connecting each wiring layer, Since the overlapping portion does not exist, disconnection of the conductive material in the overlapping portion does not cause any particular problem.

When the connection layer jn is formed, FIG.
As shown in (a), the disconnection correction rate is improved by setting the angle θ at which the connecting portion jn and the wiring layer GL are connected to 60 ° or less.

FIG. 31 is data showing the connection angle dependence of the disconnection correction rate obtained by the experiment. The horizontal axis shows the connection angle θ,
The vertical axis is the disconnection correction rate.

As is apparent from FIG. 31, the connection angle θ is 6
It can be seen that the disconnection correction rate is improved at 0 ° or less.
Furthermore, by setting the connection angle to 30 ° or less, the disconnection correction rate becomes 80% or more, which is a level that causes no problem in production.

<< Overall Configuration of Liquid Crystal Display Module >> FIG.
[Fig. 3] is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, and BLS is a backlight. The support and the LCA are the lower case, and the modules MDL are assembled by stacking the respective members in a vertical arrangement relationship as shown in the figure.

The module MDL is a shield case SH.
The whole is fixed by the claw CL and the hook FK provided on D.

The intermediate frame MFR is formed in a frame shape so that an opening corresponding to the display window LCW is provided, and the frame portion has a diffusion plate SPB, a backlight support BLS, and various circuit components in accordance with their shapes and thicknesses. There are irregularities and openings for heat dissipation.

The lower case LCA also serves as a reflector of backlight light, and a reflection mountain RM is formed corresponding to the fluorescent tube BL so as to reflect light efficiently.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 17 is a top view showing a state in which the video signal drive circuits He and Ho and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.

CHI is a driving IC chip for driving the display panel PNL (the lower three are driving ICs on the vertical scanning circuit side).
Chips, 6 each on the left and right are drive I on the video signal drive circuit side
C chip). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 18 and 19, and PCB1 is a driving in which the TCP and the capacitor CDS are mounted. It is divided into three parts on the circuit board. FGP is a frame ground pad,
A spring-like fragment FG provided by cutting into the shield case SHD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1, and the lower drive circuit board PCB1 and the right drive circuit board PCB1. As the flat cable FC, as shown in the figure, a plurality of lead wires (phosphor bronze material plated with Sn) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer are used.

<< TCP Connection Structure >> FIG. 18 shows a sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI, which constitutes the scanning signal driving circuit V and the video signal driving circuits He and Ho, is mounted on a flexible wiring substrate. FIG. 19 is a cross-sectional view of essential parts showing a state in which it is connected to the liquid crystal display panel, in this example, the video signal circuit terminal DTM.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu and has inner ends (commonly called inner leads). ) Is the integrated circuit C
The HI bonding pad PAD is connected by a so-called face-down bonding method. Terminals TTB, T
Outer end portions (commonly called outer leads) of TM correspond to the input and output of the semiconductor integrated circuit chip CHI,
CRT / TFT conversion circuit / power supply circuit S by soldering, etc.
A liquid crystal display panel P is formed on the UP by an anisotropic conductive film ACF.
Connected to NL. The package TCP has a protective film PS whose front end exposes the connection terminal DTM on the panel PNL side.
Since it is connected to the panel so as to cover V1, and therefore the external connection terminal DTM (GTM) is covered by at least one of the protective film PSV1 and the package TCP, it is strong against electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not stick to unnecessary places during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX or the like after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 for multiple protection.

<< Drive Circuit Board PCB2 >> Intermediate Frame M
As shown in FIG. 20, the drive circuit board PCB2 of the liquid crystal display unit LCD which is held / stored in the FR has an L shape, and has electronic components such as ICs, capacitors, and resistors mounted thereon. This drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit SUP including a circuit for converting into information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB2 and the inverter circuit board PCB3 are electrically connected by a backlight cable through a connector hole provided in the intermediate frame MFR.

Drive circuit board PCB1 and drive circuit board PC
B2 is electrically connected by a foldable flat cable FC. When assembled, drive circuit board PCB
2 is stacked on the back side of the drive circuit board PCB1 by bending the flat cable FC by 180 ° and fitted into a predetermined recess of the intermediate frame MFR.

[0163]

As is apparent from the above description,
According to the method of manufacturing a liquid crystal display substrate according to the present invention, it becomes possible to repair a disconnection or a short circuit extremely easily and reliably.

[Brief description of drawings]

FIG. 1 is a process drawing showing an embodiment of a method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 2 is a main-portion plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 3 is a cross-sectional view showing one pixel and its periphery taken along the section line 3-3 in FIG.

FIG. 4 is a cross-sectional view of the additional capacitance Cadd taken along the line 4-4 in FIG.

FIG. 5 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.

FIG. 6 is a panel plan view for slightly exaggerating the peripheral portion of FIG. 5 to explain it more specifically.

FIG. 7 is an enlarged plan view of a corner portion of a display panel including electrical connection portions of upper and lower substrates.

FIG. 8 is a cross-sectional view showing the vicinity of a panel angle and the vicinity of a video signal terminal portion on both sides, with the pixel portion of the matrix at the center.

FIG. 9 is a cross-sectional view showing a scan signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connecting portion between a gate terminal GTM and a gate wiring GL.

FIG. 11 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 12 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 14 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to F on the substrate SUB1 side.

FIG. 15 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps GI on the side of the substrate SUB1.

FIG. 16 is an exploded perspective view of a liquid crystal display module.

FIG. 17 is a top view showing a state in which a peripheral drive circuit is mounted on a liquid crystal display panel.

FIG. 18 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI forming a drive circuit is mounted on a flexible wiring board.

FIG. 19 is a cross-sectional view of essential parts showing a state in which the tape carrier package TCP is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 20: Peripheral drive circuit board PCB1 (top surface visible)
It is a top view which shows the connection state of power supply circuit circuit board PCB2 (a lower surface is visible).

FIG. 21 is a process diagram for repairing disconnection of a scanning signal line.

FIG. 22 is a configuration diagram showing an embodiment of a photo-CVD apparatus used in the present invention.

FIG. 23 is a process diagram for repairing disconnection of a video signal line.

FIG. 24 is an explanatory diagram showing a configuration for repairing a short circuit between a scanning signal line and a video signal line.

FIG. 25 is a process drawing showing another embodiment for repairing the disconnection of the video signal line.

FIG. 26 is a diagram illustrating a scanning method of laser light 6 according to the present invention.

FIG. 27 is an explanatory diagram showing another embodiment of the present invention.

FIG. 28 is a diagram showing another example of the scanning method of the laser beam 6.

FIG. 29 is a diagram showing another embodiment of the photo-CVD apparatus used in the present invention.

FIG. 30 is an explanatory diagram showing another embodiment of the present invention.

FIG. 31 is a diagram showing a relationship between a connection angle and a disconnection correction rate.

[Explanation of symbols]

SUB ... Transparent glass substrate, GL ... Scan signal line, DL ... Video signal line GI ... Insulating film, GT ... Gate electrode, AS ... i-type semiconductor layer SD ... Source electrode or drain electrode, PSV ... Protective film, BM ... Light-shielding film LC ... Liquid crystal, TFT ... Thin film transistor, ITO ... Transparent pixel electrode g, d ... Conductive film, Cadd ... Storage capacitor element, AOF ... Anodized film AO ... Anodized mask, GTM ... Gate terminal, DTM ...
Drain terminal SHD ... Shield case, PNL ... Liquid crystal display panel, S
PB ... Light diffusion plate, MFR ... Intermediate frame, BL ... Backlight, BLS ... Backlight support, LCA ... Lower case, RM ... Backlight light reflection mountain (abbreviated above). 5 ... Laser source, 6 ... Laser light, 7 ... Material gas, 8
... N ₂ gas, 9 ... quartz glass, 10 ... foreign matter.

Claims (5)

[Claims] 1. A method of manufacturing a liquid crystal display substrate, which includes a step of inspecting a wiring layer formed on a liquid crystal side surface of at least one transparent substrate facing each other with a liquid crystal interposed therebetween. The method further comprises the step of repairing the disconnection by adhering a conductive material to the disconnection point of the wiring layer, and forming a notch by previously cutting out a portion of the wiring layer that becomes a region where the conductive material overlaps. A method of manufacturing a liquid crystal display substrate, comprising: connecting the conductive material to a wiring layer around the cutout portion of the wiring layer. 2. The invention according to claim 1, wherein a notch portion of a portion of the wiring layer which is a superposed region of the conductive material is a part of the superposed region, whereby a conductive material is formed with a disconnection point therebetween. A method for manufacturing a liquid crystal display substrate, characterized in that a part of an outer portion of the substrate is overlapped with a wiring layer. 3. The method of manufacturing a liquid crystal display substrate according to claim 1 or 2, wherein the conductive material is attached by a photo-CVD method. 4. The invention according to claim 1, wherein a connection angle defined by a side of the wiring layer connected to the conductive material and a long side direction of the conductive material is 60 ° or less. Liquid crystal display substrate manufacturing method. 5. The invention according to claim 1, wherein a connection angle defined by a side of the wiring layer connected to the conductive material and a long side direction of the conductive material is 30 ° or less. Liquid crystal display substrate manufacturing method.