JPH0864825A - Method of fabrication of thin film transistor - Google Patents

Abstract

PURPOSE: To improve reliability by improving insulation voltage in a method of fabrication of a thin film transistor that takes a structure there a semiconductor part becoming a channel is not deteriorated. CONSTITUTION: A thin film transistor is fabricated which has a structure wherein a main gate electrode 7 and an auxiliary gate electrode 5a are substantially parallely provided on the upper part of a channel region without producing any step part on the channel region. In this case an oxide film 5' is interposed between the main gate electrode and the auxiliary gate electrode by oxydizing the upper surfaces of the main gate electrode and the auxiliary gate electrode. Hereby, insulation voltage between the main gate electrode and the auxiliary gate electrode is improved and hence a highly reliable thin film transistor is ensured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used in a display device such as an active matrix liquid crystal display device, and in particular, can reduce off current, suppress characteristic variations, and improve reliability. The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor made of polysilicon or amorphous silicon has been known as a thin film semiconductor device of this type. In particular, a thin film transistor made of polysilicon is higher than a thin film transistor made of amorphous silicon. Since it is possible to obtain mobility and a relatively high current drive capability, it is suitable as, for example, a switching element of an active matrix panel integrated with a peripheral drive circuit. However, the polysilicon thin film transistor has a problem that the leak current is larger than that of the amorphous thin film transistor. As a technique for solving this drawback, for example, Japanese Patent Laid-Open No. 58-105.
As disclosed in Japanese Patent No. 574, a region having a low impurity concentration (hereinafter referred to as "low concentration impurity region") is provided between the channel layer of the thin film transistor and the drain / source region.
A thin film transistor called an LDD (Lightly Doped Drain) structure that has been formed has been proposed.

As a technique for reducing the leak current, for example, "Extended Abstracts of the 22nd Confe"
rence on Solid State Devices and Materials (p.101)
, A structure in which an impurity region not doped with impurities is provided between the gate and the drain, and a second gate electrode is provided so as to cover the upper surface thereof. The one that has been proposed.

[0004]

However, the former length of the low-concentration impurity region in the channel direction largely influences the characteristics of the thin film transistor, and the low-concentration impurity region is formed twice in the manufacturing process. Since it is decided through the lithography process, the accuracy of the length of the low-concentration impurity region is also determined depending on the accuracy of the mask alignment in these two photolithography processes, which causes a relative variation. As a result, there is a problem that the characteristic variation of the thin film transistor is relatively large as a result. In the latter case, the first gate electrode and the second gate electrode are opposed to each other with the insulator interposed therebetween, so that the first gate electrode and the second gate electrode are opposed to each other. -There is a problem that a parasitic capacitance is formed between the gate electrode and the gate electrode, which causes a decrease in operating speed due to the parasitic capacitance and a decrease in output voltage due to a so-called field through.

Therefore, the present applicant invented a thin film transistor having a structure that solves the problems in the above-mentioned two conventional examples, and has already filed an application (Japanese Patent Application No. 5-69191).
issue). Further, in the thin film transistor of the above-mentioned Japanese Patent Application No. 5-69191, since the semiconductor layer serving as a channel has irregularities, a decrease in withstand voltage is induced at the step portion, and a semiconductor is used when the active poly-Si region is crystallized by a laser beam. In order to solve the problem that the thermal conductivity of the underlayer of the layer is locally different, which prevents uniform crystal growth and causes variations in TFT characteristics, a thin film transistor having the structure shown in FIG. (Japanese Patent Application 5-25
3668).

That is, the thin-film transistor will be described with reference to FIG. 7. This thin-film transistor comprises a poly-Si region 2 as a channel region, a source / drain, on an insulating substrate 1 made of an insulating member such as glass. Regions 3a and 3b are formed, and these poly-Si
The region 2 and the source / drain regions 3a and 3b are covered with the first gate insulating film 4. A second trapezoidal cross section is formed on the first gate insulating film 4.
The gate electrodes 5a and 5b are provided at appropriate intervals in the horizontal direction (left-right direction on the paper surface in FIG. 7). Further, the second gate electrodes 5a, 5b and the first gate are formed.
A second gate insulating film 6 is formed so as to cover the gate insulating film 4. The first gate electrode 7 is formed on the second gate insulating film 6 in the recess formed between the second gate electrodes 5a and 5b. The second gate insulating film 6 and the first gate electrode 7 are covered with an interlayer insulating film 8, and contact holes are bored in the interlayer insulating film 8 to form source / drain regions 3a and 3b. Electrode layer 10a connected to
10b is formed. Interlayer insulating film 8 and electrode layer 10
A passivation layer 9 is laminated on a and 10b as a protective layer.

With this structure, no step is formed in the poly-Si region 2 as the channel region,
Moreover, since the first gate electrode 7 and the second gate electrodes 5a and 5b are arranged substantially above the channel region, there is no portion in the channel region where the local dielectric strength is lowered, The reliability can be improved. Further, since the step difference in the channel region is eliminated, the thermal conductivity of the underlying layer does not differ, so that the crystal growth becomes uniform during crystallization by annealing and a thin film transistor with less variation in characteristics can be obtained. It is possible.

However, in the above-mentioned thin film transistor, the first gate electrode 7 and the second gate electrode 5 are used.
Since the second gate insulating film 6 existing between a and 5b needs to be thin due to the structure of the thin film transistor, a pinhole or the like is generated in this portion and the first gate insulating film 6 is formed. Dielectric breakdown is likely to occur between the gate electrode and the second gate electrode, which has led to the discovery of a new problem of reduced reliability.

The present invention has been made in view of the above circumstances, and has a structure that does not cause deterioration of a semiconductor that serves as a channel, has high reliability, and has a small off-current and a small parasitic capacitance. It is intended to provide a manufacturing method.

[0010]

In order to solve the above problems, the invention of claim 1 includes a step of forming an active layer silicon film on a substrate and a gate insulating film covering the active layer silicon film. A step of forming, a step of forming a main gate electrode and an auxiliary gate electrode adjacent to each other on the gate insulating film, a step of forming the main gate electrode and the auxiliary gate of the active layer silicon film. A step of introducing an impurity into a region other than the region corresponding to the gate electrode to form a source and drain region, and a step of forming the gate insulating film, after the step of forming the gate insulating film, Forming the auxiliary gate electrode on the gate insulating film, oxidizing the surface of the auxiliary gate electrode, and adjoining the auxiliary gate electrode after the oxidizing step. And a step of forming a gate electrode. It is characterized by a door.

According to a second aspect of the present invention, a step of forming an active layer silicon film on a substrate, a step of forming a gate insulating film covering the active layer silicon film, and a step of forming a gate insulating film on the gate insulating film. A step of forming a main gate electrode and an auxiliary gate electrode adjacent to each other, and impurities are added to a region of the active layer silicon film other than a region corresponding to the main gate electrode and the auxiliary gate electrode. In the method of manufacturing a thin film transistor, the method comprises the steps of forming a source and a drain region by introducing the source and gate regions, and after forming the gate insulating film, the main gate electrode is formed on the gate insulating film. And the main gate
And a step of forming the auxiliary gate electrode adjacent to the main gate electrode after the step of oxidizing the gate electrode surface.

The invention of claim 3 is the invention of claim 1 or claim 2.
In the method of manufacturing a thin film transistor, said auxiliary gate
A gate electrode is formed adjacent to both sides of the main gate electrode.

[0013]

The main gate electrode and the auxiliary gate electrode are formed by interposing an oxide film formed on the surface of the main gate electrode or the auxiliary gate electrode between the main gate electrode and the auxiliary gate electrode. The withstand voltage between them is improved, and a highly reliable thin film transistor can be obtained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film transistor manufactured by the method of the present invention will be described below with reference to FIGS. Here, FIG. 1 is a vertical cross-sectional view of one example of a thin film transistor manufactured by the method of the present invention (AA in FIG. 2).
2 is a plan view of the thin film transistor of FIG. 1,
3 and 4 are vertical sectional views in the main steps for explaining the manufacturing process of the thin film transistor according to the present invention.

The thin film transistor shown in FIG. 1 manufactured by the method of the present invention is similar to the thin film transistor shown in FIG. 7 on the insulating substrate 1 made of an insulating member such as glass.
A poly-Si region 2 serving as a channel region, source / drain regions 3a and 3b, and a first gate insulating film 4 covering the poly-Si region 2 and the source / drain regions 3a and 3b are sequentially laminated. are doing. Then, on the first gate insulating film 4, second gate electrodes 5a and 5b as auxiliary gate electrodes having a substantially trapezoidal cross section are arranged in the horizontal direction (the horizontal direction in the drawing of FIG. 1). In the above, it is provided with an appropriate interval.

The characteristic structure of this thin film transistor is as follows.
That is, an oxide film 5'is formed on the upper surfaces of the second gate electrodes 5a and 5b. A second gate insulating film 6 is formed so as to cover the oxide film 20 of the second gate electrodes 5a and 5b and the first gate insulating film 4. Then, in the recess formed between the second gate electrodes 5a and 5b, the first gate electrode 7 as the main gate electrode is formed on the second gate insulating film 6. . By forming the oxide film 5 ', an oxide film 5'and a second gate insulating film are provided between the second gate electrodes 5a and 5b and the first gate electrode 7. 6 exists, the dielectric breakdown between the electrodes can be surely prevented by the presence of the oxide film 5'having a high withstand voltage.

The second gate insulating film 6 and the first gate insulating film 6 are also provided.
The upper surface of the electrode 7 is covered with an interlayer insulating film 8 and
A contact hole is drilled in the source / drain region 3
Electrode layers 10a and 10b connected to a and 3b are formed. A passivation layer 9 is stacked as a protective layer on the interlayer insulating film 8 and the electrode layers 10a and 10b.

The thin film transistor is assumed to be used as, for example, a switching element for driving a liquid crystal element in an active matrix type liquid crystal display device, and FIG. 2 shows a main arrangement configuration of a pixel portion in that case. It is what In the figure,
From the source / drain region 3b, a second electrode body 5 is formed on the second gate electrode with the same metal pattern.
A storage capacitor electrode portion 11 is extended so as to face c, and a storage capacitor 12 is formed between the storage capacitor electrode portion 11 and the second gate electrode main body portion 5c.

Next, the manufacturing process of the thin film transistor will be described with reference to FIGS. First, for example, amorphous silicon is provided on the insulating substrate 1.
The film is deposited to a film thickness of about 100 nm by the LPCVD method, and is exposed to a furnace or is irradiated with a laser beam to perform crystallization anneal, and is patterned to form an island-shaped semiconductor layer poly. -Si region 2 is obtained. Then, a first gate insulating film 4 is formed on the poly-Si region 2 by depositing, for example, silicon oxide in a film thickness of about 50 nm by the ECR-CVD method (FIG. 3A). )).

Subsequently, Ta is sputtered to about 500
The second gate electrodes 5a and 5b are formed by depositing a film having a thickness of about nm and patterning by photolithography after the deposition. Although not shown in FIG. 3, when the thin film transistor manufactured by the method of the present invention is applied to a liquid crystal display device, the second
The gate electrode body 5c (see FIG. 2) is also formed at the same time. Next, the surfaces of the second gate electrodes 5a and 5b are anodized to form an oxide film 5 '(FIG. 3).
(B)).

Further, for example, LPCVD of silicon oxide is performed.
Method or plasma CVD method to form a second gate insulating film 6 with a film thickness of about 50 nm (FIG. 3).
(C)). Subsequently, polysilicon is deposited to a film thickness of about 300 nm and then patterned by photolithography to form an electrode layer 13, and then a resist 14 is formed.
Is coated on the entire surface (FIG. 3 (d)). Subsequently, by etching back the resist 14 whose surface is flattened, the electrode layer 13 is flattened so that the end portions of the second gate electrodes 5a and 5b become the electrode end portions. 1
A gate electrode 7 is obtained (FIG. 4 (a)). By this flattening, the position of the upper surface of the first gate electrode 7 and the position of the upper surfaces of the second gate electrodes 5a and 5b become substantially the same position.

Impurity ions such as P (in the case of an n-channel thin film transistor) are implanted into the entire surface from above to form the source / drain regions 3a and 3b (FIG. 4 (b)). At this time, the poly-Si region 2 located immediately below the first gate electrode 7 and the second gate electrodes 5a and 5b.
Includes a first gate electrode 7 and a second gate electrode 5a,
Since 5b serves as a mask, ions are not implanted, and the length of this portion (left and right in the plane of FIGS. 3 and 4) is determined by the first gate electrode 7 and the second gate electrode. 5
It is set in a self-aligned manner with respect to a and 5b.

Next, for example, silicon oxide is used for plasma CV.
The interlayer insulating film 8 is formed by the D method with a film thickness of about 1 μm.
Is formed (FIG. 4C), and thereafter, contact holes are formed, an A1-Cu film is formed by sputtering, and patterning is performed in order to form electrode layers 10a and 10b. Finally, by depositing silicon oxide to obtain the passivation layer 9, the thin film transistor of this embodiment is completed (see FIG. 1).

In the above structure, the second gate electrode 5
A voltage approximately the same as the voltage applied to the first gate electrode 7 is constantly applied to a and 5b. As a result, the portion of the poly-Si region 2 immediately below the second gate electrodes 5a and 5b becomes a low resistance region, so that the drain end where the electric field is concentrated in the off state of the thin film transistor is The electric field concentration is alleviated by the low resistance region, crystal defects due to impurity implantation are reduced, and the off current is sufficiently reduced. Therefore, the channel length can be set shorter than that of the thin film transistor having the structure described in the conventional example. Further, an oxide film 5'having a relatively high withstand voltage even if the film thickness is thin is present between the first gate electrode 7 and the second gate electrodes 5a and 5b, so that there is a gap between the electrodes. The breakdown voltage can be improved to prevent dielectric breakdown, and the reliability of the thin film transistor can be improved.

Further, according to the thin film transistor having the structure of FIG. 1, the first gate electrode 7 and the second gate electrodes 5a, 5 are formed.
A parasitic capacitance is generated between portions b between the side walls of the first and second sidewalls, but the size thereof is smaller than that of the conventional parasitic capacitance due to the structure, and the first gate is used. -By reducing the lateral width of the electrode 7 (left and right in the plane of FIG. 1) (inevitably the channel length is shortened),
The parasitic capacitance generated between the first and second gate electrodes 7, 5a and 5b can be reduced, and the signal delay in the gate line can be reduced.

In the embodiment described above, the surface of the second gate electrodes 5a and 5b, which are the auxiliary gate electrodes, is oxidized to oxidize the oxide film 5'between the first gate electrode 7 and the second gate electrodes 5a and 5b. However, by oxidizing the surface of the first gate electrode 7, which is the main gate electrode, an oxide film 7'may be interposed between both electrodes as shown in FIG. In this case, the manufacturing order of the first gate electrode 7 and the second gate electrodes 5a and 5b is opposite.

That is, as shown in FIG. 6, the insulating substrate 1
After forming the poly-Si region 2 and the first gate insulating film 4 thereon, a Ta film is deposited and patterned to form a first gate electrode 7 serving as a main gate electrode. The surface of the gate electrode 7 is anodized to form an oxide film 7'and further a second gate insulating film 6 (FIG. 6).
(A)). Then, polysilicon is deposited to a film thickness of about 300 nm and then patterned by photolithography to form an electrode layer 13, and a resist 14 is coated on the entire surface (FIG. 6B). By etching back the flattened resist 14,
The second gate electrodes 5a, 5 are formed by flattening the electrode layer 13 so that the end portion of the first gate electrode 7 is located at the end portion of the electrode.
b is obtained (FIG. 6 (c)). By this flattening, the first gate
Position of the upper surface of the gate electrode 7 and the second gate electrodes 5a, 5b
The position is substantially the same as the position of the upper surface of. Then, similarly to the process shown in FIGS. 3 and 4, an ion implantation process is performed to manufacture a thin film transistor. According to this embodiment, similar to the embodiment shown in FIG. 1, the first gate electrode 7 and the second gate electrode 7
Since the oxide film 7'having a relatively high withstand voltage even if the film thickness is thin is present between the gate electrodes 5a and 5b, the withstand voltage between the electrodes is improved and the occurrence of dielectric breakdown is prevented. The reliability of the thin film transistor can be improved.

In each of the above embodiments, the second gate electrode 5 is arranged as the auxiliary gate electrode on both sides of the first gate electrode 7 as the main gate electrode. The structure in which 5 is arranged on one side may be adopted.

[0029]

According to the present invention, a thin film transistor having a structure in which a main gate electrode and an auxiliary gate electrode are arranged substantially above the channel region so that no step is formed in the channel region is manufactured. In some cases, an oxide film can be interposed between the main gate electrode and the auxiliary gate electrode by oxidizing the upper surface of the main gate electrode or the auxiliary gate electrode. -The withstand voltage between the gate electrodes can be improved and a highly reliable thin film transistor can be obtained.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional explanatory view of a thin film transistor manufactured by the method of the present invention.

FIG. 2 is an explanatory plan view when a thin film transistor is applied to a pixel portion of a liquid crystal display.

3A to 3D are vertical cross-sectional explanatory views showing a part of the manufacturing process of the thin film transistor.

4A to 4C are vertical cross-sectional explanatory views showing a part of the manufacturing process of the thin film transistor.

FIG. 5 is a vertical cross-sectional explanatory view showing another embodiment of the thin film transistor.

6A to 6C are explanatory longitudinal sectional views showing a part of the manufacturing process of the thin film transistor of FIG.

FIG. 7 is a vertical cross-sectional explanatory view of a thin film transistor according to the invention of the present applicant, which is the basis of the thin film transistor manufactured by the method of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 1, 2 ... Poly-Si area | region, 4 ... 1st gate insulating film, 5a, 5b ... 2nd gate electrode (auxiliary gate electrode), 5 ', 7' ... Oxide film, 5c ... second gate electrode main body portion, 6 ... second gate insulating film, 7 ...
First gate electrode (main gate electrode)

Claims (3)

[Claims] 1. A step of forming an active layer silicon film on a substrate, a step of forming a gate insulating film covering the active layer silicon film, and a main gate adjacent to each other on the gate insulating film. A step of forming a gate electrode and an auxiliary gate electrode, and an impurity is introduced into a region of the active layer silicon film other than a region corresponding to the main gate electrode and the auxiliary gate electrode. A step of forming a gate region and a drain region, and a step of forming the auxiliary gate electrode on the gate insulating film after the step of forming the gate insulating film. And a step of oxidizing the surface of the auxiliary gate electrode, and a step of forming the gate electrode adjacent to the auxiliary gate electrode after the oxidation step. Method of manufacturing thin film transistor. 2. A step of forming an active layer silicon film on a substrate, a step of forming a gate insulating film covering the active layer silicon film, and main gates adjacent to each other on the gate insulating film. A step of forming a gate electrode and an auxiliary gate electrode, and an impurity is introduced into a region of the active layer silicon film other than a region corresponding to the main gate electrode and the auxiliary gate electrode. A step of forming a gate and a drain region, and a step of forming the main gate electrode on the gate insulating film after the step of forming the gate insulating film. And a step of oxidizing the surface of the main gate electrode, and a step of forming the auxiliary gate electrode adjacent to the main gate electrode after the oxidation step. Method of manufacturing thin film transistor. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the auxiliary gate electrode is formed adjacent to both sides of the main gate electrode. Method.