JPH0864611A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE: To easily manufacture a bipolar transistor having a high-speed operational function by facilitating surface control and thickness control in the manufacture process of the bipolar transistor. CONSTITUTION: Manufacture of a bipolar transistor includes steps of: forming a first semiconductor layer as an emitter at a predetermined position on a first insulating film 4 formed on a semiconductor substrate 1 as a collector; forming a second insulating film 7 on the first semiconductor layer; and removing a part of the first insulating film 4 located on a lower side of a multilayer body composed of the first semiconductor layer and the second insulating film 7 and a part of the first insulating film adjacent to the above-mentioned part and located on a lateral side of the multilayer body, thus exposing a part of the back surface of the first semiconductor layer and a part of the surface of the semiconductor substrate. The manufacture also includes the step of epitaxial growth of a second semiconductor layer of the second conductance type as a base on the exposed surface of the semiconductor substrate so that the semiconductor substrate is electrically connected with the first semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high speed bipolar transistor using a low temperature epitaxial growth method.

[0002]

2. Description of the Related Art A conventional bipolar transistor manufacturing process using a low temperature epitaxial growth method (hereinafter referred to as a low temperature epi growth method) is shown in FIGS. In each figure,
(A) shows the cross section of a bipolar transistor, (b) has shown the upper surface of a bipolar transistor.

FIG. 6 shows a step of forming an epitaxial base layer (hereinafter referred to as an epi base layer) 2. First, in order to remove a natural oxide film (not shown) on the semiconductor substrate 1 which is an n-type collector layer, high temperature annealing is performed using a reducing gas. Next, in-situ-doping Chemical Vapor Depo
sition, hereinafter referred to as in-situ-doping CVD), to perform low temperature epitaxial growth (hereinafter referred to as low temperature epi growth) of the p-type epi base layer 2 on the semiconductor substrate 1.
At this time, the epi base layer 2 is formed on the entire surface of the semiconductor substrate 1. By the way, CVD is a method of forming a desired thin film by supplying one or several kinds of compound gas consisting of elements constituting a thin film material or a simple substance gas onto a semiconductor substrate and performing a chemical reaction in a vapor phase or on the substrate surface. In that case, a desired doping gas is selected as a gas to be supplied onto the substrate, and the thin film is formed while doping the impurities in the doping gas into the thin film, which is particularly called in-situ - doping CVD.

FIG. 7 shows a step of forming the emitter layer 3 and the first insulating film 4. First, a natural oxide film (not shown) formed on the surface of the epi base layer 2 is removed by the above-mentioned high temperature annealing. Then, an n-type emitter layer 3 made of polycrystalline silicon is grown on the entire surface of the epi base layer 2 at low temperature by in-situ-doping CVD. Further, a first insulating film 4 is formed on the entire surface of the emitter layer 3 by CVD. Next RI
The emitter layer 3 is formed at a predetermined position on the epi base layer 2 by the E method.
Then, the first insulating film 4 is left and formed.

FIG. 8 shows a step of forming the sidewall insulating film 5. First, a resist (not shown) is formed on the first insulating film and at a predetermined position on the epi base layer. At this time, the resist on the epi base layer is formed by the emitter layer 3 and the first insulating film 4.
Are formed so as to surround them with a predetermined interval, and as a result, a groove is formed around the emitter layer 3 and the first insulating film 4. Next, the sidewall insulating film 5 is formed in a resist and a groove (not shown). Further, the sidewall insulating film 5 is etched by the RIE method to be left and formed in a fan shape as shown in FIG. At this time, the emitter layer 3 and the first insulating film 4
The side walls of the are entirely covered with the side wall insulating film 5 as shown in FIG.

FIG. 9 shows a step of forming the base electrode layer 6. First, by in-situ-doping CVD, the base electrode layer 6 is epitaxially grown at a low temperature so as to cover the first insulating film 4 and the sidewall insulating film 5 as shown in FIG. At this time, the ends of the first insulating film 4 and the sidewall insulating film 5 are shown in FIG.
It is not covered with the base electrode layer 6 as shown in FIG. Next, as the heat treatment, the semiconductor substrate 1 is heated to thermally diffuse the impurities contained in the emitter layer 3 from the emitter layer 3 to the epi base layer 2 to form the emitter layer 8.

The bipolar transistor is manufactured as described above. By the way, the operating speed of the bipolar transistor is further increased by forming a shallow and steep profile at each interface of the emitter layer 3, the epi base layer 2, and the semiconductor substrate 1. Although such a bipolar transistor is called a high speed bipolar transistor, it has been difficult to manufacture a high speed bipolar transistor by the conventional manufacturing method due to the following problems.

First, there is a problem of controlling the impurity profile at the interface between the base layer 2 and the collector layer (semiconductor substrate 1) and between the base layer 2 and the emitter layer 3. That is, when the base layer 3 is formed by the low temperature epi growth shown in FIG. 7, it is necessary to remove the natural oxide film (not shown) to expose the clean surface of the base layer 2 before the low temperature epi growth. In the manufacturing method, high-temperature annealing is performed at a temperature of at least 900 ° C. or higher using a reducing gas such as H ₂ . However, when high temperature annealing is performed, the steep profile of the base layer 2 formed by low temperature epitaxial growth becomes a gentle profile due to the re-diffusion of impurities.

Next, there is a problem of film thickness control. Usually, in the case of performing epi-growth, a delay time occurs after the reaction gas is flown until the growth nuclei are generated on the growth surface and epi-growth starts. This delay time is short and negligible in the case of growing at a high temperature, but becomes long when the growth temperature is lowered and affects the controllability of the film thickness. Further, this delay time also depends on the cleanliness of the growth atmosphere, and in the case of low temperature epi growth, H2 and H2 O that hinder low temperature epi growth are generated in large quantities in the atmosphere, and the delay time becomes large, and the film pressure controllability is increased. Have a great impact on As a result, the base resistance cannot be controlled.

[0010]

As described above, it has been difficult to control the interface and the film pressure in the conventional method for manufacturing a bipolar transistor. It is an object of the present invention to eliminate the above-mentioned drawbacks and provide a method for manufacturing a high-speed bipolar transistor in which interface control and film pressure control are easy.

[0011]

In order to achieve the above object, according to the present invention, a step of forming a first insulating film on a semiconductor substrate of a first conductivity type serving as a collector, and the first insulating film. A step of forming a first conductive type second semiconductor layer to be an emitter at a predetermined position, and a second step on the first semiconductor layer.
A step of forming an insulating film, and a part of the first insulating film located below the stacked body of the first semiconductor layer and the second insulating film, and the stacked body adjacent to the part of the first insulating film. Removing a part of the first insulating film laterally located to expose a part of the back surface of the first semiconductor layer and a part of the front surface of the semiconductor substrate; and exposing the semiconductor substrate. And a step of epitaxially growing a second semiconductor layer of a second conductivity type serving as a base on the formed surface so that the semiconductor substrate and the first semiconductor layer are electrically connected to each other. To do.

[0012]

When the means provided by the present invention is used, high temperature annealing is not performed after the epi-base layer 2 having a steep profile is formed, so that the impurities in the epi-base layer 2 do not re-diffuse and a steep profile is produced in the manufacturing process. Can be maintained. Further, the epi base layer 2 is the emitter electrode layer 3
Since the epitaxial growth is performed so that the gap between the semiconductor substrate 1 and the semiconductor substrate 1 is completely filled, the growth thickness depends on the size of the gap and is formed to have a constant thickness without being affected by various conditions during the epi growth. You can As a result, a high speed bipolar transistor can be easily manufactured.

[0013]

An embodiment of the present invention will be described with reference to the drawings.
1 to 5 show a method of manufacturing the bipolar transistor of the present invention in the order of steps. In each figure, (a) shows the cross section of the bipolar transistor, and (b) shows the upper surface of the bipolar transistor.

FIG. 1 shows a step of forming the second insulating film 7. Si is used as the n-type collector layer on the semiconductor substrate 1.
A crystal substrate is selected, and high temperature annealing is performed using a reducing gas in order to remove a natural oxide film (not shown) on the surface of the crystal substrate. Next, the semiconductor substrate 1 is exposed to an oxygen atmosphere to form a second insulating layer 7 on its surface. The material of the insulating film is preferably one that can be easily etched by wet etching, and SiO ₂ is used in this embodiment. Further, this film thickness needs to be set to the same level as the base layer formed in a later step, and is preferably set to about 50 nm.

FIG. 2 shows the emitter electrode layer 3 and the first insulating film 4.
It shows a process of forming. First, on the entire surface of the second insulating film 7, the emitter electrode layer 3 is epitaxially grown at a low temperature by in-situ-doping CVD to a thickness of 400 nm. Further, a first insulating film 4 having a thickness of 150 nm is formed on the entire surface of the emitter electrode layer 3 by CVD. Next, the emitter electrode layer 3 and the first insulating film 4 are formed in a rectangular shape at predetermined positions on the second insulating film 7 by the RIE method. The material of the first insulating film 4 needs to be different from that of the second insulating film 7, and Si ₃ N ₄ is preferably selected so as not to be wet-etched at the same time in a later step.

FIG. 3 shows a step of forming the side wall insulating film 5. First, a resist (not shown) is formed on the first insulating film and at a predetermined position on the epi base layer. At this time, the resist on the epi base layer is formed by the emitter layer 3 and the first insulating film 4.
Are formed so as to surround them with a predetermined interval, and as a result, a groove is formed around the emitter layer 3 and the first insulating film 4. Next, the sidewall insulating film 5 is formed in a resist and a groove (not shown). Further, the sidewall insulating film 5 is etched by the RIE method to be left and formed in a fan shape as shown in FIG. At this time, the emitter layer 3 and the first insulating film 4
The side walls of the are entirely covered with the side wall insulating film 5 as shown in FIG. Setting the maximum width of the side wall insulating film 5 in the surface direction of the semiconductor substrate 1 to about 100 nm is effective for increasing the speed of the bipolar transistor.

FIG. 4 shows a step of removing the second insulating film 7. First, a resist (not shown) is patterned to form a rectangular opening on the second insulating film 7, the first insulating film 4 and the sidewall insulating film 5. At this time, an opening portion of the resist is formed in the central portion of the upper surfaces of the first insulating film 4 and the side wall insulating film 5 so as to intersect with the first insulating film 4 having a rectangular shape. The first insulating film 4, the sidewall insulating film 5, and the second insulating film 7 are exposed. Next, wet etching is performed using this opening to remove the side wall insulating film 5 and the second insulating film 7 near the lower part and the central part of the emitter layer 3 so that the surface of the semiconductor substrate 1 is exposed. At that time, an HF solution or an NH ₄ F solution may be used for the wet etching. The state of the emitter layer 3 after this wet etching has a tunnel structure as shown in FIG. 3D, and the emitter electrode layer 3 is supported by the remaining second insulating film 7. Finally, the resist not shown is removed.

FIG. 5 shows a step of forming the epi base layer 2 and the base electrode layer 6. First, in order to remove the unillustrated natural oxide film on the exposed surface of the semiconductor substrate 1, the semiconductor substrate 1 is annealed at a high temperature to clean the surface of the semiconductor substrate 1 again. The annealing conditions are 90% in an H ₂ atmosphere in order to suppress the diffusion of impurities in the diffusion layer.
It is preferable to heat at 0 ° C. for 1 minute. Next, on the surface of the semiconductor substrate 1, a thin epi base layer 2 is selectively grown by low temperature epi growth so that the entire lower surface of the emitter electrode layer 3 and the sidewall insulating film 5 is covered. Conditions for low temperature epi growth are a growth temperature of 700 ° C. and a growth pressure of 1330.
Pa, carrier gas is hydrogen (H ₂ ) with a flow rate of 20 slm,
The silicon (Si) source gas may be dichlorosilane (SiH ₂ Cl ₂ ) having a flow rate of 400 sccm, and the doping gas may be a mixed gas having a flow rate of 200 sccm containing diborane (B ₂ H ₆ ) in hydrogen gas at a concentration of 150 ppm. preferable. The growth thickness of the epi base layer 2 is difficult to control in the case of low temperature epi growth, but in this embodiment it is determined by the film pressure of the second insulating film 7. The electrode layer 3 is electrically conductive and the film thickness can be easily controlled. Finally, by CVD, the base electrode layer 6 is formed into an epi base layer 2 as shown in FIG.
And the first insulating film 4 and the sidewall insulating film 5 are formed. However, the ends of the first insulating film 4 and the sidewall insulating film 5 are
It does not need to be covered from the base electrode layer 6 as shown in FIG. The base electrode layer 6 is preferably made of amorphous silicon doped with impurities. In order to operate as a bipolar transistor, it is necessary to thermally diffuse impurities from the emitter electrode layer 3 into the epi base layer 2 to form the emitter layer 8, but in this embodiment, it is 800.
It is possible to sufficiently operate the bipolar transistor by only performing heat treatment at 5 ° C. for about 5 minutes.

[0019]

As described above, according to the present invention, the interface control and the film pressure control are facilitated in the bipolar transistor manufacturing process, so that the bipolar transistor having the high speed operation function can be easily manufactured. .

[Brief description of drawings]

FIG. 1 is a process cross-sectional view of forming a second insulating film showing an embodiment of the present invention.

FIG. 2 is a process cross-sectional view of forming an emitter layer and a first insulating film showing an embodiment of the present invention.

FIG. 3 is a process cross-sectional view of forming a sidewall insulating film showing an example of the present invention.

FIG. 4 is a sectional view of a step of removing a second insulating film, showing an embodiment of the present invention.

FIG. 5 is a process sectional view of forming an epi base layer and a base layer showing an embodiment of the present invention.

FIG. 6 is a process cross-sectional view of forming an epi base layer showing a conventional example.

FIG. 7 is a process cross-sectional view showing a conventional example in which an emitter layer and a first insulating film are formed.

FIG. 8 is a process sectional view of forming a sidewall insulating film showing a conventional example.

FIG. 9 is a process sectional view of forming a base layer showing a conventional example.

[Explanation of symbols]

 1 semiconductor substrate 2 epitaxial base layer (base layer) 3 emitter electrode layer 4 first insulating film 5 sidewall insulating film 6 base electrode layer 7 second insulating film 8 emitter layer

Claims (4)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate of the first conductivity type which serves as a collector, and a first conductivity type first semiconductor film which serves as an emitter at a predetermined position on the first insulation film. A step of forming a semiconductor layer; a step of forming a second insulating film on the first semiconductor layer; a step of forming a second insulating film on the first semiconductor layer; and a step of arranging the second insulating film under a stacked body of the first semiconductor layer and the second insulating film. A part of the first insulating film and a part of the first insulating film adjacent to the first insulating film and located laterally of the stacked body are removed, and a part of the back surface of the first semiconductor layer and the part A step of exposing a part of the surface of the semiconductor substrate; and a second semiconductor layer of the second conductivity type serving as a base, which is electrically connected to the exposed surface of the semiconductor substrate. And a step of epitaxially growing so as to be connected to Method of manufacturing a transistor. 2. The method of manufacturing a bipolar transistor according to claim 1, wherein the first insulating film is removed by wet etching. 3. The method of manufacturing a bipolar transistor according to claim 1, wherein the first insulating film and the second insulating film are made of different materials. 4. The method of manufacturing a bipolar transistor according to claim 1, wherein the first semiconductor layer is polycrystalline.