JPH0863505A - Model for circuit simulation of field effect transistor - Google Patents

Abstract

PURPOSE: To precisely express the characteristics of a linear area and a saturated area with the actual characteristic of a field effect transistor by containing an exponential function where a second hyperbolic tangent function is set to be a bottom in a first function. CONSTITUTION: CPU 10 executes a control program stored in ROM 11, controls a whole system and executes a circuit simulation program stored in RAM 12. RAM 12 is used as a work area. The result of simulation is stored in a disk device 14, is displayed in a display device 15 after simulation is terminated and is printed and outputted from a printer 16. In a model for the circuit simulation of the field effect transistor in such a case, the first function including the product of the first hyperbolic tangent function, drain voltage and the exponential function where the second hyperbolic tangent function is set to be the bottom is given as the function for expressing a drain voltage/drain current characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulation model of a field effect transistor, and more particularly to a circuit simulation model expressing the drain voltage / drain current characteristics of a field effect transistor as a function.

[0002]

2. Description of the Related Art Conventionally, MESFETs (Metal Semiconductor Field Effect Transistors) have been used as compound semiconductor devices.
sistor) and HEMT [High Electron Mobility Transist
or (= MODFET: Modulation Doped Field Effect
Transistor)] and other field effect transistors (FETs)
There is.

When a large-scale integrated circuit or a high frequency circuit including such a field effect transistor is analyzed by circuit simulation in the time domain and the frequency domain, as a simulation model of the field effect transistor,
Conventionally, the formula (1) is widely used.

Ids (Vds, Vgs) = β (Vgs−V _TO ) ² · tan h (α · VdS) (1) where Ids is the drain-source current, Vds is the drain-source voltage, and Vgs Is the gate-source voltage, V _TO
Is the threshold voltage of the field effect transistor. Also, β,
α is an arbitrary constant.

[0005]

In the conventional equation (1) used in the circuit simulation of the field effect transistor, the saturation voltage parameter α used in the hyperbolic tangent relation (tangent hyperbolic function) is a constant, If the value of α is determined according to the steep rising characteristic of the linear region in the drain voltage / drain current characteristic of the field effect transistor, the characteristic of the shoulder part of the boundary between the linear region and the saturation region is different from the actual field effect transistor. However, there is a problem in that the accuracy deteriorates.

[0006] (1) of claim (Vgs -V _TO) ² value is increased larger the gate voltage Vgs,
This shows that the drain current Ids increases as the gate voltage Vgs increases. But especially HE
In MT, there is a problem that the drain current Ids is saturated as the gate voltage Vgs is increased and cannot be expressed by the conventional method.

[0007] The present invention has been made in view of the above points,
An object of the present invention is to provide a circuit simulation model of a field effect transistor in which the boundary between the linear region and the saturation region accurately approximates the characteristics of the actual field effect transistor and can represent the saturation of drain current due to an increase in gate voltage. To do.

[0008]

According to a first aspect of the present invention, there is provided a circuit simulation model of a field effect transistor for performing circuit simulation by expressing a drain voltage / drain current characteristic of the field effect transistor as a function. As a function expressing the voltage-drain current characteristic, the first function including the product of the first hyperbolic tangent function, the drain voltage, and the exponential function whose base is the second hyperbolic tangent function is provided.

According to a second aspect of the present invention, in the circuit simulation model of the field effect transistor according to the first aspect, the first hyperbolic tangent function has a gate voltage as a variable.

According to a third aspect of the present invention, in the circuit simulation model of the field effect transistor according to the first aspect, the variable of the second hyperbolic tangent function is an exponential function having the drain voltage and the gate voltage as variables. It is a function that contains.

According to a fourth aspect of the present invention, in the circuit simulation model of the field effect transistor according to the first aspect, the characteristic of a region having a small drain current is expressed.
And a fourth function represented by the reciprocal of the sum of the reciprocal of the function of and the reciprocal of the third function that determines the upper limit of the drain current,
The first function is multiplied by the fourth function.

[0012]

According to the first aspect of the invention, since the first function includes the exponential function whose base is the second hyperbolic tangent function, the characteristics of the linear region and the saturation region are compared with those of the actual field effect transistor. Can be expressed accurately.

According to the second aspect of the present invention, since the first hyperbolic tangent function has the gate voltage as a variable, the drain conductance can be accurately expressed.

According to the third aspect of the invention, the variable of the second hyperbolic tangent function includes an exponential function having the drain voltage and the gate voltage as variables, so that the saturation voltage parameter can be accurately expressed.

According to the fourth aspect of the invention, since the fourth function is multiplied by the first function, the second function representing the characteristic of the region where the drain current is small and the third function for determining the upper limit of the drain current are provided. The characteristics of the actual field effect transistor can be represented with high accuracy by approaching both the function and the function.

[0016]

FIG. 2 shows a block diagram of a computer system for implementing the method of the present invention. In the figure, CPU10
Executes the control program stored in the ROM 11 to control the entire system, and executes the circuit simulation program of the method of the present invention stored in the RAM 12.
The RAM 12 is also used as a work area, the result of the simulation is stored in the disk device 14, and after the simulation is finished, it is displayed on the display device 15 and printed out by the printer 16.

In the present invention, the following equation (2) is used to express the drain voltage / drain current characteristics of the field effect transistor. Ids (Vds, Vgs) = Sf. [Idsds (Vds, Vgs) .Idsgs (Vds, Vgs)] (2) In the formula (2), Sf is an arbitrary constant, and Ids
ds (Vds, Vgs) and Idsgs (Vds, Vgs) are (3) and
It is expressed by equation (4). Idsds (Vds, gs) = [1 + Vtl ₁ · λ ₂ {tan h (λ ₃ · Vgs −V _K ) +1} · Vds] × [tan h {Pm (Vds, Vgs) · Vds} ^{afa (Vds , Vgs)} (3)

[0018]

[Equation 1]

Where tan h (λ ₃ · Vgs −V _K ) +1
Is the first hyperbolic tangent function, tan h {Pm (Vds, Vgs) ・ V
ds} is the second hyperbolic tangent function, and equation (3) is the first
In equation (4), the fourth function is.

[0020]

[Equation 2]

[0021]

(Equation 3)

However, V _TO is the threshold value of the field effect transistor, and Vtl ₁ , λ ₂ , λ ₃ , V _K , Idss, ax, axoff, axpm
₁ , axpmds, axpmgs, V _DSOFF , am, aimax, V _TOX , nimax, i
max, cfxi (i = 1,2,3), ng2, sch, Lg, dLg, Lgo, nVtosch, ay,
Vgso, adsx, and nads are arbitrary constants.

The above equation (5) expresses the saturation voltage parameter as a function. Expression (6) is a function (second function) for determining the drain conductance in the vicinity of the origin of the drain voltage / drain current characteristic, that is, in the region where the drain current is small. Expression (7) is a characteristic function (third function) that determines the saturation value of the drain current with respect to the gate voltage. Equation (8) is a function that represents the characteristics near the threshold. The third term on the right side of the equation (9) is a function representing the difference between the gate voltage Vgs and the threshold value V _TO , including shifting the threshold value to the negative side when the drain voltage is increased. The hyperbolic tangent function (danger hyperbolic function) tan h {Pm (Vds, Vgs) · Vds} in Eq.
Instead, by using the exponential function of Eq. (5) with Vds and Vgs as variables, the saturation voltage parameter can be expressed accurately and the characteristics of the shoulder part where the drain voltage / drain current characteristic shifts from the linear region to the saturation region The characteristics of an actual field effect transistor can be accurately approximated. Furthermore, the above function tan
By adding an exponential term afa (Vds, Vgs) to h {Pm (Vds, Vgs) · Vds} to form an exponential function, the accuracy of approximation of the drain voltage / drain current characteristics near the origin is improved.

The characteristic function expressed by the equation (7) is shown by a two-dot chain line in FIG. 3, the function expressed by the equation (8) is shown by a one-dot chain line in FIG. It is the function shown by the solid line in FIG. 3 that is asymptotic to the function. In other words, it is a function that follows the equation (8) near the origin and that follows the characteristic function when it departs from the origin.

By the way, when the drain bias is increased, the threshold value V _T0 of the second term of the equation (9) is substantially shifted to the negative side by the third term of the equation (9), which is obtained.
Since Vtemp (Vds, Vgs) is substituted into the equation (8), it can be expressed that the drain current Ids is saturated when the gate voltage Vgs is increased in the HEMT.

FIG. 1 shows a flowchart of the circuit simulation method of the present invention executed by the CPU 10. In the figure, in step S10, Vds is initialized to 0, and Vgs
Is initialized to 0.1, for example.

Next, in step S12, ad is calculated by the equation (11).
s (Vds) is calculated, and in step S14, fe is calculated from the equation (10).
Calculates r (Vgs). In step S16, according to equation (9)
Vtemp (Vds, Vgs) is calculated, and then, in step S18, fg (Vds, Vg) is calculated by the equation (8) using the above Vtemp (Vds, Vgs).
s) is calculated. Further, in step S20, gg (Vds, Vgs) is calculated by the equation (7).

In the next step S22, step S12,
Using ads (Vds) and fer (Vgs) calculated in S14 (6)
Calculates afa (Vds, Vgs) by calculating the formula. Then, in step S24, Pm (Vds, Vgs) is calculated by the equation (5).
Furthermore, in step S26, Idsgs (Vds, Vgs) is obtained by performing the operation of equation (4) using fg (Vds, Vgs) and gg (Vds, Vgs) calculated in steps S18 and S20.

Next, in step S26,
Idsds (Vds, Vgs) is calculated by performing the calculation of equation (3) using afa (Vds, Vgs) and Pm (Vds, Vgs) calculated in S24. Then, in step S30, the above Idsgs (Vds, Vgs) and Idsds
(2) is calculated using (Vds, Vgs) and Ids (Vds, Vg
s).

Thereafter, in step S32, it is determined whether or not Vds is equal to or more than the final value (for example, 2V). If not, in step S34, Vds is set to a predetermined value (for example, 0.1V).
Only, the process proceeds to step S12, and steps S12 to S32 are repeated. Also, in step S32, Vd
If s is equal to or larger than the final value, it is determined in step S36 whether Vgs is equal to or larger than the final value (for example, 0.8 V). Here, if Vgs is not the final value or more, Vds in step S38
Is initialized and Vgs is increased by a predetermined value (for example, 0.1 V), and the process proceeds to step S12.
Repeat S36. If Vgs is greater than or equal to the final value in step S36, this process ends.

When the circuit simulation of the MESFET is performed by the method of the present invention, the drain voltage / drain current characteristics shown by the solid line in FIG. 4 are obtained. On the other hand, the conventional method has the drain voltage / drain current characteristics shown by the broken line. The actual measurement data of this MESFET is shown on the solid line as indicated by the black circles, and the conventional method indicated by the broken line has a large error at the shoulder of the boundary between the linear region and the saturated region, but hardly causes the error.

[0032]

As described above, according to the first aspect of the present invention, since the first function includes the exponential function whose base is the second hyperbolic tangent function, the characteristics of the linear region and the saturation region are actually realized. The characteristics of the field effect transistor can be accurately expressed.

According to the second aspect of the invention, since the first hyperbolic tangent function has the gate voltage as a variable, the drain conductance can be accurately expressed.

According to the third aspect of the invention, since the variable of the second hyperbolic tangent function includes an exponential function having the drain voltage and the gate voltage as variables, the saturation voltage parameter can be accurately expressed.

Further, according to the invention of claim 4, since the fourth function is multiplied by the first function, the upper limit of the drain current and the second function representing the characteristic of the region where the drain current is small are determined. It is asymptotic to both the third function and the actual characteristics of the field effect transistor with high accuracy, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a flowchart of a simulation using a model of the present invention.

FIG. 2 is a block diagram of a computer system for carrying out a simulation using the model of the present invention.

FIG. 3 is a diagram for explaining a model of the present invention.

FIG. 4 is a characteristic diagram of simulation results by the model of the present invention and the conventional model.

[Explanation of symbols]

 10 CPU 11 ROM 12 RAM 14 Disk Device 15 Display Device 16 Printer

Claims (4)

[Claims] 1. A drain voltage of a field effect transistor
In the circuit simulation model of the field effect transistor for performing the circuit simulation by expressing the drain current characteristic as a function, the first hyperbolic tangent function, the drain voltage, and the second
First including the product of the hyperbolic tangent function of and the exponential function
A circuit simulation model of a field-effect transistor having a function of. 2. The circuit simulation model of a field effect transistor according to claim 1, wherein the first hyperbolic tangent function has a gate voltage as a variable. 3. The circuit simulation model of a field effect transistor according to claim 1, wherein the variable of the second hyperbolic tangent function is a function including an exponential function having a drain voltage and a gate voltage as variables. A model for circuit simulation of a field effect transistor. 4. The circuit simulation model of the field effect transistor according to claim 1, wherein a reciprocal of a second function that represents the characteristics of a region having a small drain current and a reciprocal of a third function that determines an upper limit of the drain current. A circuit simulation model of a field effect transistor, comprising a fourth function represented by the reciprocal of a sum, wherein the first function is multiplied by the fourth function.