JPH0832436A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation with low power consumption by employing a current mirror type circuit for a load circuit and providing a clamp circuit to keep an output signal amplitude constant even when a current is changed during the operation. CONSTITUTION:P-channel MOSFETs MP1, MP2 in current mirror connection are provided in a load circuit of an emitter coupled logic circuit selecting a current based on an input signal voltage to process the signal and a clamp circuit controlling an output signal amplitude is provided. Furthermore, a function selecting any of plural currents as a switched current during the circuit operation is provided. That is, a larger current is supplied for a period of signal processing and a smaller current is supplied for a period not directly relating to the signal processing or a circuit whose operating speed requires no faster speed. Thus, the logic circuit operated at a high speed with low power consumption is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which processes information at high speed.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit required to operate at high speed, an emitter couple logic circuit (hereinafter referred to as an ECL circuit)
Is used. The ECL circuit operates at the highest speed among semiconductor circuits. However, this circuit is a circuit that continues to flow a constant current and switches the constant current with an input signal to detect a signal or take a logic. The operation in which it is essential to keep the constant current flowing is because the ECL circuit uses a resistor as a load.

That is, when the current value is changed, the resistance value of the load is set so that a signal amplitude corresponding to the value is generated. Therefore, it is necessary that the product of the current value and the load resistance is constant. Power consumption is constant whether or not signal processing is required. Therefore, in highly integrated circuits, the current value of this constant current is reduced in order to reduce power consumption. As the current value decreases, the load charging / discharging time increases, and the characteristics of high-speed operation are lost. Already
A large amount of current is distributed to a circuit with a large load to reduce the time required to charge and discharge the load. But,
According to this method, a large current continues to flow in the circuit having a large current value, and a significant reduction in power consumption cannot be achieved.

P-type MOSFET for bipolar differential amplifier
A circuit using the current mirror circuit has been already reported (NTT R & D Vol.41 pp.105.
7-1056). However, this circuit does not have a clamp function for limiting a signal, which is a main component of the present invention, or a function for changing a current during circuit operation.

Further, in a CMOS circuit, a source-coupled differential amplifier in which a P-type MOSFET is connected in a current mirror is used for signal detection. Some of these circuits have the ability to interrupt the current when it is not necessary to process the signal. However, it does not include the function of limiting the amplitude of a signal, which is a main component of the present invention, and the function of keeping a slight amount of current flowing even when no signal processing is performed.

[0006]

The operation in which it is essential to keep a constant current flowing as described above is based on the use of a resistor as a load in the ECL circuit. Since the resistance value of the load is set so that a signal amplitude corresponding to the current value is generated when the current value is changed, it is necessary that the product of the current value and the load resistance is constant. That is, in order to keep the signal amplitude constant, it is required to manufacture the current value and the resistance value flowing in the ECL circuit with high accuracy, and it is considered that the manufacturing is difficult.

Although it is possible to switch the current by changing the resistance value in the conventional ECL circuit, this method requires a timing design for making the switching time of the resistance value and the switching time of the current coincide with each other.

Further, when an attempt is made to apply a differential amplifier having a conventional current mirror load circuit that does not limit the output signal amplitude to a logic circuit, the collector potential drops too much, the bipolar transistor enters the saturated operation region, and the operation speed is increased. In addition, the signal amplitude decreases and the time required for charging and discharging the load capacitance increases.

Further, the ECL circuit has a drawback that the area occupied by the circuit is large. Achieving an occupation area comparable to that of a CMO logic circuit is also a problem.

[0010]

The present invention provides such an EC
The disadvantage of the L circuit is that the current mirror type circuit is used as the load circuit, the clamp circuit is provided, and the output signal amplitude is held constant even if the current is changed during the operation, thereby eliminating the need for timing design.

The reduction of the circuit occupation area is achieved by using the SOI technique for reducing the isolation region of the device.

[0012]

According to the circuit of the present invention, a large current can be made to flow during signal processing, and a small current can be made to flow in a circuit not directly involved in signal processing or a circuit whose operating speed may be slow. This enabled the realization of a logic circuit with low power consumption and high speed operation.

[0013]

1 is a circuit diagram of the present invention. Q1 to Q3
Is a bipolar transistor, the emitters of Q1 to Q3 are connected to the drain terminal 33 of the N-type MOSFET MN1 to which the voltage Vcs is supplied, and a predetermined current Ics (not shown)
Is supplied. IN1 and IN2 are signal input terminals and VRE
F is the reference voltage of the input signal. When either IN1 or IN2 exceeds the voltage of VREF, the current Ics becomes the terminal 31.
Comes to flow.

A P-type M diode-connected to the terminal 31
There is an OSFET MP1, and a current Ics flows. At this time, the potential of the terminal 31 is the gate potential required to flow the current Ics. A current equal to the current Ics also flows through the P-type MOSFET MP2. However, since Q3 is in the cutoff state, the current supplied from MP2 is applied to raise the potential of the terminal OUT, and the potential of the terminal OUT is raised to the ground potential. That is, in this input state, the output potential becomes the ground potential.

This output potential is independent of the current supplied by MN1 unless Q3 is in the cutoff state and no current is drawn from the output terminal OUT. IN from this state
When both potentials of 1 and IN2 become lower than the reference potential VREF, Q1 and Q2 are cut off, and no current flows to MP1. For this reason, the gate voltage also decreases, and M
P2 is also in the cutoff state. On the other hand, Q3 conducts to draw a current from the output terminal OUT and drop the potential.

The potential of the terminal OUT is clamped by the diode D1 and the low level of the output signal is determined. Even in this state, the low level of the output is determined by the forward voltage of the diode and does not depend on the current of MN1.

As is apparent from the above operation, the circuit of FIG. 1 shows that the signal amplitude does not change with the current supplied by MN1. That is, it can be seen that the supply current is for charging and discharging the parasitic capacitance of the output terminal when the output signal is switched, and it is not necessary to flow a large amount of current after this operation is completed. Further, since the low level of the signal does not change even if the current changes as compared with the conventional ECL circuit in which the low level of the signal changes due to the current, it is not necessary to set the current strictly. Rather, taking advantage of this feature, it is possible to improve the operating speed by supplying a slightly larger current during the period when the signal changes.

When the load is large, the operating speed is improved by adding the transistor Q4 of the emitter follower as shown in the circuit diagram of FIG. MN2 of this circuit is Q
4 is a device for supplying a predetermined current to the MN
The current is switched as in 1.

The ECL circuit is said to operate effectively at a higher speed than the NAND circuit or the NOR circuit of the CMOS circuit because it can obtain the logical outputs of NOR and OR. In the circuits of FIGS. 1 and 2, only the OR output can be obtained. On the other hand, the circuit of FIG. 3 can be used to form a NOR output circuit. This requires twice as many devices as the ECL circuit, but since the signals are processed in parallel, an operating speed equivalent to that of the ECL circuit can be obtained. Further, since the circuit of FIG. 2 is provided with the emitter follower circuit, it is also provided with the wired OR logic function, and the logic capability is ECL.
It is equivalent to a circuit.

By applying this circuit to the conventional ECL circuit, the power consumption is reduced to about 1/4. About 30 devices
%, But the overall increase was only about 10% due to the large signal wiring area.

FIG. 4 is a view showing the structure of a device and its arrangement suitable for manufacturing the circuit of the present invention. The bipolar transistor is shown in the left half, the P-type MOSFET is shown in the right half, the sectional structure is shown in the upper part, and the planar structure is shown in the lower part.
A device is manufactured on a silicon film 3 (SOI: Silicon on Insulator) provided on the oxide film 2 in order to reduce the isolation region 12 between the bipolar transistors and the P-type MOSFET. As a result, the isolation region 12 between elements is reduced, and the collectors 3 and 15 and the drain 21 are removed.
The parasitic capacitance attached to the device has been reduced and the speed has been further increased. Hereinafter, description will be given with reference to sectional views according to the manufacturing process shown in FIG.

FIG. 5A shows an SOI substrate. A silicon substrate 1 has an oxide film 2 formed thereon with a thickness of about 400 nm. Further, a silicon single crystal film 3 is formed thereon with a thickness of about 200 nm. The SOI substrate having this structure is available by being manufactured by a bonding method or an ion implantation method.

In FIG. 5B, after forming the isolation trench 12 between devices, an oxide film 4 of about 5 nm is formed in the P-type MOSFET region, and a polycrystalline silicon film (shown by wave hatching) and oxidation are formed on the entire surface. A cross-sectional structure is shown when a film (indicated by a white space) is deposited and processing for leaving both films of the gate region 5 and the base region 6 is performed.

In FIG. 5C, an oxide film is formed on the side wall of the polycrystalline silicon film by the self-alignment method, and the collector 9 and the base 5 and the emitter 7 are selectively formed in the bipolar transistor region.
And the drain 21 and the source 24 are both formed in the P-type MOSFET region.
Both regions are formed by self-alignment using the polycrystalline silicon films 5 and 6 and their side wall oxide films as ion implantation masks. Further, the source 24 of the P-type MOSFET is provided with an N-type region 27 formed by diffusion self-alignment. Since these self-alignment methods are techniques used for manufacturing integrated circuits, description thereof will be omitted.

An electrode mounting hole is provided in the structure of FIG.
The electrodes 4, 8, 22, and 26 are formed to complete the device structure shown in FIG.

The device having the structure shown in FIG. 4 has the following characteristics.

(1) Since the collector of the bipolar transistor is formed in self-alignment with the base, and the width of the polycrystalline silicon film can be processed to 0.2 μm or less in recent microfabrication, the high concentration region from the emitter region to the collector is formed. Can be accurately formed to a very small value such as 0.3 micron or less, and collector resistance can be reduced. Also,
Since it is formed on a thin SOI substrate, the parasitic capacitance of the collector becomes small. Furthermore, since the base region is formed with the minimum processing size, the parasitic capacitance of the base can be reduced. The increase in base resistance due to the narrow width of the polycrystalline silicon serving as the base electrode can be reduced by siliciding the polycrystalline silicon film or forming a multi-layer structure of the polycrystalline silicon film and the silicide film. It can be said that the best structure is a multi-layered film of the polycrystalline silicon film and the silicide film.

(2) Since the source region of the P-type MOSFET is formed by diffusion self-alignment and the substrate is connected to the source electrode, the controllability of electrical characteristics which is the same as that of the conventional MOSFET can be obtained even in the SOI structure. In addition, in this structure, the parasitic capacitance of the drain and source is reduced, and
The high frequency characteristics of are improved.

(3) Since the devices are formed on a thin SOI substrate, the separation between the devices is complete, the influence of the potential of the power supply wiring and the like is eliminated, and the influence of external noise such as α rays is also reduced. It became more stable.
Further, by narrowing the isolation region, the area required for isolation was reduced, and the integration degree was improved and the occupied area was reduced.

FIG. 6 shows a structure in which the depth of both the base and emitter regions of the bipolar transistor having the structure shown in FIG. 4 is increased to reach the oxide film 2. When a device is manufactured in this structure, the contact area between the base region and the emitter region is limited to the side wall of the emitter region, so that the capacitance between the emitter and the base becomes extremely small. Also, the capacity between the collector and the base was reduced.

In the above embodiments, the combination circuit of the NPN bipolar transistor and the P-type MOSFET has been described, but the PNP bipolar transistor and the N-type MOSFE are described.
The combinational circuit with T shows similar characteristics. Also, the same effect can be obtained by replacing the bipolar transistor with a MOSFET. Replacing the bipolar transistor with an N-type MOSFET further facilitates device isolation, so that an increase in area can be reduced without applying SOI technology.

[0032]

An ECL circuit having a current mirror circuit as a load is used for a circuit requiring high-speed operation, and high-speed operation is achieved by increasing the current value during a period required for high-speed operation. The power consumption was reduced correspondingly by lowering the current value during the period that does not affect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is an explanatory diagram showing structures of a bipolar transistor and a P-type MOSFET suitable for the logic circuit of the present invention.

FIG. 5 is a sectional view of a main manufacturing process of a bipolar transistor and a P-type MOSFET suitable for the logic circuit of the present invention.

FIG. 6 is an explanatory diagram showing another structure of a bipolar transistor and a P-type MOSFET suitable for the logic circuit of the present invention.

[Explanation of symbols]

Q1-Q3 ... Bipolar transistor, D1 ... Diode, MP1, MP2 ... P-type MOSFET, MN1 ... N-type MOSFET.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 17/567 19/086

Claims (2)

[Claims] 1. A P-type MOSFET connected in a current mirror to a load of a logic circuit that switches a current with an input signal voltage to process a signal, and the value of the switched current has a plurality of values during circuit operation. A semiconductor integrated circuit characterized by switching to a current value. 2. A P-type MOSFET current-mirror connected to a load of a logic circuit that processes a signal by switching a current with an input signal voltage, and has a function of limiting an output signal amplitude, and A semiconductor integrated circuit characterized in that the value of the current to be switched is switched to a plurality of current values during circuit operation.