JPH0829472A - Method for checking conformity of signal line - Google Patents
Method for checking conformity of signal lineInfo
- Publication number
- JPH0829472A JPH0829472A JP6165043A JP16504394A JPH0829472A JP H0829472 A JPH0829472 A JP H0829472A JP 6165043 A JP6165043 A JP 6165043A JP 16504394 A JP16504394 A JP 16504394A JP H0829472 A JPH0829472 A JP H0829472A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- voltage
- semiconductor
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は信号配線の良否検査方法
に係り、特に、半導体集積回路を実装する回路基板上に
設けられた信号配線の良否検査方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal wiring quality inspection method, and more particularly to a signal wiring quality inspection method provided on a circuit board on which a semiconductor integrated circuit is mounted.
【0002】[0002]
【従来の技術】従来より、半導体集積回路などが実装さ
れた回路基板に設けられた信号配線の良否検査を行う場
合には、検査しようとする回路基板上の信号配線各部,
電源端子,接地端子のそれぞれにスプリングピンなどの
導電性の針を立てておき、インサーキットテスタなどを
用いて各々のピン間の抵抗値を測定することで、信号配
線各部における断線や短絡の有無を判定する、というの
が一般的であったが、近年では、回路基板の高密度化と
ともにスプリングピンを立てるスペースの確保が困難と
なってきたため、スプリングピンを使わずに信号配線の
良否検査を容易に行う手法として、バウンダリ・スキャ
ン(IEEE標準1149.1)が利用される機会が増加しつつあ
る。2. Description of the Related Art Conventionally, when conducting a pass / fail inspection of a signal wiring provided on a circuit board on which a semiconductor integrated circuit or the like is mounted, each portion of the signal wiring on the circuit board to be inspected,
Whether there is a disconnection or short circuit in each part of the signal wiring by setting a conductive needle such as a spring pin on each of the power supply terminal and ground terminal and measuring the resistance value between each pin using an in-circuit tester etc. In general, it has become difficult to secure a space for erecting spring pins with the increase in density of circuit boards in recent years, so it is necessary to inspect the quality of signal wiring without using spring pins. Boundary scan (IEEE Std 1149.1) is increasingly being used as an easy method.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、上述し
たバウンダリ・スキャンによる信号配線の良否検査方法
は、あらかじめ半導体集積回路に内蔵されているテスト
用回路を利用する検査方法であり、検査を実施するため
にはこのテスト用回路に対して給電しなければならな
い。すなわち、実際には検査対象である回路基板を通し
て半導体集積回路内のテスト用回路に給電しなければな
らないので、回路基板に設けられた信号配線と電源端子
または接地端子との間に短絡があった場合には、実装さ
れた半導体集積回路を破壊してしまう危険性が大きいと
いう問題点があった。However, the above-described method of inspecting the quality of the signal wiring by the boundary scan is an inspection method utilizing a test circuit built in the semiconductor integrated circuit in advance, and is used for performing the inspection. Must supply power to this test circuit. That is, since it is actually necessary to supply power to the test circuit in the semiconductor integrated circuit through the circuit board to be inspected, there is a short circuit between the signal wiring provided on the circuit board and the power supply terminal or the ground terminal. In this case, there is a risk that the mounted semiconductor integrated circuit may be destroyed.
【0004】したがって本発明の目的は、上記の問題点
を解決して、回路基板に設けられた信号配線と電源端子
または接地端子との間における短絡の有無を、実装され
ている半導体集積回路を破壊することなく、容易に検出
することのできる信号配線の良否検査方法を提供するこ
とにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and to detect the presence or absence of a short circuit between a signal wiring provided on a circuit board and a power supply terminal or a ground terminal in a mounted semiconductor integrated circuit. An object of the present invention is to provide a quality inspection method of a signal wiring which can be easily detected without being destroyed.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
め、本発明の信号配線の良否検査方法は、半導体集積回
路を構成するすべての半導体回路について、前記半導体
回路が遮断状態を維持する検査用電圧と、前記半導体回
路の遮断電流を満足する制限電流とを有する電源・接地
短絡検出用電圧源を用いて、前記半導体集積回路の電源
端子に対して前記検査用電圧を印加するとともに前記半
導体集積回路が実装された回路基板上に設けられた信号
配線の終端部における電圧の有無を判定するか、あるい
は、前記終端部に対して前記検査用電圧を印加するとと
もに前記電源端子における電圧の有無を判定することに
より、前記電源端子と前記信号配線との間の短絡検出を
行うものである。In order to achieve the above-mentioned object, a signal wiring quality inspection method according to the present invention is an inspection method for maintaining all semiconductor circuits constituting a semiconductor integrated circuit in a cutoff state. A voltage for power supply / ground short circuit detection having a limiting voltage satisfying a cutoff current of the semiconductor circuit, and applying the test voltage to a power supply terminal of the semiconductor integrated circuit, and the semiconductor. Whether or not there is a voltage at the terminal end of the signal wiring provided on the circuit board on which the integrated circuit is mounted, or whether the inspection voltage is applied to the terminal and the voltage at the power supply terminal is present Is determined to detect a short circuit between the power supply terminal and the signal wiring.
【0006】また、別の方法として例えば、半導体集積
回路を構成するすべての半導体回路について、前記半導
体回路が遮断状態を維持する検査用電圧と、前記半導体
回路の遮断電流を満足する制限電流とを有する電源・接
地短絡検出用電圧源を用いて、前記半導体集積回路が実
装された回路基板上に設けられた信号配線の終端部に対
して前記検査用電圧を印加するとともに接地端子と前記
終端部との間における電流の有無を判定することによ
り、前記接地端子と前記信号配線との間の短絡検出を行
うものである。As another method, for example, for all the semiconductor circuits forming the semiconductor integrated circuit, a test voltage for maintaining the cutoff state of the semiconductor circuit and a limiting current satisfying the cutoff current of the semiconductor circuit are set. Using the power supply / grounding short-circuit detection voltage source that is provided, the inspection voltage is applied to the termination portion of the signal wiring provided on the circuit board on which the semiconductor integrated circuit is mounted, and the ground terminal and the termination portion are provided. By detecting the presence or absence of a current between and, the short circuit between the ground terminal and the signal wiring is detected.
【0007】[0007]
【作用】上記構成に基づく作用を説明する。The operation based on the above configuration will be described.
【0008】本発明の信号配線の良否検査方法では、半
導体集積回路を構成するすべての半導体回路について、
前記半導体回路が遮断状態を維持する検査用電圧と、前
記半導体回路の遮断電流を満足する制限電流とを有する
電源・接地短絡検出用電圧源を用いて、前記半導体集積
回路の電源端子に対して前記検査用電圧を印加するとと
もに前記半導体集積回路が実装された回路基板上に設け
られた信号配線の終端部における電圧の有無を判定する
か、あるいは、前記終端部に対して前記検査用電圧を印
加するとともに前記電源端子における電圧の有無を判定
することにより、前記電源端子と前記信号配線との間の
短絡検出を行うので、電源端子間の短絡によって複数の
電源端子に同時に電圧が印加されてしまったときでも、
実装された半導体回路が遮断状態を維持する検査用電圧
が供給され、半導体回路に損傷が発生することを防止で
きるとともに、終端部で電圧が検出されない場合には短
絡していないことを、一定の電圧が検出される場合には
短絡していることを、それぞれ知ることができる。According to the quality inspection method of the signal wiring of the present invention, for all the semiconductor circuits that constitute the semiconductor integrated circuit,
With respect to the power supply terminal of the semiconductor integrated circuit, using a power supply / ground short-circuit detection voltage source having a test voltage for maintaining the semiconductor circuit in the cutoff state and a limiting current satisfying the cutoff current of the semiconductor circuit. Whether the voltage for inspection is applied and the presence or absence of a voltage at the terminal of the signal wiring provided on the circuit board on which the semiconductor integrated circuit is mounted is determined, or the voltage for inspection is applied to the terminal. Since a short circuit between the power supply terminal and the signal wiring is detected by determining the presence or absence of a voltage at the power supply terminal while applying, a voltage is simultaneously applied to a plurality of power supply terminals due to a short circuit between the power supply terminals. Even when it ’s gone
It is possible to prevent damage to the semiconductor circuit by supplying the inspection voltage that keeps the mounted semiconductor circuit in the cut-off state, and to confirm that there is no short-circuit if no voltage is detected at the terminal end. When the voltage is detected, it can be known that each of them is short-circuited.
【0009】また、別の方法として例えば、半導体集積
回路を構成するすべての半導体回路について、前記半導
体回路が遮断状態を維持する検査用電圧と、前記半導体
回路の遮断電流を満足する制限電流とを有する電源・接
地短絡検出用電圧源を用いて、前記半導体集積回路が実
装された回路基板上に設けられた信号配線の終端部に対
して前記検査用電圧を印加するとともに接地端子と前記
終端部との間における電流の有無を判定することによ
り、前記接地端子と前記信号配線との間の短絡検出を行
うので、電源端子と接地端子との間の短絡によって短絡
電流が流れてしまったときでも、半導体回路の遮断電流
を満足する電流値となるように制限され、短絡部分に発
生する損傷を最小限に抑えることができるとともに、接
地端子と終端部との間に電流が検出されない場合には短
絡していないことを、一定の電流が検出される場合には
短絡していることを、それぞれ知ることができる。As another method, for example, for all the semiconductor circuits forming the semiconductor integrated circuit, a test voltage for maintaining the cutoff state of the semiconductor circuit and a limiting current satisfying the cutoff current of the semiconductor circuit are set. Using the power supply / grounding short-circuit detection voltage source that is provided, the inspection voltage is applied to the termination portion of the signal wiring provided on the circuit board on which the semiconductor integrated circuit is mounted, and the ground terminal and the termination portion are provided. Since a short circuit between the ground terminal and the signal wiring is detected by determining the presence / absence of a current between and, even when a short circuit current flows due to a short circuit between the power supply terminal and the ground terminal. The current value is limited so that the breaking current of the semiconductor circuit is satisfied, and the damage that occurs in the short-circuited part can be minimized, and the ground terminal and the termination part That no current is short-circuited when not detected, if the constant current is detected that is shorted, can be known, respectively.
【0010】[0010]
【実施例】以下、本発明の信号配線の良否検査方法の一
実施例を図面を用いて詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a signal wiring quality inspection method of the present invention will be described in detail below with reference to the drawings.
【0011】図1は、本発明の信号配線の良否検査方法
における半導体集積回路の電源端子と検査対象の信号配
線との間の短絡検出について説明するための回路構成図
である。同図中、1は検査対象の信号配線を有する被試
験回路基板、2および3は被試験回路基板1に実装され
たECL( Emitter-Coupled-Logic)半導体IC、4,
5,6は信号配線、7および8は終端抵抗、9は接地端
子(VCC端子)、10は半導体回路用電源端子(VE
E端子)、11は終端抵抗7および8を介して信号配線
4および5が接続されている信号終端用電源端子(VT
T端子、請求項中の終端部に相当する)である。また、
12は電流制限機能を有する電圧源、13は電圧計、1
5はスイッチである。FIG. 1 is a circuit configuration diagram for explaining detection of a short circuit between a power supply terminal of a semiconductor integrated circuit and a signal wiring to be inspected in the method of inspecting the quality of a signal wiring of the present invention. In the figure, 1 is a circuit board under test having a signal wiring to be inspected, 2 and 3 are ECL (Emitter-Coupled-Logic) semiconductor ICs mounted on the circuit board under test 1, 4,
5, 6 are signal wirings, 7 and 8 are terminating resistors, 9 is a ground terminal (VCC terminal), and 10 is a semiconductor circuit power supply terminal (VE
E terminal), 11 are signal terminating power supply terminals (VT) to which the signal wirings 4 and 5 are connected via terminating resistors 7 and 8.
T terminal, which corresponds to the terminal portion in the claims). Also,
12 is a voltage source having a current limiting function, 13 is a voltmeter, 1
5 is a switch.
【0012】図1において、電圧源12の出力電圧はE
CL半導体IC2および3が遮断状態を維持する範囲の
検査用電圧(e)に、電流制限値は同じく遮断電流を満
足する範囲の制限電流に、あらかじめ設定しておく。そ
して、スイッチ15をオンすると、VEE端子10に対
して検査用電圧(e)が印加されるので、この状態でV
TT端子11における電圧を電圧計13を用いて測定す
る。このとき、信号配線4,5,6とVEE端子10と
の間に短絡がなかった場合には電圧測定結果が0[V]
となるが、短絡があった場合にはVEE端子10に印加
したのと同じ電圧値(e)が測定結果として得られる。
これにより、信号配線と半導体回路用電源端子(VEE
端子)との短絡検査を行うことができる。また、図1中
の電圧源12と電圧計13の位置を入れ替えて、半導体
回路用電源端子(VEE端子)10に検査用電圧(e)
を印加し、信号終端用電源端子(VTT端子)11にお
ける電圧を測定しても、同様の短絡検査を行うことがで
きる。In FIG. 1, the output voltage of the voltage source 12 is E
The CL semiconductor ICs 2 and 3 are set in advance to the inspection voltage (e) in the range where the cutoff state is maintained, and the current limit value is set to the limit current in the range where the cutoff current is also satisfied. Then, when the switch 15 is turned on, the inspection voltage (e) is applied to the VEE terminal 10, so that in this state V
The voltage at the TT terminal 11 is measured using the voltmeter 13. At this time, if there is no short circuit between the signal wirings 4, 5, 6 and the VEE terminal 10, the voltage measurement result is 0 [V].
However, if there is a short circuit, the same voltage value (e) as that applied to the VEE terminal 10 is obtained as the measurement result.
This enables signal wiring and semiconductor circuit power supply terminals (VEE
It is possible to perform a short circuit inspection with the (terminal). Further, the positions of the voltage source 12 and the voltmeter 13 in FIG. 1 are exchanged, and the inspection voltage (e) is applied to the semiconductor circuit power supply terminal (VEE terminal) 10.
The same short-circuit inspection can be performed by applying the voltage and measuring the voltage at the signal terminal power supply terminal (VTT terminal) 11.
【0013】図2は、本発明の信号配線の良否検査方法
における接地端子と検査対象の信号配線との間の短絡検
出について説明するための回路構成図である。同図中、
図1と同一構成部分については同一符号を記し、その説
明を省略する。また、14は電流計である。図2におい
ても、図1と同様に電圧源12の出力電圧はECL半導
体IC2および3が遮断状態を維持する範囲の検査用電
圧(e)に、電流制限値は同じく遮断電流を満足する範
囲の制限電流に、あらかじめ設定しておく。そして、ス
イッチ15をオンすると、VTT端子11に対して検査
用電圧(e)が印加されるので、この状態で接地端子
(VCC端子)9と信号終端用電源端子(VTT端子)
11との間における電流を電流計14を用いて測定す
る。このとき、信号配線4,5,6とVCC端子9との
間に短絡がなかった場合には電流測定結果が0[A]と
なるが、短絡があった場合にはVTT端子11に印加し
た電圧値(e)と終端抵抗値(r:図示なし)で決まる
電流値が測定結果として得られる。これにより、信号配
線と接地端子(VCC端子)との短絡検査を行うことが
できる。FIG. 2 is a circuit configuration diagram for explaining detection of a short circuit between the ground terminal and the signal wiring to be inspected in the signal wiring quality inspection method of the present invention. In the figure,
The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Further, 14 is an ammeter. Also in FIG. 2, as in FIG. 1, the output voltage of the voltage source 12 is the inspection voltage (e) in the range in which the ECL semiconductor ICs 2 and 3 maintain the cutoff state, and the current limit value is in the range that also satisfies the cutoff current. Set the current limit in advance. Then, when the switch 15 is turned on, the inspection voltage (e) is applied to the VTT terminal 11, so in this state, the ground terminal (VCC terminal) 9 and the signal terminating power supply terminal (VTT terminal).
The current between 11 and 11 is measured using the ammeter 14. At this time, when there is no short circuit between the signal wirings 4, 5, 6 and the VCC terminal 9, the current measurement result is 0 [A], but when there is a short circuit, it is applied to the VTT terminal 11. A current value determined by the voltage value (e) and the termination resistance value (r: not shown) is obtained as the measurement result. Accordingly, it is possible to perform a short circuit inspection between the signal wiring and the ground terminal (VCC terminal).
【0014】以上のように本実施例によれば、信号配線
4,5,6の終端部である信号終端用電源端子(VTT
端子)11,半導体回路用電源端子(VEE端子)1
0,接地端子(VCC端子)9の3個所を測定系に接続
するだけで、すべての信号配線と半導体回路用電源端子
(VEE端子)10または接地端子(VCC端子)9と
の間の短絡の有無を検査することができる。また、電圧
源12の出力電圧はECL半導体IC2および3が遮断
状態を維持する範囲の検査用電圧(e)に、電流制限値
は同じく遮断電流を満足する範囲の制限電流に、あらか
じめ設定されているので、半導体回路の回り込みなどに
よる誤判定を防止するとともに、信号配線とVEE端子
10またはVCC端子9との間に短絡があった場合で
も、実装されているECL半導体ICや被試験回路基板
の損傷を防止することができる。As described above, according to this embodiment, the signal terminal power supply terminal (VTT) which is the terminal portion of the signal wirings 4, 5, and 6.
Terminal) 11, power supply terminal for semiconductor circuit (VEE terminal) 1
0, the ground terminal (VCC terminal) 9 is connected to the measurement system by simply connecting all the signal wiring and the semiconductor circuit power supply terminal (VEE terminal) 10 or the ground terminal (VCC terminal) 9 The presence or absence can be inspected. Further, the output voltage of the voltage source 12 is preset to the inspection voltage (e) in the range in which the ECL semiconductor ICs 2 and 3 maintain the cutoff state, and the current limit value is preset to the limited current in the range to satisfy the cutoff current. Therefore, erroneous determination due to wraparound of the semiconductor circuit is prevented, and even when there is a short circuit between the signal wiring and the VEE terminal 10 or the VCC terminal 9, the mounted ECL semiconductor IC or the circuit board under test is Damage can be prevented.
【0015】なお、本実施例では短絡の有無を判定する
ために電圧計および電流計を用いたが、電圧または電流
の有無のみを検出する閾値判定のみが可能なものを用い
て短絡の有無を判定してもよい。In this embodiment, the voltmeter and the ammeter are used to determine the presence or absence of a short circuit. However, the presence or absence of a short circuit can be determined by using a device that can only determine the threshold value that detects only the presence or absence of voltage or current. You may judge.
【0016】[0016]
【発明の効果】以上詳しく説明したように、本発明の信
号配線の良否検査方法によれば、半導体集積回路を構成
するすべての半導体回路について、前記半導体回路が遮
断状態を維持する検査用電圧と、前記半導体回路の遮断
電流を満足する制限電流とを有する電源・接地短絡検出
用電圧源を用いて、前記半導体集積回路の電源端子に対
して前記検査用電圧を印加するとともに前記半導体集積
回路が実装された回路基板上に設けられた信号配線の終
端部における電圧の有無を判定するか、あるいは、前記
終端部に対して前記検査用電圧を印加するとともに前記
電源端子における電圧の有無を判定することにより、前
記電源端子と前記信号配線との間の短絡検出を行うの
で、電源端子間の短絡によって複数の電源端子に同時に
電圧が印加されてしまったときでも、実装された半導体
回路が遮断状態を維持する検査用電圧が供給され、半導
体回路に損傷が発生することを防止できるとともに、終
端部で電圧が検出されない場合には短絡していないこと
を、一定の電圧が検出される場合には短絡していること
を、それぞれ知ることができるという効果が得られる。As described above in detail, according to the quality inspection method of the signal wiring of the present invention, for all the semiconductor circuits constituting the semiconductor integrated circuit, the inspection voltage for keeping the semiconductor circuit in the cutoff state and A power supply / ground short-circuit detection voltage source having a limiting current satisfying a cut-off current of the semiconductor circuit, and applying the inspection voltage to a power supply terminal of the semiconductor integrated circuit, and The presence or absence of a voltage at the terminal end of the signal wiring provided on the mounted circuit board is determined, or the presence or absence of the voltage at the power supply terminal is determined by applying the inspection voltage to the terminal end. By doing so, a short circuit between the power supply terminal and the signal wiring is detected, so that a voltage is simultaneously applied to a plurality of power supply terminals due to a short circuit between the power supply terminals. Even when the semiconductor circuit is mounted, the inspection voltage that keeps the mounted semiconductor circuit off is supplied, preventing damage to the semiconductor circuit and not causing a short circuit if no voltage is detected at the terminal end. Therefore, when a constant voltage is detected, it is possible to know that each is short-circuited.
【0017】また、別の方法として例えば、半導体集積
回路を構成するすべての半導体回路について、前記半導
体回路が遮断状態を維持する検査用電圧と、前記半導体
回路の遮断電流を満足する制限電流とを有する電源・接
地短絡検出用電圧源を用いて、前記半導体集積回路が実
装された回路基板上に設けられた信号配線の終端部に対
して前記検査用電圧を印加するとともに接地端子と前記
終端部との間における電流の有無を判定することによ
り、前記接地端子と前記信号配線との間の短絡検出を行
うので、電源端子と接地端子との間の短絡によって短絡
電流が流れてしまったときでも、半導体回路の遮断電流
を満足する電流値となるように制限され、短絡部分に発
生する損傷を最小限に抑えることができるとともに、接
地端子と終端部との間に電流が検出されない場合には短
絡していないことを、一定の電流が検出される場合には
短絡していることを、それぞれ知ることができるという
効果が得られる。As another method, for example, for all the semiconductor circuits forming the semiconductor integrated circuit, a test voltage for maintaining the cutoff state of the semiconductor circuit and a limiting current satisfying the cutoff current of the semiconductor circuit are set. Using the power supply / grounding short-circuit detection voltage source that is provided, the inspection voltage is applied to the termination portion of the signal wiring provided on the circuit board on which the semiconductor integrated circuit is mounted, and the ground terminal and the termination portion are provided. Since a short circuit between the ground terminal and the signal wiring is detected by determining the presence / absence of a current between and, even when a short circuit current flows due to a short circuit between the power supply terminal and the ground terminal. The current value is limited so that the breaking current of the semiconductor circuit is satisfied, and the damage that occurs in the short-circuited part can be minimized, and the ground terminal and the termination part That no current is short-circuited if not detected, that it is short-circuited when the constant current is detected, the effect that it is possible to know each obtained.
【図1】本発明の信号配線の良否検査方法における半導
体集積回路の電源端子と検査対象の信号配線との間の短
絡検出について説明するための回路構成図である。FIG. 1 is a circuit configuration diagram for explaining detection of a short circuit between a power supply terminal of a semiconductor integrated circuit and a signal wiring to be inspected in a signal wiring quality inspection method of the present invention.
【図2】本発明の信号配線の良否検査方法における接地
端子と検査対象の信号配線との間の短絡検出について説
明するための回路構成図である。FIG. 2 is a circuit configuration diagram for explaining detection of a short circuit between a ground terminal and a signal wiring to be inspected in the signal wiring quality inspection method of the present invention.
1 被試験回路基板 2,3 ECL半導体IC 4,5,6 信号配線 7,8 終端抵抗 9 接地端子(VCC) 10 半導体回路用電源端子(VEE) 11 信号終端用電源端子(VTT) 12 電圧源 13 電圧計 14 電流計 15 スイッチ 1 circuit board under test 2, 3 ECL semiconductor IC 4, 5, 6 signal wiring 7, 8 termination resistor 9 ground terminal (VCC) 10 power supply terminal for semiconductor circuit (VEE) 11 power supply terminal for signal termination (VTT) 12 voltage source 13 Voltmeter 14 Ammeter 15 Switch
Claims (1)
体回路について、前記半導体回路が遮断状態を維持する
検査用電圧と、前記半導体回路の遮断電流を満足する制
限電流とを有する電源・接地短絡検出用電圧源を用い
て、 前記半導体集積回路の電源端子に対して前記検査用電圧
を印加するとともに前記半導体集積回路が実装された回
路基板上に設けられた信号配線の終端部における電圧の
有無を判定するか、あるいは、前記終端部に対して前記
検査用電圧を印加するとともに前記電源端子における電
圧の有無を判定することにより、前記電源端子と前記信
号配線との間の短絡検出を行うことを特徴とする信号配
線の良否検査方法。1. A power supply / ground short-circuit detection circuit for all semiconductor circuits constituting a semiconductor integrated circuit, having a test voltage for maintaining the cutoff state of the semiconductor circuit and a limiting current satisfying a cutoff current of the semiconductor circuit. A voltage source for applying the inspection voltage to the power supply terminal of the semiconductor integrated circuit, and checking the presence / absence of a voltage at the terminal end of the signal wiring provided on the circuit board on which the semiconductor integrated circuit is mounted. It is possible to detect a short circuit between the power supply terminal and the signal wiring by judging or by applying the inspection voltage to the terminal portion and judging the presence or absence of the voltage at the power supply terminal. A characteristic inspection method for signal wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6165043A JPH0829472A (en) | 1994-07-18 | 1994-07-18 | Method for checking conformity of signal line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6165043A JPH0829472A (en) | 1994-07-18 | 1994-07-18 | Method for checking conformity of signal line |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0829472A true JPH0829472A (en) | 1996-02-02 |
Family
ID=15804755
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6165043A Pending JPH0829472A (en) | 1994-07-18 | 1994-07-18 | Method for checking conformity of signal line |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0829472A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006053006A (en) * | 2004-08-11 | 2006-02-23 | Tempearl Ind Co Ltd | Method and apparatus for checking wiring connection of earthing-type wall socket |
-
1994
- 1994-07-18 JP JP6165043A patent/JPH0829472A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006053006A (en) * | 2004-08-11 | 2006-02-23 | Tempearl Ind Co Ltd | Method and apparatus for checking wiring connection of earthing-type wall socket |
JP4500130B2 (en) * | 2004-08-11 | 2010-07-14 | テンパール工業株式会社 | Method and apparatus for checking wiring connection of outlet with ground electrode |
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