JPH08236549A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH08236549A
JPH08236549A JP7041469A JP4146995A JPH08236549A JP H08236549 A JPH08236549 A JP H08236549A JP 7041469 A JP7041469 A JP 7041469A JP 4146995 A JP4146995 A JP 4146995A JP H08236549 A JPH08236549 A JP H08236549A
Authority
JP
Japan
Prior art keywords
terminal
conductive
surge
circuit
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7041469A
Other languages
Japanese (ja)
Inventor
Masahiro Akiyama
正博 秋山
Nagayasu Yamagishi
長保 山岸
Aotake Kou
青竹 高
Takashi Ueda
孝 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP7041469A priority Critical patent/JPH08236549A/en
Publication of JPH08236549A publication Critical patent/JPH08236549A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To prevent a surge from intruding into an electronic circuit by a method wherein a first conductive region, which is formed between the circuit and an input/output terminal, and a second conductive region, which is formed between the circuit and a power terminal, are monolithically integrated so that the withstand voltages of the first and second conductive regions to a conductive substrate are made lower than that of the circuit. CONSTITUTION: A semi-insulative crystal layer 2 is grown on a conductive substrate 1, an electronic circuit 3 is formed in the layer 2 and an input/output terminal 4 and a power terminal 5 are provided. Moreover, a conductive region 6 is formed between the terminal 4 and the circuit 3 and a conductive region 7 is formed between an terminal, which is applied a surge through an external terminal, such as the terminal 5, and the circuit 3. The distances (d1 ) and (d2 ) between the substrate 1 and the regions 6 and 7 are selected so that the withstand voltages of the regions 6 and 7 to the substrate 1 are made lower than that of the circuit 3. Thereby, before the circuit 3 is broken or malfunctioned, a current flows between the regions 6 and 7 and the substrate 1 and the surge applied to the terminal can be absorbed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、エンジン・モータの制
御等のサージ電圧が発生する条件下で安定に動作する半
導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which operates stably under conditions such as engine / motor control for which surge voltage is generated.

【0002】[0002]

【従来の技術】従来、このような分野の技術としては、
例えば、「電子技術 1991−5.P.61〜67」
に開示されるものがあった。この文献に示されるよう
に、サージ電圧が発生し、これが回路にかかるような条
件下で使用される電子回路では、サージを吸収するため
に、サージ電圧がかかる電極と接地の間にバリスタを入
れる方法が通常行われている。
2. Description of the Related Art Conventionally, techniques in such a field include:
For example, "Electronic Technology 1991-5.P. 61-67"
Was disclosed in. As shown in this document, in an electronic circuit which is used under conditions where a surge voltage is generated and applied to the circuit, a varistor is inserted between the electrode to which the surge voltage is applied and ground in order to absorb the surge. The method is usually done.

【0003】その場合、バリスタは、ある電圧までは高
抵抗であるが、その電圧を越える電圧が端子間に加わる
と低抵抗となり、サージ電圧を短絡して、回路を保護す
る。また、バリスタの代わりに、同様の特性を有するツ
ェナーダイオードが用いられる場合もある。
In this case, the varistor has a high resistance up to a certain voltage, but when a voltage exceeding that voltage is applied across the terminals, the varistor has a low resistance and short-circuits the surge voltage to protect the circuit. Further, a Zener diode having similar characteristics may be used instead of the varistor.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記し
た従来の方法では、安定にサージ電圧を吸収することが
できるが、保護すべき電子回路に外付けで、そのような
素子を設けなければならず、半導体回路と一体化してモ
ノシリックに集積回路を構成することは困難であった。
However, in the conventional method described above, the surge voltage can be stably absorbed, but such an element must be provided externally to the electronic circuit to be protected. It has been difficult to monolithically form an integrated circuit by integrating with a semiconductor circuit.

【0005】本発明は、上記問題点を除去し、サージ電
圧を吸収することができる機能を内蔵する半導体回路と
一体化してモノシリックに集積される半導体装置を提供
することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above problems and to provide a semiconductor device which is monolithically integrated with a semiconductor circuit having a function capable of absorbing a surge voltage.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体装置において、 (1)導電性基板と、この導電性基板上に成長する半絶
縁性結晶層と、この半絶縁性結晶層に形成される電子回
路と、この電子回路に接続される入出力端子及び電源端
子と、前記電子回路と入出力端子間に形成される第1の
導電領域と、前記電子回路と電源端子間に形成される第
2の導電領域とを設け、前記第1の導電領域及び第2の
導電領域と前記導電性基板間の耐圧を前記電子回路の耐
圧より低くなるようにモノシリックに集積するようにし
たものである。
In order to achieve the above object, the present invention provides a semiconductor device comprising: (1) a conductive substrate; a semi-insulating crystal layer grown on the conductive substrate; An electronic circuit formed in the insulating crystal layer, an input / output terminal and a power supply terminal connected to the electronic circuit, a first conductive region formed between the electronic circuit and the input / output terminal, and the electronic circuit A second conductive region formed between power supply terminals is provided, and the breakdown voltage between the first conductive region and the second conductive region and the conductive substrate is monolithically integrated so as to be lower than the breakdown voltage of the electronic circuit. It is something that is done.

【0007】(2)導電性基板と、この導電性基板上に
成長する半絶縁性結晶層と、この半絶縁性結晶層に形成
される能動素子と、この能動素子に形成される少なくと
も第1の端子及び第2の端子と、前記能動素子の第1の
端子に接続される第1の導電領域と、前記能動素子と第
2の端子間に形成される第2の導電領域とを設け、前記
第1の導電領域及び第2の導電領域と前記導電性基板間
の耐圧を前記能動素子の耐圧より低くなるようにモノシ
リックに集積するようにしたものである。
(2) A conductive substrate, a semi-insulating crystal layer grown on the conductive substrate, an active element formed on the semi-insulating crystal layer, and at least the first element formed on the active element. And a second terminal, a first conductive region connected to the first terminal of the active element, and a second conductive region formed between the active element and the second terminal, The breakdown voltage between the first and second conductive regions and the conductive substrate is monolithically integrated so as to be lower than the breakdown voltage of the active element.

【0008】(3)上記(1)又は(2)記載の半導体
装置において、前記半絶縁性結晶層の厚さをサージ電圧
に対応させるようにしたものである。 (4)上記(2)記載の半導体装置において、前記能動
素子は電界効果トランジスタであり、第1の導電領域は
ソース又はドレイン、第2の導電領域はドレイン又はソ
ースである。
(3) In the semiconductor device described in (1) or (2) above, the thickness of the semi-insulating crystal layer is adapted to the surge voltage. (4) In the semiconductor device according to (2), the active element is a field effect transistor, the first conductive region is a source or a drain, and the second conductive region is a drain or a source.

【0009】(5)上記(4)記載の半導体装置におい
て、電界効果トランジスタはショットキゲート電界効果
トランジスタである。
(5) In the semiconductor device described in (4) above, the field effect transistor is a Schottky gate field effect transistor.

【0010】[0010]

【作用】[Action]

(1)請求項1記載の半導体装置によれば、電子回路に
加わるサージをチップ内で吸収し、サージの電子回路へ
の侵入を防止するために、電子回路が破壊されず、正常
に動作するだけでなく、サージの吸収回路を集積回路に
外付けする必要がなく、モノシリック集積回路として構
成することができる。
(1) According to the semiconductor device of the first aspect, since the surge applied to the electronic circuit is absorbed in the chip and the surge is prevented from entering the electronic circuit, the electronic circuit is not destroyed and operates normally. In addition, it is not necessary to externally attach the surge absorbing circuit to the integrated circuit, and the surge absorbing circuit can be configured as a monolithic integrated circuit.

【0011】また、サージを吸収する導電領域と基板の
距離を制御するのみで、容易に種々のサージ電圧に対応
する半導体装置を構成することができる。 (2)請求項2記載の半導体装置によれば、集積回路を
構成する能動素子自体にサージ耐性をもたせることがで
きるため、集積回路の外部にサージ対策を施す必要がな
く、モノシリックに集積化したサージ耐性を有する半導
体装置を構成することができる。
Further, by only controlling the distance between the conductive region that absorbs the surge and the substrate, it is possible to easily construct a semiconductor device that can cope with various surge voltages. (2) According to the semiconductor device of the second aspect, since the active element itself forming the integrated circuit can be provided with surge resistance, it is not necessary to take a surge countermeasure outside the integrated circuit, and the integrated circuit is monolithically integrated. A semiconductor device having surge resistance can be configured.

【0012】[0012]

【実施例】以下、本発明の実施例を図面を参照しながら
説明する。図1は本発明の第1実施例を示すサージ吸収
機能を有する半導体装置の断面図である。この図に示す
ように、導電性基板1上に半絶縁性結晶層2を成長さ
せ、その半絶縁性結晶層2に電子回路3を形成する。そ
して、入力端子又は出力端子4、電源端子5等の外部か
らサージが加わる端子とを設け、入力端子又は出力端子
4と電子回路3の間に導電領域6、電源端子5等の外部
からサージが加わる端子と電子回路3の間に導電領域7
を形成して、各端子と電気的に接続する。この導電領域
6又は7は、導電性の結晶で形成してもよいし、また金
属で形成してもよい。
Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a semiconductor device having a surge absorbing function according to a first embodiment of the present invention. As shown in this figure, a semi-insulating crystal layer 2 is grown on a conductive substrate 1, and an electronic circuit 3 is formed on the semi-insulating crystal layer 2. Then, a terminal to which a surge is applied from the outside such as the input terminal or the output terminal 4 and the power supply terminal 5 is provided, and a surge is applied from the outside such as the conductive region 6 and the power supply terminal 5 between the input terminal or the output terminal 4 and the electronic circuit 3. A conductive area 7 is provided between the applied terminal and the electronic circuit 3.
Are formed and electrically connected to each terminal. The conductive region 6 or 7 may be formed of a conductive crystal or a metal.

【0013】そして、導電領域6又は7と導電性基板1
の耐圧の値を、それぞれの端子が接続する電子回路の耐
圧よりも低くなるように、導電性基板1と導電領域6又
は7との距離d1 又はd2 を選ぶ。半絶縁性結晶として
GaAs、導電性基板としてn型GaAs基板を例にと
ると、d1 、d2 が1μmに対して、導電領域6又は7
と導電性基板1の間の耐圧は約20V程度となる。この
場合、導電性基板1は基本的には接地して使用する。
Then, the conductive region 6 or 7 and the conductive substrate 1
The distance d 1 or d 2 between the conductive substrate 1 and the conductive region 6 or 7 is selected so that the withstand voltage value is lower than the withstand voltage of the electronic circuit to which each terminal is connected. Taking GaAs as a semi-insulating crystal and an n-type GaAs substrate as a conductive substrate, for example, the conductive region 6 or 7 for d 1 and d 2 is 1 μm.
The breakdown voltage between the conductive substrate 1 and the conductive substrate 1 is about 20V. In this case, the conductive substrate 1 is basically grounded before use.

【0014】この構成は、半絶縁性の結晶が得られれ
ば、結晶材料にはよらず、また導電性基板と、その上部
の結晶は同種である必要はない。さらに、電子回路を構
成する素子にもよらない。このように構成した集積回路
の入力端子又は出力端子4や、電源端子5等にサージが
加わった場合、電子回路3の耐圧よりも、各端子に接続
した導電領域6又は7と導電性基板1の耐圧の方が低い
ために、電子回路3が破壊又は誤動作する前に、導電領
域6又は7と導電性基板1の間に電流が流れ、端子に加
わったサージを吸収する。
In this structure, as long as a semi-insulating crystal is obtained, the crystal material does not need to be the same, and the conductive substrate and the crystal above it need not be of the same type. Furthermore, it does not depend on the element that constitutes the electronic circuit. When a surge is applied to the input terminal or output terminal 4, the power supply terminal 5 or the like of the integrated circuit configured as described above, the conductive region 6 or 7 connected to each terminal and the conductive substrate 1 are higher than the withstand voltage of the electronic circuit 3. Since the withstand voltage is lower, a current flows between the conductive region 6 or 7 and the conductive substrate 1 to absorb the surge applied to the terminal before the electronic circuit 3 is destroyed or malfunctions.

【0015】以上、サージの吸収機能を有する集積回路
の構成について説明したが、この構成により、サージ耐
圧の高い集積回路を容易に実現できるので、エンジン・
モータの制御等のサージが発生する部分、雑音の大きな
部分等で安定に動作させることができる。図2は本発明
の第2実施例を示すサージ吸収機能を有する半導体装置
の断面図である。
The structure of the integrated circuit having a surge absorbing function has been described above. With this structure, an integrated circuit having a high surge withstand voltage can be easily realized.
It is possible to stably operate in a portion where a surge such as motor control occurs or a portion where noise is large. FIG. 2 is a sectional view of a semiconductor device having a surge absorbing function showing a second embodiment of the present invention.

【0016】まず、n型又はp型の導電性基板(例え
ば、GaAs基板、またはSi基板)11上に、膜厚d
1 の半絶縁性結晶層(例えば、GaAs)12を成長さ
せる。その半絶縁性結晶層12にショットキゲート電界
効果トランジスタ13(以下、MESFET)を形成
し、これを能動素子として集積回路を構成する。17は
ソース電極、18ゲート電極、19はドレイン電極であ
り、このとき、MESFET13のドレイン領域16、
ソース領域14間の耐圧をV1 とするとき、ドレイン領
域16と導電性基板11の間の耐圧V2 が、 V2 <V1 となるように、半絶縁性結晶層12の膜厚d3 、ドレイ
ン領域16の深さd4 を形成する。そして、導電性基板
11を接地した構成とする。このドレイン領域16と導
電性基板11の間の耐圧V2 は結晶の材料によって異な
るが、例としてGaAsにCr、又はV等を添加して形
成した場合には、d3 −d4 の値に対して、約20V/
μmとなる。
First, a film thickness d is formed on an n-type or p-type conductive substrate (for example, GaAs substrate or Si substrate) 11.
One semi-insulating crystal layer (eg, GaAs) 12 is grown. A Schottky gate field effect transistor 13 (hereinafter, MESFET) is formed on the semi-insulating crystal layer 12, and an integrated circuit is configured by using this as an active element. Reference numeral 17 is a source electrode, 18 is a gate electrode, and 19 is a drain electrode. At this time, the drain region 16 of the MESFET 13,
When the withstand voltage between the source regions 14 is V 1 , the film thickness d 3 of the semi-insulating crystal layer 12 is such that the withstand voltage V 2 between the drain regions 16 and the conductive substrate 11 is V 2 <V 1. The depth d 4 of the drain region 16 is formed. Then, the conductive substrate 11 is grounded. The breakdown voltage V 2 between the drain region 16 and the conductive substrate 11 varies depending on the crystal material, but when formed by adding Cr, V or the like to GaAs as an example, the breakdown voltage V 2 becomes a value of d 3 -d 4 . On the other hand, about 20V /
μm.

【0017】なお、MESFET13のドレイン領域1
6・ソース領域14間の耐圧V1 は回路が正常に動作す
る電圧より高いことは言うまでもない。このように、集
積回路を構成した場合、電源線に重畳されたサージがド
レイン領域16にかかると、MESFET13のドレイ
ン・ソース間の耐圧V1 よりも、ドレイン領域16と導
電性基板11との間の耐圧V2 の方が小さいために、サ
ージ電圧が加わると、MESFET13が正常に動作し
なくなる前に電流が導電性基板11に流れて、サージを
吸収し、素子としてのMESFET13を破壊から保護
する。なお、図2において、15はチャネル部である。
The drain region 1 of the MESFET 13
It goes without saying that the withstand voltage V 1 between the 6 and source regions 14 is higher than the voltage at which the circuit operates normally. In the case where the integrated circuit is configured as described above, when the surge superimposed on the power supply line is applied to the drain region 16, the voltage between the drain region 16 and the conductive substrate 11 is higher than the drain-source breakdown voltage V 1 of the MESFET 13. for towards the breakdown voltage V 2 is small, a surge voltage is applied, MESFET13 flows through the conductive substrate 11 current before not work properly, to absorb surges, protected from destroy MESFET13 as element . In addition, in FIG. 2, 15 is a channel part.

【0018】以上、サージ電圧に対して耐性を有する素
子構造について述べたが、この構造により、エンジン・
モータの制御等のサージの発生する部分の回路、また雑
音の大きな部分で使用する回路等に安定に動作するモノ
シリックに集積される半導体装置を構成することができ
る。なお、本発明は上記実施例に限定されるものではな
く、本発明の趣旨に基づいて種々の変形が可能であり、
これらを本発明の範囲から排除するものではない。
The element structure having resistance to surge voltage has been described above.
It is possible to configure a monolithically integrated semiconductor device that operates stably in a circuit in a portion where a surge occurs such as motor control or in a circuit used in a portion where noise is large. The present invention is not limited to the above-mentioned embodiment, and various modifications can be made based on the spirit of the present invention.
They are not excluded from the scope of the present invention.

【0019】[0019]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 (1)請求項1記載の発明によれば、電子回路に加わる
サージをチップ内で吸収し、サージの電子回路への侵入
を防止するために、電子回路が破壊されず、正常に動作
するだけでなく、サージの吸収回路を集積回路に外付け
する必要がなく、モノシリック集積回路として構成する
ことができる。
As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention described in claim 1, in order to absorb the surge applied to the electronic circuit in the chip and prevent the surge from invading the electronic circuit, the electronic circuit is not destroyed and only operates normally. Moreover, it is not necessary to externally attach the surge absorbing circuit to the integrated circuit, and the surge absorbing circuit can be configured as a monolithic integrated circuit.

【0020】また、サージを吸収する導電領域と基板の
距離を制御するのみで、容易に種々のサージ電圧に対応
する半導体装置を構成することができる。 (2)請求項2記載の発明によれば、集積回路を構成す
る能動素子自体にサージ耐性をもたせることができるた
め、集積回路の外部にサージ対策を施す必要がなく、モ
ノシリックに集積化したサージ耐性を有する半導体装置
を構成することができる。
Further, by only controlling the distance between the conductive region that absorbs the surge and the substrate, it is possible to easily construct a semiconductor device that can cope with various surge voltages. (2) According to the invention as set forth in claim 2, since the active element itself constituting the integrated circuit can be provided with surge resistance, it is not necessary to take a surge countermeasure outside the integrated circuit, and the surge integrated monolithically is provided. A durable semiconductor device can be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例を示すサージ吸収機能を有
する半導体装置の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device having a surge absorbing function showing a first embodiment of the present invention.

【図2】本発明の第2実施例を示すサージ吸収機能を有
する半導体装置の断面図である。
FIG. 2 is a sectional view of a semiconductor device having a surge absorbing function showing a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,11 導電性基板 2,12 半絶縁性結晶層 3 電子回路 4 入力端子又は出力端子 5 電源端子 6,7 導電領域 13 ショットキゲート電界効果トランジスタ 14 ソース領域 15 チャネル部 16 ドレイン領域 17 ソース電極 18 ゲート電極 19 ドレイン電極 1, 11 conductive substrate 2, 12 semi-insulating crystal layer 3 electronic circuit 4 input terminal or output terminal 5 power supply terminal 6, 7 conductive region 13 Schottky gate field effect transistor 14 source region 15 channel part 16 drain region 17 source electrode 18 Gate electrode 19 Drain electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 上田 孝 東京都港区虎ノ門1丁目7番12号 沖電気 工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Ueda 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】(a)導電性基板と、(b)該導電性基板
上に成長する半絶縁性結晶層と、(c)該半絶縁性結晶
層に形成される電子回路と、(d)該電子回路に接続さ
れる入出力端子及び電源端子と、(e)前記電子回路と
入出力端子間に形成される第1の導電領域と、(f)前
記電子回路と電源端子間に形成される第2の導電領域と
を設け、(g)前記第1の導電領域及び第2の導電領域
と前記導電性基板間の耐圧を前記電子回路の耐圧より低
くなるようにモノシリックに集積することを特徴とする
半導体装置。
1. A conductive substrate, (b) a semi-insulating crystal layer grown on the conductive substrate, (c) an electronic circuit formed on the semi-insulating crystal layer, and (d). ) An input / output terminal and a power supply terminal connected to the electronic circuit, (e) a first conductive region formed between the electronic circuit and the input / output terminal, and (f) formed between the electronic circuit and the power supply terminal. And (g) monolithically integrating such that the breakdown voltage between the first and second conductive regions and the conductive substrate is lower than the breakdown voltage of the electronic circuit. A semiconductor device characterized by:
【請求項2】(a)導電性基板と、(b)該導電性基板
上に成長する半絶縁性結晶層と、(c)該半絶縁性結晶
層に形成される能動素子と、(d)該能動素子に形成さ
れる少なくとも第1の端子及び第2の端子と、(e)前
記能動素子の第1の端子に接続される第1の導電領域
と、(f)前記能動素子と第2の端子間に形成される第
2の導電領域とを設け、(g)前記第1の導電領域及び
第2の導電領域と前記導電性基板間の耐圧を前記能動素
子の耐圧より低くなるようにモノシリックに集積するこ
とを特徴とする半導体装置。
2. (a) a conductive substrate, (b) a semi-insulating crystal layer grown on the conductive substrate, (c) an active element formed on the semi-insulating crystal layer, and (d) ) At least a first terminal and a second terminal formed in the active element, (e) a first conductive region connected to the first terminal of the active element, (f) the active element and A second conductive region formed between two terminals, and (g) a breakdown voltage between the first conductive region and the second conductive region and the conductive substrate is lower than a breakdown voltage of the active element. A semiconductor device characterized by being monolithically integrated into a semiconductor device.
【請求項3】 請求項1又は2記載の半導体装置におい
て、前記半絶縁性結晶層の厚さをサージ電圧に対応させ
てなることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the thickness of the semi-insulating crystal layer corresponds to a surge voltage.
【請求項4】 請求項2記載の半導体装置において、前
記能動素子は電界効果トランジスタであり、第1の導電
領域はソース又はドレイン、第2の導電領域はドレイン
又はソースである半導体装置。
4. The semiconductor device according to claim 2, wherein the active element is a field effect transistor, the first conductive region is a source or a drain, and the second conductive region is a drain or a source.
【請求項5】 請求項4記載の半導体装置において、電
界効果トランジスタはショットキゲート電界効果トラン
ジスタである半導体装置。
5. The semiconductor device according to claim 4, wherein the field effect transistor is a Schottky gate field effect transistor.
JP7041469A 1995-03-01 1995-03-01 Semiconductor device Pending JPH08236549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7041469A JPH08236549A (en) 1995-03-01 1995-03-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7041469A JPH08236549A (en) 1995-03-01 1995-03-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08236549A true JPH08236549A (en) 1996-09-13

Family

ID=12609236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7041469A Pending JPH08236549A (en) 1995-03-01 1995-03-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08236549A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004023555A1 (en) * 2002-09-09 2004-03-18 Sanyo Electric Co., Ltd. Protective device
US6914280B2 (en) 2002-10-17 2005-07-05 Sanyo Electric Co., Ltd. Switching circuit device
US6946891B2 (en) 2003-02-20 2005-09-20 Sanyo Electric Co., Ltd. Switching circuit device
CN1326240C (en) * 2003-02-06 2007-07-11 三洋电机株式会社 Semiconductor device
US7538394B2 (en) 2004-12-22 2009-05-26 Sanyo Electric Co., Ltd. Compound semiconductor switch circuit device
US7732868B2 (en) 2002-09-09 2010-06-08 Sanyo Electric Co., Ltd. Semiconductor device
US8450805B2 (en) 2004-12-22 2013-05-28 Semiconductor Components Industries, Llc Compound semiconductor switch circuit device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004023555A1 (en) * 2002-09-09 2004-03-18 Sanyo Electric Co., Ltd. Protective device
CN1324708C (en) * 2002-09-09 2007-07-04 三洋电机株式会社 Protective device
US7732868B2 (en) 2002-09-09 2010-06-08 Sanyo Electric Co., Ltd. Semiconductor device
US8742506B2 (en) 2002-09-09 2014-06-03 Semiconductor Components Industries, Llc Protecting element having first and second high concentration impurity regions separated by insulating region
US9735142B2 (en) 2002-09-09 2017-08-15 Semiconductor Components Industries, Llc Method of forming a protecting element comprising a first high concentration impurity region separated by an insulating region of a substrate
US6914280B2 (en) 2002-10-17 2005-07-05 Sanyo Electric Co., Ltd. Switching circuit device
CN1326240C (en) * 2003-02-06 2007-07-11 三洋电机株式会社 Semiconductor device
US7262470B2 (en) 2003-02-06 2007-08-28 Sanyo Electric Co., Ltd. Semiconductor device
US6946891B2 (en) 2003-02-20 2005-09-20 Sanyo Electric Co., Ltd. Switching circuit device
US7538394B2 (en) 2004-12-22 2009-05-26 Sanyo Electric Co., Ltd. Compound semiconductor switch circuit device
US8450805B2 (en) 2004-12-22 2013-05-28 Semiconductor Components Industries, Llc Compound semiconductor switch circuit device

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