JPH0823145A - Substrate for hybrid ic - Google Patents

Substrate for hybrid ic

Info

Publication number
JPH0823145A
JPH0823145A JP6154849A JP15484994A JPH0823145A JP H0823145 A JPH0823145 A JP H0823145A JP 6154849 A JP6154849 A JP 6154849A JP 15484994 A JP15484994 A JP 15484994A JP H0823145 A JPH0823145 A JP H0823145A
Authority
JP
Japan
Prior art keywords
substrate
ceramic substrate
heat dissipation
film circuit
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6154849A
Other languages
Japanese (ja)
Inventor
Toshiyuki Nagase
敏之 長瀬
Yoshio Kanda
義雄 神田
Akifumi Hatsuka
昌文 初鹿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6154849A priority Critical patent/JPH0823145A/en
Publication of JPH0823145A publication Critical patent/JPH0823145A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To realize heat radiating property, insulating property and heat resistance by forming a thin-film circuit or thick-film circuit on the surface of a first ceramic substrate for heat radiation and piling and bonding an aluminum plate and a second ceramic substrate for heat radiation thereon respectively by an Al-Si based brazing material. CONSTITUTION:First, a substrate 10 for hybrid IC is formed by piling up and bonding a first ceramic substrate 11 for heat radiation, an aluminum plate 21 and a second ceramic substrate 22 for heat radiation in order by using an Al-Si based brazing material. Then a thin-film circuit or thick-film circuit 12 having a thick-film resistor 12a is formed on the surface of the substrate 11. Thus, the heat radiating property is further improved and the substrate 10 becomes more excellent in insulating property and heat resistance than an insulation layer of an HITT plate, resulting in soldering and brazing at a high temperature.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップが実装さ
れるハイブリッドIC用基板に関する。更に詳しくはア
ルミニウム板を用いた放熱性に優れた、大電力用に適す
るハイブリッドIC用基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid IC substrate on which a semiconductor chip is mounted. More specifically, the present invention relates to a hybrid IC substrate that uses an aluminum plate and is excellent in heat dissipation and suitable for high power.

【0002】[0002]

【従来の技術】近年の電子機器の小型化、高性能化によ
る単位体積当りの発熱量の増大に伴い、高放熱性のハイ
ブリッドIC用基板の要求が高まってきている。従来、
この種のハイブリッドIC用基板として、アルミニウム
板の表面に絶縁層を介して銅箔を接着した絶縁高熱伝導
性基板が知られている(加藤ら:実務表面技術、No.4,
55 (1982))。この基板は商品名「デンカHITTプレ
ート」(電気化学工業(株))と呼ばれ、この絶縁層には
高熱伝導性の無機フィラーを高充填したエポキシ系接着
剤が用いられる。このエポキシ系接着剤の熱伝導率は
4.2×10-3cal/cm・sec・℃であり、通常
のエポキシ樹脂の約10倍、ガラスエポキシの約6倍で
ある。 約80μm厚の上記絶縁層を有するHITTプ
レートの熱抵抗は0.72℃/Wであり、通常の約65
0μm厚のアルミナ基板の熱抵抗1.02℃/Wより小
さく、HITTプレートの熱伝導性が優れている。
2. Description of the Related Art With the recent miniaturization and higher performance of electronic equipment and an increase in the amount of heat generated per unit volume, there has been an increasing demand for a hybrid IC substrate with high heat dissipation. Conventionally,
As a hybrid IC substrate of this type, an insulating high thermal conductive substrate in which a copper foil is adhered to the surface of an aluminum plate via an insulating layer is known (Kato et al .: Practical Surface Technology, No. 4,
55 (1982)). This substrate is called a trade name "Denka HITT plate" (Denki Kagaku Kogyo Co., Ltd.), and an epoxy adhesive highly filled with an inorganic filler having a high thermal conductivity is used for this insulating layer. The thermal conductivity of this epoxy adhesive is 4.2 × 10 −3 cal / cm · sec · ° C., which is about 10 times that of ordinary epoxy resin and about 6 times that of glass epoxy. The HITT plate having the insulating layer having a thickness of about 80 μm has a thermal resistance of 0.72 ° C./W, which is about 65%.
The thermal resistance of the alumina substrate having a thickness of 0 μm is smaller than 1.02 ° C./W, and the thermal conductivity of the HITT plate is excellent.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来のハ
イブリッドIC用基板は熱伝導性又は放熱性に優れるも
のの、絶縁層が薄層であることもあって、絶縁特性が高
くない不具合があった。この絶縁特性を上げるために、
絶縁層を厚くすると、上記エポキシ系樹脂の熱抵抗は比
較的大きいため、基板の熱抵抗が大きくなる問題点があ
った。また絶縁層にエポキシ系樹脂を用いた基板は、耐
熱性に劣り、高温のはんだ付けやろう付けを行うことが
できない欠点があった。本発明の目的は、放熱性のみな
らず、絶縁性及び耐熱性にも優れたハイブリッドIC用
基板を提供することにある。
However, although the above-mentioned conventional hybrid IC substrate is excellent in thermal conductivity or heat dissipation, there is a problem that the insulating property is not high because the insulating layer is a thin layer. . In order to improve this insulation characteristic,
When the insulating layer is thickened, the thermal resistance of the epoxy resin is relatively large, and thus the thermal resistance of the substrate becomes large. In addition, a substrate using an epoxy resin for the insulating layer has poor heat resistance and has a drawback that high-temperature soldering or brazing cannot be performed. An object of the present invention is to provide a hybrid IC substrate which is excellent not only in heat dissipation but also in insulation and heat resistance.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するため
に、図1に示すように、本発明の第1のハイブリッドI
C用基板10は、第1放熱用セラミック基板11とアル
ミニウム板21と第2放熱用セラミック基板22とがそ
れぞれAl−Si系ろう材を介してこの順に積層接着さ
れ、第1放熱用セラミック基板11の表面に薄膜回路又
は厚膜回路12が形成されたものである。
In order to achieve the above object, as shown in FIG. 1, a first hybrid I of the present invention is provided.
In the C substrate 10, the first heat-dissipating ceramic substrate 11, the aluminum plate 21, and the second heat-dissipating ceramic substrate 22 are laminated and adhered in this order through Al-Si based brazing filler metal. The thin film circuit or the thick film circuit 12 is formed on the surface of the.

【0005】また図2に示すように、本発明の第2のハ
イブリッドIC用基板20は、第1のハイブリッドIC
用基板10の第2放熱用セラミック基板22の裏面に放
熱フィン31が接着されたものである。
Further, as shown in FIG. 2, the second hybrid IC substrate 20 of the present invention is the first hybrid IC substrate.
The heat radiation fins 31 are bonded to the back surface of the second heat radiation ceramic substrate 22 of the power supply substrate 10.

【0006】更に図3及び図4に示すように、本発明の
第3のハイブリッドIC用基板30は、第1放熱用セラ
ミック基板11の表面中央部に薄膜回路又は厚膜回路1
2が形成され、この薄膜回路又は厚膜回路12に電気的
に絶縁するように放熱用セラミック基板11の表面周縁
部にアルミニウムからなる枠板32がAl−Si系ろう
材を介して接着され、放熱用セラミック基板11の裏面
全体にアルミニウム板21がAl−Si系ろう材を介し
て接着されたものである。
Further, as shown in FIGS. 3 and 4, the third hybrid IC substrate 30 of the present invention has a thin film circuit or a thick film circuit 1 in the central portion of the surface of the first heat dissipation ceramic substrate 11.
2 is formed, and a frame plate 32 made of aluminum is adhered to the peripheral edge of the surface of the heat dissipation ceramic substrate 11 via an Al-Si brazing material so as to be electrically insulated from the thin film circuit or the thick film circuit 12. An aluminum plate 21 is adhered to the entire back surface of the heat dissipation ceramic substrate 11 via an Al-Si based brazing material.

【0007】なお、上記第1放熱用セラミック基板11
又は第2放熱用セラミック基板22としては、Al23
基板、AlN基板又はSiC基板を用いることができ
る。図5に示すように第1及び第2放熱用セラミック基
板がそれぞれAlN基板41及び51の場合には、基板
に化学安定性を付与するために基板を酸化処理して基板
表面にAl23層42及び52を形成した後、それぞれ
SiO2層43及び53を被覆しておくことが必要であ
る。Al23層とSiO2層の形成を要するのは、Al
N基板に厚膜を直接形成すると、厚膜形成後、大気中で
焼成したときに厚膜中に含まれているガラスとAlN
(窒化アルミニウム)が反応してN2やNOのガスを発
生し、厚膜に気泡を生じる不具合を解消するためであ
る。また、第1又は第2放熱用セラミック基板の厚さが
0.1〜1.0mmであって、アルミニウム板の厚さが
0.1〜1.0mmであって、アルミニウム板の厚さが
第1又は第2放熱用セラミック基板の厚さの10〜10
0%であることが好ましい。セラミック基板が0.1m
m未満であると、絶縁特性及び機械的強度に劣り、アル
ミニウム板がセラミック基板より相対的に厚くなると、
接着後の応力緩和時のクラック、割れが生じやすくな
る。アルミニウム板の厚さが0.1mm未満であるか、
或いはセラミック基板の10%未満になると、ハイブリ
ッドIC用基板としての放熱性が十分でない。
The first heat radiation ceramic substrate 11 is used.
Alternatively, as the second heat dissipating ceramic substrate 22, Al 2 O 3 is used.
A substrate, AlN substrate or SiC substrate can be used. As shown in FIG. 5, when the first and second heat-dissipating ceramic substrates are AlN substrates 41 and 51, respectively, the substrates are oxidized to impart chemical stability to the substrates, and Al 2 O 3 is applied to the substrate surfaces. After forming layers 42 and 52, it is necessary to coat SiO 2 layers 43 and 53, respectively. It is necessary to form the Al 2 O 3 layer and the SiO 2 layer because
If a thick film is formed directly on the N substrate, the glass and AlN contained in the thick film when baked in the air after the thick film is formed.
This is to solve the problem that (aluminum nitride) reacts with each other to generate N 2 and NO gas, thereby causing bubbles in the thick film. The first or second ceramic substrate for heat dissipation has a thickness of 0.1 to 1.0 mm, the aluminum plate has a thickness of 0.1 to 1.0 mm, and the aluminum plate has a thickness of 1 to 10 of the thickness of the second ceramic substrate for heat dissipation
It is preferably 0%. Ceramic substrate is 0.1m
When it is less than m, the insulating property and mechanical strength are poor, and when the aluminum plate becomes relatively thicker than the ceramic substrate,
Cracks and fractures tend to occur during stress relaxation after adhesion. Whether the thickness of the aluminum plate is less than 0.1 mm,
Alternatively, if it is less than 10% of the ceramic substrate, the heat dissipation as a hybrid IC substrate is insufficient.

【0008】[0008]

【作用】図1に示すように、アルミニウム板21を間に
挟んでセラミック基板11及び22を接着することによ
り、セラミック基板がAl23基板であれば、熱伝導度
が70×10-3cal/cm・sec・℃のAl23
板からなる絶縁層が得られ、この絶縁層の熱伝導度は、
従来のHITTプレートの絶縁層であるエポキシ系接着
剤の熱伝導度の4.2×10-3cal/cm・sec・
℃より遥かに大きい。熱伝導度がAl23より極めて大
きいAlN又はSiCをセラミック基板に用いれば、本
発明の絶縁層の熱伝導度はより一層大きくなり、アルミ
ニウム板と併用することにより、その熱伝導性はより顕
著になり、結果としてハイブリッドIC用基板の熱抵抗
は小さくなる。また、本発明のAl23、AlN又はS
iC等からなるセラミック基板は、従来のHITTプレ
ートの絶縁層より絶縁性及び耐熱性に優れ、高温のはん
だ付け、ろう付けが可能となる。
As shown in FIG. 1, by bonding the ceramic substrates 11 and 22 with the aluminum plate 21 sandwiched therebetween, if the ceramic substrate is an Al 2 O 3 substrate, the thermal conductivity is 70 × 10 −3. An insulating layer made of an Al 2 O 3 substrate of cal / cm · sec · ° C. is obtained, and the thermal conductivity of this insulating layer is
The thermal conductivity of the epoxy adhesive that is the insulating layer of the conventional HITT plate is 4.2 × 10 −3 cal / cm · sec ·
Much larger than ℃. When AlN or SiC whose thermal conductivity is much higher than that of Al 2 O 3 is used for the ceramic substrate, the thermal conductivity of the insulating layer of the present invention is further increased, and when it is used together with the aluminum plate, its thermal conductivity is further improved. As a result, the thermal resistance of the hybrid IC substrate becomes small. Further, according to the present invention, Al 2 O 3 , AlN or S
The ceramic substrate made of iC or the like is superior in insulating property and heat resistance to the insulating layer of the conventional HITT plate, and can be soldered or brazed at high temperature.

【0009】図2に示すように、第2放熱性セラミック
基板22の裏面にアルミニウム板21及び放熱フィン3
1を接着することにより、より一層放熱性が高まる。
As shown in FIG. 2, the aluminum plate 21 and the radiation fins 3 are provided on the back surface of the second radiation ceramic substrate 22.
By bonding 1 to each other, the heat dissipation is further enhanced.

【0010】[0010]

【実施例】次に本発明の実施例を図面に基づいて説明す
る。 <実施例1>Al23が96%純度の厚さ0.38m
m、たて50mm、よこ50mmのAl23基板の表面
にAuペーストをスクリーン印刷し150℃で乾燥した
後、大気中で連続ベルト炉を用いて850℃で10分間
焼成した。次いでRuO2系厚膜抵抗体ペーストを印刷
して150℃で乾燥し、再び、大気中、850℃で10
分間焼成し厚膜回路基板を得た。次にこの基板と、この
基板と同形同大の厚さ0.15mmの純アルミニウム板
と、このアルミニウム板と同形同大のAl23が96%
純度の厚さ0.38mmのAl23基板の間に、これら
と同形同大の厚さ30μmのAl−7.5%Si箔をそ
れぞれ挟んでこれらを重ね、これらに2kgf/cm2
の荷重を加えて真空炉中で630℃、30分間加熱して
3枚の板を積層接着した。図1に示すように、これによ
りAl23基板11とAl23基板22の間に高熱伝導
層としてのアルミニウム板21が接着され、基板11の
表面に厚膜抵抗体12aを有する厚膜回路12が形成さ
れたハイブリッドIC用基板10が得られた。ここで、
Al23基板22はアルミニウム板21を接着したこと
によって生じるAl23基板11の反りを防止し、応力
的に釣り合わせるために接着される。この基板10の厚
膜回路12に更に放熱特性を調べるためにシリコン半導
体チップ14をAl−Siはんだを用いて420℃でダ
イボンディングした後、300℃でAuワイヤボンディ
ングを行って実装した。
Embodiments of the present invention will now be described with reference to the drawings. Example 1 Al 2 O 3 is 96% pure and has a thickness of 0.38 m.
The Au paste was screen-printed on the surface of an Al 2 O 3 substrate of m, vertical 50 mm, and horizontal 50 mm, dried at 150 ° C., and then fired in the atmosphere at 850 ° C. for 10 minutes using a continuous belt furnace. Then, a RuO 2 type thick film resistor paste is printed, dried at 150 ° C., and again at 850 ° C. in the atmosphere at 10 ° C.
It was baked for a minute to obtain a thick film circuit board. Next, this substrate, a pure aluminum plate having the same shape and the same size as this substrate and a thickness of 0.15 mm, and Al 2 O 3 having the same shape and the same size as this aluminum plate are 96%.
Between the Al 2 O 3 substrate having a thickness of 0.38mm of purity, overlapping them across these same shape and size thickness 30μm of the Al-7.5% Si foil respectively, these 2 kgf / cm 2
Was applied and heated in a vacuum furnace at 630 ° C. for 30 minutes to laminate and adhere the three plates. As shown in FIG. 1, as a result, an aluminum plate 21 as a high thermal conductive layer is adhered between the Al 2 O 3 substrate 11 and the Al 2 O 3 substrate 22, and a thick film resistor 12a is provided on the surface of the substrate 11. The substrate 10 for hybrid IC on which the film circuit 12 was formed was obtained. here,
The Al 2 O 3 substrate 22 is bonded to prevent warpage of the Al 2 O 3 substrate 11 caused by bonding the aluminum plate 21 and to balance the stress. The silicon semiconductor chip 14 was mounted on the thick film circuit 12 of the substrate 10 by die bonding at 420 ° C. using Al—Si solder and further by Au wire bonding at 300 ° C. in order to further investigate the heat dissipation characteristics.

【0011】<実施例2>Al23が96%純度の厚さ
0.38mm、たて50mm、よこ50mmのAl23
基板の表面に実施例1と同様にAuペーストを印刷乾燥
して焼成し、かつRuO2系厚膜抵抗体ペーストを印刷
乾燥して焼成することにより、厚膜回路基板を得た。次
にこの基板と、この基板と同形同大の厚さ0.15mm
の純アルミニウム板と、このアルミニウム板と同形同大
のAl23が96%純度の厚さ0.38mmのAl23
基板の間に、これらと同形同大の厚さ30μmのAl−
7.5%Si箔をそれぞれ挟んでこれらを重ねた。この
とき、この厚膜回路を形成していない側のAl23基板
には、内径0.8mmのスルーホールをレーザ加工など
により形成し、この中にAlワイヤを挿入しておいた。
接着されかつ厚膜回路を形成していない側のAl23
板と放熱フィンの間に厚さ60μmのAl−7.5%S
i箔を挟み、20g/cm2の荷重を加えて真空炉中で
630℃、30分間加熱してスルーホールに挿入したA
lワイヤと放熱フィンを接着した。即ちアルミニウム板
にサーマルビア(thermal via hole)を介して放熱フィ
ンが接続された。図2に示すように、これによりAl2
3基板11とAl23基板22の間に高熱伝導層とし
てのアルミニウム板21が接着され、基板11の表面に
厚膜抵抗体12aを有する厚膜回路12が形成され、か
つサーマルビア22aで基板22に放熱フィン31が接
着されたハイブリッドIC用基板20が得られた。この
基板20の厚膜回路12に更に実施例1と同じシリコン
半導体チップ14を実施例1と同様に実装した。
[0011] <Example 2> Al 2 O 3 is 96% pure thickness 0.38 mm, vertical 50mm, horizontal 50mm of Al 2 O 3
A thick paste was printed and dried on the surface of the substrate in the same manner as in Example 1, and a RuO 2 -based thick film resistor paste was printed, dried and fired to obtain a thick film circuit board. Next, this board and the same shape and size as this board, thickness of 0.15 mm
Pure aluminum plate and Al 2 O 3 of the same shape and size as the aluminum plate of 96% purity and a thickness of 0.38 mm of Al 2 O 3
Between the substrates, Al-having the same shape and size and a thickness of 30 μm
These were stacked with a 7.5% Si foil sandwiched therebetween. At this time, a through hole having an inner diameter of 0.8 mm was formed by laser processing or the like in the Al 2 O 3 substrate on the side where the thick film circuit was not formed, and the Al wire was inserted therein.
60 μm thick Al-7.5% S between the Al 2 O 3 substrate which is adhered and on which the thick film circuit is not formed and the radiation fin.
i foil was sandwiched, a load of 20 g / cm 2 was applied, and the foil was heated in a vacuum furnace at 630 ° C. for 30 minutes and inserted into the through hole A
The 1-wire and the radiation fin were bonded. That is, the radiating fins were connected to the aluminum plate via thermal via holes. As shown in FIG. 2, this results in Al 2
An aluminum plate 21 as a high thermal conductive layer is adhered between the O 3 substrate 11 and the Al 2 O 3 substrate 22, a thick film circuit 12 having a thick film resistor 12a is formed on the surface of the substrate 11, and a thermal via 22a is formed. Thus, the hybrid IC substrate 20 in which the radiation fin 31 is bonded to the substrate 22 was obtained. The same silicon semiconductor chip 14 as in Example 1 was further mounted on the thick film circuit 12 of the substrate 20 in the same manner as in Example 1.

【0012】<実施例3>Al23が96%純度の厚さ
0.635mm、たて50mm、よこ50mmのAl2
3基板の表面にAuペーストをスクリーン印刷し15
0℃で乾燥した後、更にこのAl23基板に形成したス
ルーホール内にAuペーストを充填し150℃で乾燥し
た。その後大気中で連続ベルト炉を用いて850℃で1
0分間焼成した。次いでRuO2系厚膜抵抗体ペースト
を印刷して150℃で乾燥し、再び、大気中、850℃
で10分間焼成し厚膜回路基板を得た。次にこの基板
と、この基板と同形同大の厚さ0.2mmの純アルミニ
ウム板の間に厚さ30μmのAl−7.5%Si箔を挟
んでこれらを重ね、これらに2kgf/cm2の荷重を
加えて真空炉中で630℃、30分間加熱して2枚の板
を接着した。このAl23基板の表面端部とアルミニウ
ムからなる複数の厚さ0.4μmのリード端子との間に
厚さ30μmのAl−7.5%Si箔を挟んでこれらを
重ね、更にリード端子を設けないAl23基板の表面端
部に厚さ0.4μmの純アルミニウムの枠板を配し、基
板の表面端部と枠板との間に厚さ30μmのAl−7.
5%Si箔を挟んでこれらを重ね、リード端子、枠板及
び表面端部に2kgf/cm2の荷重を加えて真空炉中
で630℃、30分間加熱して、リード端子及び枠板を
基板の表面端部に接着した。図3及び図4に示すよう
に、これによりAl23基板11の裏面に高熱伝導層及
びグランド層としてのアルミニウム板21が接着され、
基板11の表面に厚膜抵抗体12aを有する厚膜回路1
2が形成され、かつ基板11の表面端部に複数のリード
端子13と枠板32が接着されたハイブリッドIC用基
板30が得られた。ここで枠板32はAl23基板11
のアルミニウム板21を接着したことによって生じる基
板の反りを防止し、応力的に釣り合わせるために接着さ
れる。この基板30の厚膜回路12に更に実施例1と同
じシリコン半導体チップ14を実施例1と同様にして実
装した。図4に示すように半導体チップ14直下の基板
11にはAuが充填されたスルーホール11aが設けら
れ、半導体チップ14のアース回路12bはこのスルー
ホール11aを介してアルミニウム板21に電気的に接
続された。
[0012] <Example 3> Al 2 O 3 96% purity thickness 0.635 mm, longitudinal 50 mm, lateral 50 mm Al 2
Screen-print Au paste on the surface of O 3 substrate 15
After drying at 0 ° C., Au paste was filled in the through holes formed in the Al 2 O 3 substrate and dried at 150 ° C. Then, in a continuous atmosphere using a continuous belt furnace at 850 ° C for 1
Bake for 0 minutes. Next, a RuO 2 type thick film resistor paste is printed, dried at 150 ° C., and again in air at 850 ° C.
And baked for 10 minutes to obtain a thick film circuit board. Next, this substrate and a pure aluminum plate having the same shape and size and a thickness of 0.2 mm and having a thickness of 30 μm of Al-7.5% Si foil sandwiched between them were stacked, and 2 kgf / cm 2 A load was applied and heating was performed in a vacuum furnace at 630 ° C. for 30 minutes to bond the two plates. An Al-7.5% Si foil having a thickness of 30 μm is sandwiched between the surface end of the Al 2 O 3 substrate and a plurality of lead terminals made of aluminum and having a thickness of 0.4 μm, and the lead terminals are further stacked. A pure aluminum frame plate having a thickness of 0.4 μm is arranged on the surface end portion of an Al 2 O 3 substrate not provided with Al 7 O having a thickness of 30 μm between the surface end portion of the substrate and the frame plate.
These are stacked with 5% Si foil sandwiched between them, and a load of 2 kgf / cm 2 is applied to the lead terminal, the frame plate and the surface end portion, and the mixture is heated in a vacuum furnace at 630 ° C. for 30 minutes to form the lead terminal and the frame plate on the substrate. Glued to the edge of the surface. As shown in FIGS. 3 and 4, by this, the aluminum plate 21 as the high thermal conductive layer and the ground layer is bonded to the back surface of the Al 2 O 3 substrate 11,
Thick film circuit 1 having thick film resistor 12a on the surface of substrate 11
2 was formed, and the hybrid IC substrate 30 was obtained in which the plurality of lead terminals 13 and the frame plate 32 were adhered to the end portions of the surface of the substrate 11. Here, the frame plate 32 is the Al 2 O 3 substrate 11
The aluminum plate 21 is adhered in order to prevent the warp of the substrate caused by the adhesion and to balance the stress. Further, the same silicon semiconductor chip 14 as in Example 1 was mounted on the thick film circuit 12 of the substrate 30 in the same manner as in Example 1. As shown in FIG. 4, a through hole 11a filled with Au is provided in the substrate 11 immediately below the semiconductor chip 14, and the ground circuit 12b of the semiconductor chip 14 is electrically connected to the aluminum plate 21 through the through hole 11a. Was done.

【0013】<実施例4>同形同大で厚さ0.38m
m、たて50mm、よこ50mmの2枚のAlN基板を
酸素雰囲気中で1300℃、1時間熱処理し、それぞれ
の基板の表裏両面に酸化層であるAl23層を形成し
た。次いで薄膜回路が形成される一方のAlN基板の表
面部分及び薄膜回路が形成されない他方のAlN基板の
裏面全体にSiO2ゾルを塗布した後、両AlN基板を
300℃で1時間乾燥させ、続いて900℃で1時間焼
成することにより、一方のAlN基板の表面部分及び他
方のAlN基板の裏面全体にSiO2層をそれぞれ形成
した。次にこの一方のAlN基板と、この基板と同形同
大の厚さ0.15mmの純アルミニウム板と、他方のA
lN基板との間に、これらと同形同大の厚さ30μmの
Al−7.5%Si箔をそれぞれ挟んでこれらを重ね、
これらに2kgf/cm2の荷重を加えて真空炉中で6
30℃、30分間加熱して3枚の板を積層接着した。図
5に示すように、これによりAlN基板41とAlN基
板51の間に高熱伝導層としてのアルミニウム板21が
接着された。この接着されたAlN基板41の表面全体
にスパッタリング法によりCu薄膜を形成し、回路パタ
ーン部分を被覆するマスクをした後、塩化第二鉄水溶液
でエッチングしてマスクで被覆されない部分のCu薄膜
を溶解し、AlN基板41の表面に導体パターンをそし
て同様にNi−Crの薄膜抵抗体44aを作ることによ
り薄膜回路44を形成した。ここで、AlN基板51は
アルミニウム板21を接着したことによって生じるAl
N基板41の反りを防止し、応力的に釣り合わせるため
に接着される。このハイブリッドIC用基板40の薄膜
回路44に更に実施例1と同じシリコン半導体チップ1
4を実装した。
<Embodiment 4> Same shape, same size and thickness of 0.38 m
Two AlN substrates having a length of 50 mm and a width of 50 mm were heat-treated in an oxygen atmosphere at 1300 ° C. for 1 hour to form Al 2 O 3 layers as oxide layers on both front and back surfaces of each substrate. Next, SiO 2 sol is applied to the entire front surface of one AlN substrate where the thin film circuit is formed and the entire back surface of the other AlN substrate where the thin film circuit is not formed, and then both AlN substrates are dried at 300 ° C. for 1 hour, and subsequently, By firing at 900 ° C. for 1 hour, a SiO 2 layer was formed on the front surface of one AlN substrate and the entire back surface of the other AlN substrate. Next, this one AlN substrate, a pure aluminum plate of the same shape and size and a thickness of 0.15 mm, and the other A
These are laminated with an Al-7.5% Si foil of the same shape and size and a thickness of 30 μm sandwiched between them and the 1N substrate,
A load of 2 kgf / cm 2 is applied to these, and 6 in a vacuum furnace
The plates were laminated and adhered by heating at 30 ° C. for 30 minutes. As shown in FIG. 5, as a result, the aluminum plate 21 as the high thermal conductive layer was bonded between the AlN substrate 41 and the AlN substrate 51. A Cu thin film is formed on the entire surface of the adhered AlN substrate 41 by a sputtering method, and a mask for covering the circuit pattern portion is used as a mask, followed by etching with an aqueous solution of ferric chloride to dissolve the Cu thin film in the portion not covered by the mask. Then, a thin film circuit 44 was formed by forming a conductor pattern on the surface of the AlN substrate 41 and similarly forming a Ni—Cr thin film resistor 44a. Here, the AlN substrate 51 is an Al produced by bonding the aluminum plate 21.
The N substrate 41 is adhered in order to prevent the warp and to balance the stress. The thin film circuit 44 of the hybrid IC substrate 40 further includes the same silicon semiconductor chip 1 as in the first embodiment.
Implemented 4.

【0014】<比較例1>アルミニウム板21とAl2
3基板22を接着しない以外は実施例1と同じ、即ち
Al23基板11のみのハイブリッドIC用基板の回路
に実施例1と同じシリコン半導体チップ14を実装し
た。
<Comparative Example 1> Aluminum plate 21 and Al 2
The same silicon semiconductor chip 14 as in Example 1 was mounted on the circuit of the hybrid IC substrate having only the Al 2 O 3 substrate 11 except that the O 3 substrate 22 was not adhered.

【0015】<比較例2>厚さ0.83mm、たて50
mm、よこ50mmの純アルミニウム板の表面に厚さ8
0μmのエポキシ系接着剤層を介して厚さ35μmのC
u箔を接着したハイブリッドIC用基板(前述したHI
TTプレート同等基板)を用意した。このエポキシ系接
着剤は高熱伝導性の無機フィラーを高充填して調製され
たものである。このハイブリッドIC用基板の回路に更
に実施例1と同じシリコン半導体チップ14を実装し
た。
<Comparative Example 2> Thickness 0.83 mm, vertical 50
8 mm thick, 50 mm wide, pure aluminum plate
C with a thickness of 35 μm through a 0 μm epoxy adhesive layer
Substrate for hybrid IC with u foil bonded
A substrate equivalent to a TT plate) was prepared. This epoxy adhesive is prepared by highly filling an inorganic filler having high thermal conductivity. The same silicon semiconductor chip 14 as in Example 1 was further mounted on the circuit of the hybrid IC substrate.

【0016】<比較試験と評価> (a) 放熱性試験 25℃の恒温室中で、実施例1〜実施例4のハイブ
リッドIC用基板と比較例1及び比較例2のハイブリッ
ドIC用基板のそれぞれのシリコン半導体チップに通電
し、20分後のチップの表面温度TC1と発熱量Q1を測
定した。室温をTR1として、次の式(1)より放熱特性
を求めた。 放熱特性(℃/W) = (TC1−TR1)/Q1 …… (1) 実施例1〜実施例4のハイブリッドIC用基板と比
較例1及び比較例2のハイブリッドIC用基板をチップ
実装面を上方に向けて、20℃で水冷された厚さ30m
m、たて100mm、よこ100mmのいわゆる理想放
熱器の純Cu板の上に置いた。上記と同様にシリコン
半導体チップに通電し、10分後のチップの表面温度T
C2と発熱量Q2を測定した。また基板裏面の温度をTR2
として、次の式(2)より基板の熱抵抗値を求めた。な
お、実施例2のハイブリッドIC用基板20では放熱フ
ィン31を外して測定した。 基板の熱抵抗値(℃/W) = (TC2−TR2)/Q2 …… (2) これらの結果を表1に示す。
<Comparative Test and Evaluation> (a) Heat Dissipation Test Each of the hybrid IC substrates of Examples 1 to 4 and the hybrid IC substrates of Comparative Examples 1 and 2 in a thermostatic chamber at 25 ° C. Then, the surface temperature T C1 of the chip and the amount of heat generation Q 1 of the chip were measured after 20 minutes of application of electricity. The room temperature as T R1, determine the heat radiation characteristics by the following equation (1). Heat dissipation characteristic (° C./W)=(T C1 −T R1 ) / Q 1 (1) The hybrid IC substrates of Examples 1 to 4 and the hybrid IC substrates of Comparative Examples 1 and 2 are chipped. 30m thickness water-cooled at 20 ℃ with the mounting surface facing upward
It was placed on a pure Cu plate of a so-called ideal radiator of m, vertical 100 mm, and horizontal 100 mm. The silicon semiconductor chip is energized in the same manner as above, and the surface temperature T of the chip after 10 minutes
C2 and the calorific values were measured Q 2. The temperature of the substrate back surface T R2
As a result, the thermal resistance value of the substrate was obtained from the following equation (2). In the hybrid IC substrate 20 of Example 2, the heat radiation fin 31 was removed and the measurement was performed. The thermal resistance of the substrate (℃ / W) = (T C2 -T R2) / Q 2 ...... (2) These results are shown in Table 1.

【0017】[0017]

【表1】 [Table 1]

【0018】表1から明らかなように、比較例1と比べ
て、放熱特性及び基板の熱抵抗値とも実施例1〜実施例
4は優れていた。また比較例2と比べて、放熱特性に関
しては実施例2及び実施例4が優れ、実施例1及び実施
例3は同じ値を示した。基板の熱抵抗値に関しては実施
例1〜実施例4はいずれも比較例2より優れていた。特
に、実施例4の熱抵抗値は比較例2の約3分の1であっ
た。
As is clear from Table 1, Examples 1 to 4 were superior to Comparative Example 1 in both heat dissipation characteristics and substrate thermal resistance. Further, as to the heat dissipation characteristics, the second and the fourth embodiments are superior to the second comparative example, and the first and the third examples show the same value. Regarding the thermal resistance value of the substrate, all of Examples 1 to 4 were superior to Comparative Example 2. Particularly, the thermal resistance value of Example 4 was about one-third that of Comparative Example 2.

【0019】(b) 絶縁性試験及び耐熱性試験 実施例1〜実施例4のハイブリッドIC用基板と比較例
2のハイブリッドIC用基板の絶縁耐圧と耐熱性をそれ
ぞれ調べた。絶縁耐圧はハイブリッドIC用基板表面の
回路と基板裏面との間に電流値1mA以下で1分間印加
したときの絶縁破壊しない最大電圧を測定した。また耐
熱性はハイブリッドIC用基板を260℃と430℃と
でそれぞれ5分間維持したときの基板表面の回路の膨れ
や基板のうねりの有無を肉眼で調べた。これらの結果を
表2に示す。表2の耐熱性の結果において、○は変化な
しで良好、×は膨れやうねり等を生じた不良を示す。
(B) Insulation test and heat resistance test The dielectric strength and heat resistance of the hybrid IC substrates of Examples 1 to 4 and the hybrid IC substrate of Comparative Example 2 were examined. As the withstand voltage, the maximum voltage that does not cause dielectric breakdown was measured when a current value of 1 mA or less was applied between the circuit on the front surface of the hybrid IC substrate and the back surface of the substrate for 1 minute. Regarding the heat resistance, the presence or absence of swelling of the circuit on the surface of the substrate and undulation of the substrate when the substrate for hybrid IC was kept at 260 ° C. and 430 ° C. for 5 minutes respectively was examined visually. Table 2 shows the results. In the results of heat resistance in Table 2, ◯ means good without any change, and x means bad such as swelling or waviness.

【0020】[0020]

【表2】 [Table 2]

【0021】表2から明らかなように、比較例2の絶縁
耐圧が2kV以下であるのに対して、実施例1〜実施例
4では5kV以上を示した。また430℃で比較例2は
膨れやうねりを生じたのに対して、実施例1〜実施例4
は全く異常は見られなかった。
As is clear from Table 2, the withstand voltage of Comparative Example 2 is 2 kV or less, while that of Examples 1 to 4 is 5 kV or more. Further, at 430 ° C., Comparative Example 2 produced swelling and undulation, whereas Examples 1 to 4
No abnormalities were found.

【0022】なお、本発明の放熱性セラミック基板はA
23基板及びAlN基板に限らず、SiC基板でもよ
い。実施例4のようにAlN基板を第2及び第3のハイ
ブリッドIC用基板に用いることもでき、また第1放熱
性セラミック基板の表面に厚膜回路の代わりに薄膜回路
を形成してもよい。また、Al−Si系ろう材として、
Al−7.5%Si箔を例示したが、これ以外にAl−
13%Si、Al−9.5%Si−1.0%Mg、Al
−7.5%Si−10%Ge等からなる箔を用いること
もできる。
The heat-dissipating ceramic substrate of the present invention is A
Not limited to the l 2 O 3 substrate and the AlN substrate, a SiC substrate may be used. The AlN substrate may be used as the second and third hybrid IC substrates as in Example 4, and a thin film circuit may be formed on the surface of the first heat radiation ceramic substrate instead of the thick film circuit. Further, as an Al-Si brazing material,
Although Al-7.5% Si foil was illustrated, other than this, Al-
13% Si, Al-9.5% Si-1.0% Mg, Al
A foil made of -7.5% Si-10% Ge or the like can also be used.

【0023】[0023]

【発明の効果】以上述べたように、従来のHITTプレ
ートに代表される絶縁高熱伝導性基板からなるハイブリ
ッドIC用基板と比べて、本発明のハイブリッドIC用
基板はアルミニウム板を回路形成する放熱性セラミック
基板の裏面に接着することにより、放熱性を向上でき
る。特に第2放熱性セラミック基板の裏面にアルミニウ
ム板及び放熱フィンを接着することにより、より一層放
熱性が高まる。また、本発明のAl23、AlN又はS
iC等からなるセラミック基板は、従来のHITTプレ
ートの絶縁層より絶縁性及び耐熱性に優れ、高温のはん
だ付け、ろう付けが可能となる。
As described above, the hybrid IC substrate of the present invention has a heat dissipation property that forms a circuit of an aluminum plate, as compared with the hybrid IC substrate made of an insulating and high thermal conductive substrate represented by a conventional HITT plate. By adhering to the back surface of the ceramic substrate, heat dissipation can be improved. Particularly, by adhering the aluminum plate and the heat radiation fins to the back surface of the second heat radiation ceramic substrate, the heat radiation is further enhanced. Further, according to the present invention, Al 2 O 3 , AlN or S
The ceramic substrate made of iC or the like is superior in insulating property and heat resistance to the insulating layer of the conventional HITT plate, and can be soldered or brazed at high temperature.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1のハイブリッドIC用基板の断面
図。
FIG. 1 is a cross-sectional view of a first hybrid IC substrate of the present invention.

【図2】本発明の第2のハイブリッドIC用基板の断面
図。
FIG. 2 is a sectional view of a second hybrid IC substrate of the present invention.

【図3】本発明の第3のハイブリッドIC用基板の断面
図。
FIG. 3 is a cross-sectional view of a third hybrid IC substrate of the present invention.

【図4】図3のA−A線断面図。FIG. 4 is a sectional view taken along line AA of FIG. 3;

【図5】本発明の別の第1のハイブリッドIC用基板の
断面図。
FIG. 5 is a cross-sectional view of another first hybrid IC substrate of the present invention.

【符号の説明】[Explanation of symbols]

10,20,30,40 ハイブリッドIC用基板 11 第1放熱用セラミック基板(Al23基板) 11a スルーホール 12 厚膜回路 12b アース回路 13 リード端子 21 アルミニウム板 22 第2放熱用セラミック基板(Al23基板) 22a サーマルビア 31 放熱フィン 32 枠板 41 第1放熱用セラミック基板(AlN基板) 51 第2放熱用セラミック基板(AlN基板) 42,52 酸化層(Al23層) 43,53 SiO210, 20, 30, 40 Hybrid IC substrate 11 First heat dissipation ceramic substrate (Al 2 O 3 substrate) 11a Through hole 12 Thick film circuit 12b Ground circuit 13 Lead terminal 21 Aluminum plate 22 Second heat dissipation ceramic substrate (Al 2 O 3 substrate) 22a thermal via 31 heat dissipation fin 32 frame plate 41 first heat dissipation ceramic substrate (AlN substrate) 51 second heat dissipation ceramic substrate (AlN substrate) 42, 52 oxide layer (Al 2 O 3 layer) 43, 53 SiO 2 layer

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/36 H05K 1/02 F 1/05 Z H01L 23/12 J 23/14 M 23/36 Z Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI Technical display location H01L 23/36 H05K 1/02 F 1/05 Z H01L 23/12 J 23/14 M 23/36 Z

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 第1放熱用セラミック基板(11,41)とア
ルミニウム板(21)と第2放熱用セラミック基板(22,51)
とがそれぞれAl−Si系ろう材を介してこの順に積層
接着され、 前記第1放熱用セラミック基板(11,41)の表面に薄膜回
路(44)又は厚膜回路(12)が形成されたハイブリッドIC
用基板。
1. A first heat dissipation ceramic substrate (11, 41), an aluminum plate (21), and a second heat dissipation ceramic substrate (22, 51).
Are laminated and adhered in this order via Al-Si type brazing filler metal, and a thin film circuit (44) or a thick film circuit (12) is formed on the surface of the first heat dissipation ceramic substrate (11, 41). IC
Substrate.
【請求項2】 第1放熱用セラミック基板(11,41)とア
ルミニウム板(21)と第2放熱用セラミック基板(22,51)
とがそれぞれAl−Si系ろう材を介してこの順に積層
接着され、 前記第1放熱用セラミック基板(11,41)の表面に薄膜回
路(44)又は厚膜回路(12)が形成され、かつ前記第2放熱
用セラミック基板(22,51)の裏面に放熱フィン(31)が接
着されたハイブリッドIC用基板。
2. A first heat dissipation ceramic substrate (11, 41), an aluminum plate (21), and a second heat dissipation ceramic substrate (22, 51).
Are laminated and adhered in this order through Al-Si brazing filler metal, and a thin film circuit (44) or a thick film circuit (12) is formed on the surface of the first heat dissipation ceramic substrate (11, 41), and A hybrid IC substrate in which a heat radiation fin (31) is adhered to the back surface of the second heat radiation ceramic substrate (22, 51).
【請求項3】 第1放熱用セラミック基板(11,41)の表
面中央部に薄膜回路(44)又は厚膜回路(12)が形成され、 前記薄膜回路(44)又は厚膜回路(12)に電気的に絶縁する
ように前記放熱用セラミック基板(11,41)の表面周縁部
にアルミニウムからなる枠板(32)がAl−Si系ろう材
を介して接着され、 前記放熱用セラミック基板(11,41)の裏面全体にアルミ
ニウム板(21)がAl−Si系ろう材を介して接着された
ハイブリッドIC用基板。
3. A thin film circuit (44) or a thick film circuit (12) is formed in the central portion of the surface of the first heat dissipation ceramic substrate (11, 41), and the thin film circuit (44) or the thick film circuit (12). A frame plate (32) made of aluminum is adhered to the peripheral edge portion of the surface of the heat dissipation ceramic substrate (11, 41) via an Al-Si brazing material so as to be electrically insulated from the heat dissipation ceramic substrate ( A hybrid IC substrate in which an aluminum plate (21) is adhered to the entire back surface of (11, 41) via an Al-Si brazing material.
【請求項4】 第1放熱用セラミック基板(11,41)の表
面中央部に形成された薄膜回路(44)又は厚膜回路(12)の
うちのアース回路(12b)とアルミニウム板(21)とを電気
的に接続するスルーホール(11a)が前記放熱用セラミッ
ク基板(11,41)に形成された請求項3記載のハイブリッ
ドIC用基板。
4. The earth circuit (12b) and the aluminum plate (21) of the thin film circuit (44) or the thick film circuit (12) formed in the central portion of the surface of the first heat dissipating ceramic substrate (11, 41). The substrate for hybrid IC according to claim 3, wherein a through hole (11a) for electrically connecting and is formed in the heat dissipation ceramic substrate (11, 41).
【請求項5】 第1放熱用セラミック基板(11,41)がA
23基板、SiC基板又は基板を酸化処理後基板表面
がSiO2層で被覆されたAlN基板である請求項1な
いし4いずれか記載のハイブリッドIC用基板。
5. The first heat dissipation ceramic substrate (11, 41) is A
l 2 O 3 substrate, a substrate for a hybrid IC of a SiC substrate or substrate oxidation treatment after the substrate surface according with claim 1, which is a AlN substrate coated with the SiO 2 layer 4.
【請求項6】 第1及び第2放熱用セラミック基板(11,
41,22,51)がそれぞれAl23基板、SiC基板又は基
板を酸化処理後基板表面がSiO2層で被覆されたAl
N基板である請求項1又は2記載のハイブリッドIC用
基板。
6. The first and second heat radiation ceramic substrates (11,
41, 22, 51) are Al 2 O 3 substrates, SiC substrates, or Al whose surfaces are coated with a SiO 2 layer after the substrate is oxidized.
The hybrid IC substrate according to claim 1, which is an N substrate.
【請求項7】 第1又は第2放熱用セラミック基板(11,
41,22,51)の厚さが0.1〜1.0mmであって、アル
ミニウム板(21)の厚さが0.1〜1.0mmであって、
前記アルミニウム板の厚さが前記第1又は第2放熱用セ
ラミック基板の厚さの10〜100%である請求項1な
いし4いずれか記載のハイブリッドIC用基板。
7. The first or second heat radiation ceramic substrate (11,
41,22,51) has a thickness of 0.1 to 1.0 mm, the aluminum plate (21) has a thickness of 0.1 to 1.0 mm,
The hybrid IC substrate according to any one of claims 1 to 4, wherein the thickness of the aluminum plate is 10 to 100% of the thickness of the first or second ceramic substrate for heat dissipation.
JP6154849A 1994-07-06 1994-07-06 Substrate for hybrid ic Withdrawn JPH0823145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6154849A JPH0823145A (en) 1994-07-06 1994-07-06 Substrate for hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6154849A JPH0823145A (en) 1994-07-06 1994-07-06 Substrate for hybrid ic

Publications (1)

Publication Number Publication Date
JPH0823145A true JPH0823145A (en) 1996-01-23

Family

ID=15593251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6154849A Withdrawn JPH0823145A (en) 1994-07-06 1994-07-06 Substrate for hybrid ic

Country Status (1)

Country Link
JP (1) JPH0823145A (en)

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