JPH08181302A - Semiconductor device and its manufacture as well as thin film transistor and its manufacture as well as liquid crystal display device - Google Patents

Abstract

PURPOSE: To enhance a conductive characteristic and to lower resistance by a method wherein a silicide layer which contains a phosphorus or boron element and a hydrogen element at a concentration in a specific range is formed on respective surfaces of a doped source part and a doped drain part. CONSTITUTION: A silicon semiconductor film 3 is covered with a metal film 7. After that, phosphors or boron ions 8 are implanted together with hydrogen ions. Then, a silicide layer 9s is formed on the surface of a silicon semiconductor 3s as a source part, and a silicide layer 9p is formed on the surface of a silicon semiconductor 3p as a drain part. The silicide layers 9s, 9p contain a phosphorus or boron element at a concentration of 2×10<19> to 2×10<21> pieces/cm<3> , and they contain a hydrogen element at a concentration of 1×10<19> to 4×10<21> pieces/cm<3> . Thereby, the silicide layers with low resistance can be formed at a low temperature without executing a high temperature annealing treatment and without irradiating them with intense light such as a laser or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device preferably used for a liquid crystal display, a long image sensor and the like, a manufacturing method thereof, a thin film transistor and a manufacturing method thereof, and a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, in the above-described liquid crystal display, image sensor, etc., it is necessary to form a thin film transistor (TFT) of an external mounting drive circuit on a substrate provided in the display or the image sensor, that is, on the same substrate. Is increasing. In manufacturing such a TFT, a technique of implanting ions using the gate electrode as a mask to form source / drain parts in a self-aligned manner was developed because the transistor channel length can be shortened and high performance is easily achieved. Is progressing.

[0003]

However, when an inexpensive glass substrate is used as the substrate, it is usually 600 ° C. or lower,
It is necessary to perform the temperature process preferably at 500 ° C. or less, and it is difficult to form the source / drain portion having such low temperature and low resistance.

For example, when the semiconductor film of the transistor is an amorphous silicon film, the n-type resistivity is 10 ³ to 10 ⁵ Ω · c.
Since the resistivity is extremely high as m, the resistance of the source / drain portion becomes high, which is a problem. On the other hand, when the semiconductor film of the transistor is a polycrystalline silicon film, the n-type resistivity is usually about 10 ^-2 Ω · cm, and if the film thickness is 100 nm, the sheet resistance is 1 kΩ / □, which is a relatively high resistance. Met. In particular, when a TFT having an electric field mobility of more than 150 cm ² / V · s is manufactured, it is necessary to have a sheet resistance of 500 Ω / □ or less, which is a problem.

Therefore, the following three methods have been proposed as a method for reducing the substantial resistance by forming a silicide film on the source / drain portions. The first proposed method is a method of forming a silicide film by laminating a metal film that reacts with silicon and heating and reacting it after an ion introduction step of introducing an n-type or p-type impurity ion (Japanese Patent Application Laid-Open No. Hei. 94133). Generally, it is difficult to form a low-resistance silicide unless heat treatment is performed at a high temperature. In this proposal, since the treatment is performed at a low temperature of about 250 to 300 ° C., the surface resistance is about 10 kΩ / □. Therefore, only a silicide film having a considerably high resistance can be formed.

Similarly, the second proposed method is a method of forming a silicide film by laminating a metal film which reacts with silicon after introducing impurities into the amorphous semiconductor of the source / drain portions (special feature). (Kaisho 63-168052). Generally, it is difficult to form a low-resistance silicide unless the heat treatment is performed at a high temperature, and it is preferable to perform the annealing treatment at 150 ° C. for about 20 minutes in the specification.
Also in this case, the surface resistance is about 10 because it is processed at a low temperature.
Only a silicide film having a very high resistance of kΩ / □ can be formed.

In the third proposed method, a metal film is formed on the silicon semiconductor film of the source / drain portion in which impurities are implanted, and then the metal film is irradiated with strong light to combine the metal and silicon to form the silicide film. It is a method of forming (JP-A-6-124962). In this case, as a method of combining a metal and silicon to form a silicidation, strong light such as a laser is irradiated and reacted. Usually, it is common to raise the temperature of the portion to be reacted in this way to silicidize, and an extra step of irradiating strong light or performing thermal annealing was necessary.

The present invention has been made to solve the problems of the prior art as described above, and a semiconductor device having a low resistance silicide layer and a method for manufacturing the same, and a thin film transistor having a low resistance source / drain portion, and It is an object of the present invention to provide a manufacturing method thereof and a liquid crystal display device having high display quality.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
Contains phosphorus or boron element and contains 1 × 10 ¹⁹ to 4 × 1
It has a silicide layer containing a hydrogen element with a concentration of 0 ²¹ pieces / cm ^{3 and} thereby achieves the above object.

In the semiconductor device of the present invention, it is preferable that the silicide layer contains phosphorus or boron element at a concentration of 2 × 10 ¹⁹ to 2 × 10 ²¹ pieces / cm ³ .

The thin film transistor of the present invention has a semiconductor film containing silicon, a gate insulating film, and a gate electrode covered with an anodized oxide film. A silicide layer containing a phosphorus or boron element and a hydrogen element at a concentration of 1 × 10 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ is provided on the surface, thereby achieving the above object.

In the thin film transistor of the present invention, it is preferable that the silicide layer contains phosphorus or boron element at a concentration of 2 × 10 ¹⁹ to 2 × 10 ²¹ pieces / cm ³ .

A method of manufacturing a semiconductor device according to the present invention includes a step of coating a metal film on a silicon semiconductor film, and a phosphorus or boron element and a hydrogen element between the silicon semiconductor film and the metal film. The step of providing the silicide layer by implanting phosphorus or boron ions together with hydrogen ions, whereby the above object is achieved.

In the method of manufacturing a semiconductor device of the present invention,
2 × 10 ¹⁹ to 2 × 10 ²¹ silicide layers / cm ³
Containing a concentration of phosphorus or boron element, and 1 × 10 ¹⁹
Ion implantation is preferably performed so as to contain a hydrogen element at a concentration of up to 4 × 10 ²¹ pieces / cm ³ . A method of manufacturing a thin film transistor according to the present invention includes a step of forming a silicon semiconductor film, a step of forming a gate insulating film, and a step of forming a gate electrode covered with an anodized oxide film. In a step of coating a metal film on the silicon semiconductor film, and forming a silicide layer containing a phosphorus or boron element and a hydrogen element between the silicon semiconductor film and the metal film together with hydrogen ions. And a step of providing by implanting ions, whereby the above object is achieved.

In the method of manufacturing a thin film transistor according to the present invention, the number of silicide layers is 2 × 10 ¹⁹ to 2 × 10 ²¹ /
Containing elemental phosphorus or boron at a concentration of cm ³ and 1 ×
Preferably, the ion implantation to contain 10 ^{1 9} ~4 × 10 ²¹ atoms / cm ³ concentration of hydrogen element.

In the method of manufacturing a thin film transistor of the present invention, it is preferable that the silicide layer on the source portion and the drain portion is formed in a self-aligned manner by etching the gate insulating film using the gate electrode as a mask. .

In the method of manufacturing a thin film transistor according to the present invention, it is preferable that the step of providing the silicide layer and the steps thereafter are performed at a temperature of 450 ° C. or lower.

The liquid crystal display device of the present invention achieves the above object by using the thin film transistor of the present invention as the thin film transistor of the picture element portion.

[0019]

According to the semiconductor device of the present invention, the element contains phosphorus or boron and contains 1 × 10 ¹⁹ to 4 × 10 ²¹ pieces / cm 3.
^It has a silicide layer containing ^three concentrations of hydrogen element. Since this silicide layer has a low resistance, it is formed on the electrodes and wirings of the semiconductor device. In this case, the silicide layer is 2 × 1
If the phosphorus or boron element is contained at a concentration of 0 ^{19 to} 2 × 10 ²¹ pieces / cm ³ , the resistance can be further reduced.

In this semiconductor device, a step of coating a metal film on a silicon semiconductor film, and a silicide layer containing a phosphorus or boron element and a hydrogen element is formed between the silicon semiconductor film and the metal film with hydrogen. The process can be performed by implanting phosphorus or boron ions together with the ions. Therefore, without anneal treatment at high temperature or irradiation with strong light such as laser light, 450 ° C. or lower, for example, 3
The silicide layer can be formed at a low temperature of 00 ° C. or lower.

The thin film transistor of the present invention is also similar to the above-mentioned semiconductor device, but has a structure in which the silicide layer on the source part and the drain part is formed in a self-aligned manner by using the gate electrode as a mask. Thereby, the resistance values of the source part and the drain part can be made extremely small.

In the liquid crystal display device of the present invention, by using the above-mentioned thin film transistor in the picture element part, the voltage drop due to the resistance of the electrode wiring part and the delay due to the time constant of CR are eliminated, and the liquid crystal display device has a high display quality. be able to.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Example 1 In this example, the present invention is applied to a thin film transistor which is an example of a semiconductor device.

FIGS. 1A to 1G are process sectional views showing a method of manufacturing a thin film transistor of this embodiment.
(G) is sectional drawing which shows the thin-film transistor of a present Example. The configuration of this thin film transistor will be described in the order of steps.

As shown in FIG. 1A, an insulating film such as a SiO ₂ film is formed on an insulating substrate 1 made of glass.
In order to form the coating film 2 having a film thickness of 100 to 500 nm and subsequently improve the coating film 2,
Annealing was performed at 600 ° C. for 12 hours in an N ₂ atmosphere. As the coating film 2, a SiO ₂ film formed by atmospheric pressure CVD method at 430 ° C. using SiH ₄ gas and O ₂ gas was used. Although the atmospheric pressure CVD method was used in this embodiment,
A film thickness of 100 by any one of the sputtering method, the low pressure CVD method, the plasma CVD method, and the remote plasma CVD method.
It goes without saying that a SiO ₂ film of up to 500 nm may be used. Further, although the SiO ₂ film is used in this embodiment,
SiN _x film, Al ₂ O ₃ film, Ta ₂ O ₅ film or these 2
It goes without saying that a film composed of a plurality of films combined as described above may be used.

Next, a film thickness of 3 is formed on the coating film 2.
The semiconductor film 3 processed into an island shape having a thickness of 0 to 150 nm is formed. As the material of the semiconductor film 3, for example, an amorphous material such as silicon (Si) or silicon germanium (SiGe), a microcrystal, a polycrystal, or a single crystal is used.

The semiconductor film 3 is formed as follows. That is, in the case of an amorphous silicon semiconductor, SiH ₄ gas and H ₂ gas are used by the plasma CVD method,
A film is formed at a substrate temperature of 200 to 300 ° C. Further, in the case of a microcrystalline silicon semiconductor, Si is formed by a plasma CVD method.
The gas ratio of H ₄ / H ₂ is set in the range of 1/30 to 1/100, and the film is formed at the substrate temperature of 200 to 400 ° C.

In the case of a polycrystalline silicon semiconductor,
The amorphous silicon film formed at a substrate temperature of 450 ° C. by the low pressure CVD method or the amorphous silicon film formed by the plasma CVD method described above is annealed in N ₂ gas at 550 to 600 ° C. for 24 hours to obtain a large amount. A crystalline silicon film is formed. Here, Si ₂ H ₆ can be used as the source gas in addition to SiH ₄ . Also, a polycrystalline silicon film may be formed from the beginning. Further, a polycrystalline silicon film may be formed on the above-mentioned amorphous silicon film by laser irradiation or light irradiation with a lamp. In the case of a single crystal,
A silicon film is formed on the substrate by epitaxially growing silicon at a high temperature using a sapphire substrate or the like, or a single crystal silicon film is formed from an amorphous or polycrystalline silicon film by laser irradiation. Alternatively, it may be a silicon wafer itself which is a single crystal.

The silicon semiconductor film thus produced is patterned by etching to form the island-shaped silicon semiconductor film 3.

Next, the island-shaped silicon semiconductor film 3 is covered with a film having a thickness of, for example, 50 to 1 on the coating film 2.
Forming a gate insulating film 4 of 50 nm, followed by, in order to improve the gate insulating film 4, 12 at 600 ° C. in a N ₂ atmosphere
Annealing of h was performed. As the gate insulating film 27, a SiO ₂ film formed by atmospheric pressure CVD method at 430 ° C. using SiH ₄ gas and O ₂ gas was used. In this embodiment, normal pressure C
Although the VD method is used, any of a sputtering method, a low pressure CVD method, a plasma CVD method, and a remote plasma CVD method may be used. Furthermore, TE with good step coverage
OS (Tetra-Ethyl-Ortho-Sili
atmospheric pressure CV using cat, Si (OC ₂ H ₅ ) ₄ ) gas
You may use D method and plasma CVD method. Further, in this embodiment, the SiO ₂ film is used as the gate insulating film 4, but
SiN _x film, Al ₂ O ₃ film, Ta ₂ O ₅ film or these 2
A film composed of a plurality of films combined as described above may be used.

Next, a gate metal electrode 5 having a film thickness of 200 to 400 nm is formed on the gate insulating film 4 and above the silicon semiconductor film 3. The gate metal electrode 5 is formed by a sputtering method, and the material is Ta, Al, AlS.
A metal containing Al such as i, AlTi or AlSc was used. In particular, a metal containing Al is preferable because a low resistance electrode wiring can be formed.

Next, an anodic oxide film 6 obtained by anodizing the gate metal electrode 5 is formed on the outer surface of the gate metal electrode 5.
The thickness of the anodic oxide film 6 is 50 nm to 1 μm. As described above, the structure shown in the sectional view of FIG.

Next, as shown in FIG. 1B, the gate insulating film 4 is etched in a self-aligned manner by using the gate electrode 5 and the anodic oxide film 6 as a mask to form a source / drain portion of the silicon semiconductor film 3. The exposed area. For the etching, wet etching using an etching solution or dry etching using plasma can be used for the etching.

Next, when an oxide film such as a natural oxide film is formed on the exposed surface of the silicon semiconductor film 3, the subsequent silicidation may become unstable. Therefore, a silicon oxide film such as a natural oxide film is formed. 1C, the metal film 7 is coated by the sputtering method in the state where there is as little as possible. The metal film 7 is preferably formed by exposing the silicon semiconductor film 3 and then performing a coating process of the metal film 7 in a non-oxidizing atmosphere such as a vacuum atmosphere or an N ₂ gas atmosphere. Alternatively, when an oxide film is formed on the surface of the silicon semiconductor film 3, the oxide film is removed by wet etching with a hydrofluoric acid-based etching solution or the like, or a plasma using a fluorine-based gas such as CHF ₃ as a raw material. May be removed by dry etching. Metal film 7 to cover
The film thickness of 10 may be 10 to 30 nm as long as it can pass the impurity ions to be implanted later. Metal film 7
The materials of are Mo, W, Cr, Ti, Ni, Pt, Pd,
A metal material that combines with silicon, such as Co or Ta, can be used.

Next, after the metal film 7 is coated, as shown in FIG. 1D, the impurity ions 8 containing hydrogen ions are implanted by using the ion implantation device described below. As the impurity ions, for example, ions containing phosphorus or boron element are applicable.

FIG. 2 is a front sectional view showing a schematic structure of the ion implantation apparatus used in the present invention. This ion implantation apparatus includes a gas inlet 101, a chamber 102 forming a plasma chamber for generating a plasma source, a high frequency power source 103 for exciting the plasma source, and a high frequency electrode for supplying high frequency power to the plasma source. 104 and a magnet 105 for increasing the ionization efficiency and adjusting the plasma shape, which form a plasma source. In addition, this ion implantation apparatus includes a first-stage ion acceleration power supply 106 for extracting ions from the plasma source, a second-stage ion acceleration power supply 107 for further accelerating the extracted ions, and a secondary ion acceleration power supply 107. A suppression power supply 108 for suppressing electrons, a porous electrode plate 109, and an insulator 110 for insulating each electrode plate are provided, and these constitute an ion acceleration unit. Furthermore, this ion implantation apparatus includes a substrate holder 111 on which a substrate 112 to be implanted is mounted. The substrate holder 111 has a rotation mechanism for improving uniformity.

Ion implantation by this ion implantation apparatus is
This is done as follows. A hydrogen-diluted source gas such as hydrogen-diluted PH ₃ or B ₂ H ₆ is introduced from the gas introduction port 101, and high-frequency power is applied to the high-frequency electrode 104 to form an excited plasma source. Substrate 112 mounted on the substrate holder 111 after being accelerated by
Ion implantation. As an example of implantation conditions in this case, hydrogen is introduced from a PH ₃ gas inlet of 5% dilution, high-frequency power for plasma formation is 100 to 200 W, total acceleration voltage of ions is 10 to 60 kV, and ion current density is 5 to 20 μA / cm ² , total ion implantation amount is 2 × 1
It was set to 0 ^{14 to} 5 × 10 ¹⁶ pieces / cm ² .

Although an ion implantation apparatus using a plasma source excited by high-frequency power is used, the ion implantation apparatus is not limited to this, and a plasma source generated by electron emission from a hot filament can be used.

As described above, since the ion implantation is performed after coating the metal film 7, it is possible to prevent the charge-up due to the ion beam. The electric charges possessed by the ion beam are emitted through the metal film 7 on the surface. This allows
Usually, there is an advantage that the dielectric breakdown of the device due to the charge-up caused by the ion implantation can be prevented. Next, as shown in FIG. 1E, the unreacted metal film 7 portion is etched and removed. In this way, the silicide layer 9 _S is formed on the surface of the silicon semiconductor 3 _S which is the impurity-implanted source portion, and the silicide layer 9 _D is formed on the surface of the silicon semiconductor 3 _D which is the impurity-implanted drain portion.

FIG. 3 is a graph showing the relationship between the measured value of the concentration of phosphorus element in the silicide layer by SIMS analysis and the sheet resistance of the silicide layer. The relationship in this Fig. 3 is
For example, it is a case where Mo having a film thickness of 20 nm is used for the metal film 7 to be coated and phosphorus-based ions including hydrogen ions are implanted at an acceleration voltage of 30 kV.

As can be understood from FIG. 3, in the region where the phosphorus element concentration is 2 × 10 ¹⁹ pieces / cm ³ or more, the sheet resistance can be made smaller than in the conventional case, but the phosphorus element concentration is 2 × 10 ¹⁹ pieces / cm 3. ^In the region of less than ³ , the surface resistance is as high as 10 kΩ / □ or higher, and there is no great merit. However, when the phosphorus element concentration exceeds 2 × 10 ²¹ pieces / cm ³ , the sheet resistance becomes almost saturated, and even if a larger amount is injected, the throughput is deteriorated and there is no merit. Therefore, by setting the phosphorus element concentration to 2 × 10 ¹⁹ pieces / cm ³ or more, preferably 2 × 10 ¹⁹ to 2 × 10 ²¹ pieces / cm ³ ,
A low resistance silicide layer can be easily formed.

Also, even if only the impurity element phosphorus is implanted to the same phosphorus concentration as above using an ion implanter for mass separation, the resistance value is only 5 to 10 times that of the present invention. There wasn't. Therefore, it is desirable to implant hydrogen ions at the same time as impurity ions. Especially SI
When the concentration of hydrogen element in the silicide layer was measured by MS analysis, it was found that the phosphorus concentration was in the above range and that it was 1 × 1.
It has been found that the fact that the hydrogen element is contained at a concentration of 0 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ is the point at which such a low resistance silicide layer can be formed. It has been found that when the hydrogen element deviates from this concentration range, the resistance becomes higher than twice the resistance of the silicide layer shown in FIG. Therefore, 1 × 1
It is very preferable that the hydrogen element is contained at a concentration of 0 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ .

Further, the same result was obtained by conducting the same experiment as for the boron element instead of the phosphorus element, so that the impurity element may be phosphorus or boron. Phosphorus may be used to make the silicon semiconductor N-type, and boron may be used to make it P-type.

Usually, it is necessary to raise the temperature for silicidation, and it is necessary to perform thermal annealing or irradiate strong light such as laser to cause silicidation reaction. 450 ° C
Although the resistance is only about 10 kΩ / □ at the low temperature below, thermal annealing treatment after ion implantation or intense light irradiation treatment such as laser irradiation is not necessary in this embodiment, and the temperature is 450 ° C. or lower in the subsequent steps, 10k even below 300 ° C
A silicide layer having a low resistance of Ω / □ to 100Ω / □ can be formed.

Next, on the substrate 1 in this state, as shown in FIG.
The interlayer insulating film 10 is formed as shown in (f). The inter-layer insulating film 10 is a SiO ₂ film formed by an atmospheric pressure CVD method or TEOS (Tetra-Ethyl) which has a good gap coverage.
-Ortho-Silicate, Si (OC
₂ H ₅ ) ₄ ) Atmospheric pressure CVD method using gas, plasma CVD
A SiO ₂ film was formed to a film thickness of 300 to 500 nm by the method. Or 200 to 250 ° C. by plasma CVD method
Alternatively, a silicon nitride film may be formed.

Finally, as shown in FIG. 1G, a contact hole is formed in the interlayer insulating film 10 portion on the silicon semiconductor 3 _S which is the source portion and the silicon semiconductor 3 _D which is the drain portion. Subsequently, the extraction electrodes 11 _S and 11 _{D in} which the contact holes are partially filled are formed by forming a film by a sputtering method and then patterning it. A thin film transistor was manufactured as described above.

As described above, according to this embodiment, since the gate electrode and the like can be masked to form the low resistance source / drain portion by self-alignment, the on-current due to the parasitic resistance of the source / drain portion can be obtained. Can be minimized. Further, when amorphous silicon is used for the silicon semiconductor film, it is amorphous silicon containing hydrogen in order to terminate the dangling bond of silicon. Since such an amorphous silicon film is usually formed at a substrate temperature of 200 to 300 ° C. by a plasma CVD method, a structure change or desorption of hydrogen occurs when a temperature of 300 ° C. or higher is passed. In addition, the transistor characteristics are deteriorated. Therefore, normally, a silicide layer or a source / drain portion having a low resistance could not be formed, but according to the present invention, a special annealing treatment is not required,
For example, a low resistance silicide layer of about 10 k to 100 Ω / □ can be formed at a low temperature of 300 ° C. or lower, and a good source / drain portion can be easily formed. Also, 30
Since the whole process of the transistor can be completed by the low temperature process of 0 ° C. or less, there is no deterioration of the transistor characteristics as described above.
Good transistor characteristics were obtained.

Further, since the gate electrode is covered with the anodized oxide film, it is possible to prevent a short circuit between the silicide layer on the source / drain portion and the gate electrode. In addition, there is a problem that a protrusion called hillock is generated in the A1 metal by the annealing process or the ion implantation process up to the final process and penetrates through the interlayer insulating film to cause a short circuit with the upper wiring or an increase in leak current. With the structure covered with the anodized oxide film, it is possible to suppress the growth of hillocks from Al in the anodized film, and to suppress the generation of hillocks, which is a problem of Al. Further, when a metal containing Al is used for the gate electrode, a low resistance gate electrode and a bus line can be formed. When applied to a liquid crystal display, it is preferable to use a low resistance material for the gate electrode and the bus line in order to reduce the delay due to the CR time constant, and it is very advantageous if an Al-based material that is a low resistance material can be used.

Example 2 Example 2 is a case where the present invention is applied to a thin film transistor having another structure. FIG.
(A)-(e) is process sectional drawing which shows the manufacturing method of the thin-film transistor of this Example, and FIG.4 (e) is sectional drawing which shows the thin-film transistor of this Example. The configuration of this thin film transistor will be described in the order of steps.

As shown in FIG. 4A, a gate metal electrode 22 having a film thickness of 200 to 400 nm is formed on an insulating substrate 21 made of glass. This gate metal electrode 22
Is formed by the sputtering method, and the material is Ta or AlS
A metal containing Al such as i, AlTi, and AlSc was used.
In particular, it is preferable that the metal containing Al can form the low resistance electrode wiring.

Next, on the outer surface of the gate metal electrode 22, the gate metal electrode 22 is anodized to have a film thickness of 20 nm.
An anodic oxide film 23 of about 1 μm is formed.

Next, the gate insulating film 2 having a film thickness of 50 to 300 nm is formed on the substrate 21 while covering the anodic oxide film 23.
4 is formed. The gate insulating film 24 is formed by plasma CV.
A silicon nitride film formed by the D method at 200 to 300 ° C. was used. Although a silicon nitride film is used here, a normal pressure C
VD method, sputtering method, low pressure CVD method, plasma CVD
It goes without saying that a SiO ₂ film having a film thickness of 50 to 300 nm formed by any one of the method and the remote plasma CVD method may be used. Needless to say, Al ₂ O ₃ , Ta ₂ O _5, or a combination thereof may be used. In addition, TEOS (Tetr, which has good step coverage)
a-Ethyl-Ortho-Silicate, Si
An SiO ₂ film formed by an atmospheric pressure CVD method using a (OC ₂ H ₅ ) ₄ ) gas or a plasma CVD method may be used. Needless to say, it is not necessary to use the silicon nitride film or the SiO ₂ film alone, and these films may be used in combination. Next, the island-shaped semiconductor film 25 having a film thickness of 30 to 200 nm is formed on the gate insulating film 24. This semiconductor film 25 is made of, for example, Si or SiGe.
Amorphous, microcrystalline, polycrystal, single crystal, etc. are used.

The semiconductor film 25 is formed as follows. That is, in the case of an amorphous silicon semiconductor, a film is formed by a plasma CVD method using SiH ₄ gas and H ₄ gas at a substrate temperature of 200 to 300 ° C. Further, in the case of a microcrystalline silicon semiconductor, a film is formed by a plasma CVD method at a substrate temperature of 200 to 400 ° C. with a SiH ₄ / H ₄ gas ratio of 1/30 to 1/100. Also,
In the case of a polycrystalline silicon semiconductor, an amorphous silicon film formed at a substrate temperature of 450 ° C. by a low pressure CVD method or an amorphous silicon film formed by the plasma CVD method described above is used in N ₂ gas at 550 to 600. A polycrystalline silicon film is formed by annealing at 24 ° C. for 24 hours. here,
As the source gas, Si ₂ H ₆ can be used in addition to SiH ₄ . Also, a polycrystalline silicon film may be formed from the beginning. Further, the above-mentioned amorphous silicon film may be irradiated with laser or light with a lamp to form a polycrystalline silicon film. In the case of a single crystal body, a silicon film is formed on the substrate by epitaxially growing silicon at a high temperature using a sapphire substrate or the like, or a single crystal silicon film is formed from an amorphous or polycrystalline silicon film by laser irradiation. Form. Alternatively, it may be a silicon wafer itself which is a single crystal.

The silicon semiconductor film thus manufactured is patterned by etching to form an island-shaped silicon semiconductor film 25.

Next, an insulating film 26 having a film thickness of 50 to 300 nm is formed on the silicon semiconductor film 25 above the anodic oxide film 23. The insulating film 26 is a plasma CV.
A silicon nitride film formed by the D method at 200 to 300 ° C. was used. Although a silicon nitride film is used here, a normal pressure C
VD method, sputtering method, low pressure CVD method, plasma CVD
Needless to say, a SiO ₂ film having a film thickness of 50 to 300 nm formed by any one of the method and the remote plasma CVD method may be used. Needless to say, Al ₂ O ₃ , Ta ₂ O _5, or a combination thereof may be used. In particular, at the time of patterning the insulating film 26, the insulating film 26 is formed and then covered with a photoresist to form the substrate 21.
By irradiating ultraviolet light from the side to expose the photoresist with the gate electrode 22 as a mask and processing the insulating film 26 into substantially the same shape as the gate electrode 22, the source / drain portions are formed in the subsequent steps. It is preferable that it can be self-aligned with.

The insulating film 26 is finally formed by etching, but at that time, the portions of the silicon semiconductor film 25 that will be the source / drain portions are exposed. For etching in this case, wet etching using an etching solution or dry etching using plasma can be used. As described above, FIG.
The structure shown in the sectional view of FIG.

Next, when an oxide film such as a natural oxide film is formed on the exposed surface of the silicon semiconductor film 25, the subsequent silicidation may become unstable. Therefore, a silicon oxide film such as a natural oxide film may be formed. 4B, the metal film 27 is coated by the spattering method in the state where there is as little as possible. The metal film 27 is preferably formed by, for example, exposing the silicon semiconductor film 25 and then performing a coating process of the metal film 27 in a non-oxidizing atmosphere such as vacuum or N ₂ gas atmosphere. Alternatively, when an oxide film is formed on the surface of the silicon semiconductor film 25, the oxide film is removed by wet etching using a hydrofluoric acid-based etching solution or the like, or a plasma using a fluorine-based gas such as CHF ₃ as a raw material. May be removed by dry etching. The film thickness of the metal film 27 to be coated may be 10 to 30 nm as long as it can pass the impurity ions to be implanted later. The material of the metal film 27 is Mo, W, Cr, Ti, Ni,
A metal material that combines with silicon, such as Pt, Pd, Co, or Ta, can be used. Next, after the metal film 27 is coated, as shown in FIG. 4C, impurity ions 28 containing hydrogen ions are implanted using the ion implanter shown in FIG. 3 as in the first embodiment. The impurity ion 28
The ion corresponds to an ion containing a phosphorus or boron element. In this case, the metal film 2 is formed as in the first embodiment.
7 has an advantage that charge-up caused by ion implantation can be prevented and dielectric breakdown of the device can be prevented.

Next, as shown in FIG. 4D, the unreacted metal film 27 is removed by etching. In this way, a silicide layer 29 _S is formed on the surface of the silicon semiconductor 25 _S that is the impurity-implanted source portion, and a silicide layer 29 _D is formed on the surface of the silicon semiconductor 25 _D that is the impurity-implanted drain portion.

In this case, for example, when phosphorus having a thickness of 20 nm is used for the metal film 27 to be coated and phosphorus-based ions including hydrogen ions are implanted at an acceleration voltage of 30 kV, S
The relationship between the measured value of the phosphorus element concentration in the silicide layer by the IMS analysis and the sheet resistance of the silicide layer was the same as that in FIG. 3 described above.

Therefore, the surface resistance can be made smaller than in the conventional case in the region where the phosphorus element concentration is 2 × 10 ¹⁹ pieces / cm ³ or more, but in the area where the phosphorus element concentration is less than 2 × 10 ¹⁹ pieces / cm ^3. It is as high as 10 kΩ / □ or higher, and there is no great merit. However, when the phosphorus element concentration exceeds 2 × 10 ²¹ pieces / cm ³ , the sheet resistance becomes almost saturated,
Even if a larger amount is injected, the throughput is deteriorated and there is no merit. Therefore, the phosphorus element concentration should be 2 ×
10 ¹⁹ pieces / cm ³ or more, preferably 2 × 10 ¹⁹ to 2 × 1
By setting the number to be ²¹ / cm ³ , a low-resistance silicide layer can be easily formed.

Even if phosphorus, which is an impurity element, is implanted to the same phosphorus concentration as described above by using an ion implantation apparatus for mass separation, the resistance value of the present invention is 5 to more than the resistance value of the present invention.
The resistance value was only about 10 times. Therefore, it is desirable to implant hydrogen ions at the same time as impurity ions. In particular, when the concentration of the hydrogen element in the silicide layer was measured by SIMS analysis, it was found that the phosphorus concentration was in the above range and that the hydrogen element was contained at a concentration of 1 × 10 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ . However, it was found that this is the point where such a low resistance silicide layer can be formed. It has been found that when the hydrogen element deviates from this concentration range, the resistance becomes higher than twice the resistance of the silicide layer shown in FIG.
Therefore, it is very preferable that the hydrogen element is contained at a concentration of 1 × 10 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ .

Further, when a similar experiment was conducted by using a boron element instead of the phosphorus element, the same result was obtained.
The impurity element may be phosphorus or boron. Phosphorus may be used to make the silicon semiconductor N-type, and boron may be used to make it P-type.

Usually, it is necessary to raise the temperature for silicidation, and it is necessary to perform thermal annealing or irradiate strong light such as laser to cause silicidation reaction. 450 ° C
Although the resistance is only about 10 kΩ / □ at the following temperature, the above-mentioned present invention does not require thermal annealing treatment after ion implantation or irradiation with strong light such as laser, and the temperature in the subsequent steps is 450 ° C. or less. , Especially below 300 ° C
A silicide layer having a low resistance of 0 kΩ / □ to 100 Ω / □ can be formed.

Finally, as shown in FIG. 4E, the extraction electrodes 30 _S and 30 _D are formed by sputtering and then patterning. A thin film transistor was manufactured as described above.

As described above, according to the present embodiment, since the source / drain portions can be formed in a self-aligned manner by using the gate electrode or the like as a mask, the on-current is reduced due to the parasitic resistance of the source / drain portions. Can be minimized. When amorphous silicon is used for the silicon semiconductor, the amorphous silicon contains hydrogen in order to terminate dangling bonds of silicon. Such an amorphous silicon film is usually formed by plasma CVD.
Since the film is formed by the method at a substrate temperature of 200 to 300 ° C., a structure change or desorption of hydrogen occurs at a temperature of 300 ° C. or higher, which causes deterioration of transistor characteristics. Therefore, normally, it was not possible to form a silicide layer or a source / drain portion having a low resistance, but according to the present invention, a special annealing treatment is not required, and for example, 30
A low resistance silicide layer of about 10 k to 100 Ω / □ can be formed at a low temperature of 0 ° C. or lower, and a good source / drain portion can be easily formed. Since all steps of the transistor can be completed at a low temperature step of 300 ° C. or lower, good transistor characteristics were obtained without the above-mentioned deterioration of transistor characteristics.

Although the unreacted metal film is removed by etching in FIG. 1 (e) of the first embodiment and FIG. 4 (d) of the second embodiment, it can be used as it is for electrodes and wiring. The part may be left without being removed. For example, after the step of FIG. 1D, a resist or the like is applied on the metal film 7, and patterning is performed by a photolithography technique in a state in which only the resist or the like corresponding to the desired portion of the metal film 7 is left. As shown in FIG. 5, the metal film 7 may be used as lead wires 12 _S and 12 _D. 5B is a plan view, and FIG. 5A is a cross-sectional view taken along the line AA ′ of FIG. 5B. This means that the second embodiment shown in FIG.
But you can do the same.

(Embodiment 3) In this embodiment, the present invention is applied to a TFT provided in a picture element portion of a liquid crystal display device.

FIG. 6 is a circuit diagram showing the liquid crystal display device of this embodiment, FIG. 7 is a perspective view showing the display portion of the liquid crystal display device, and FIG. 8 is a sectional view showing the display portion. . As shown in FIG. 6, in this liquid crystal display device, a gate line 1004 and a data line 1005 are formed in a display unit 1001 so as to intersect with each other, and a TFT 1006 is connected to a liquid crystal unit 1007 and an auxiliary capacitor 1008 near each intersection. Is formed. A gate line driving circuit 1002 and a data line driving circuit 1003 are provided around the display portion 1001. The TFT 100 is provided by the gate line 1004 and the data line 1005, respectively.
It is connected with 6.

As shown in FIG. 7, the TFT 1006, the scanning line 1004, the data line 1005 and the pixel electrode 2007.
Are formed on the substrate 2001. Further, as shown in FIG. 8, the gate electrode 5 of the TFT 1006 is connected to the gate line 10.
04, the silicon semiconductor 3 _{S serving} as the source portion is connected to the data line 1005 via the silicide layer 9 _S therebetween, and the silicon semiconductor 3 _{D serving} as the drain portion is interposed between the silicide layer 9 _D and the buffer metal for contact. 3009
It is connected to the pixel electrode 2007 via.

A liquid crystal alignment film 3012 is further formed on the substrate 2001, and the liquid crystal alignment film 3012 is provided so as to face the counter substrate 2002 on which the common electrode 2008, the color filter 2009 and the second liquid crystal alignment film 3015 are formed. A liquid crystal layer 2003 is provided in a gap between both substrates to form a liquid crystal panel, and a portion where the pixel electrode 2007 and the common electrode 2008 face each other is each pixel (the above-mentioned liquid crystal portion 1007).

Polarizing plates 2010 are provided on both outer sides of the liquid crystal panel.
2011, white light 201 is provided from the substrate 2001 side.
2 is illuminated and the transmitted light is displayed. TFT1006
On the substrate 2001, the source portion, the drain portion,
A semiconductor layer having a channel portion is formed, and a gate electrode 5 is formed on the semiconductor layer with a gate insulating film 4 interposed therebetween. An interlayer insulating film 3006 is formed on the gate electrode 5, and a data line 1005 is formed thereon. The data line 1005 is provided in the interlayer insulating film 3006 and is connected to the silicide 9 _S on the source portion through the contact hole.

A second interlayer insulating film 3008 is provided on the data line 1005, and a contact buffer metal 3009 and a pixel electrode 2007 are provided thereon. The pixel electrode 2007 includes the interlayer insulating film 3006 and the second
Through the contact hole formed in the interlayer insulating film 3008, and is connected to the silicide layer 9 _D above the drain portion through the contact buffer metal 3009. In addition, the auxiliary capacitance line 1005 and the second interlayer insulating film 3006.
The overlapping portion of the pixel power 2007 and the pixel power 2007 is an auxiliary capacitance portion 1008. Further, a protective film 3011 and a liquid crystal alignment film 3012 are formed on it.

Since the source / drain portion of the TFT 1006 can easily have a low resistance as described in the first and second embodiments, it is possible to minimize the reduction of the on-current due to the parasitic resistance of the source / drain portion. It is possible to obtain a liquid crystal display device having high display quality with excellent transistor characteristics.

In the third embodiment, the TFT of the first embodiment is applied to the TFT provided in the picture element portion of the liquid crystal display device, but the present invention is not limited to this, and the TFT of the second embodiment is applied to the liquid crystal display device. It can be applied to the TFT provided in the pixel portion.

[0076]

As described above, the semiconductor device of the present invention contains phosphorus or boron and contains 1 ×.
10 ¹⁹ to 4 × 10 ²¹ elements / cm ³ containing hydrogen element concentration,
It has a low resistance silicide layer. Therefore, when the silicide layer is formed on the electrodes and wirings of the semiconductor device, the electric conduction characteristics can be improved. Further, in this case, if the silicide layer contains phosphorus or boron element at a concentration of 2 × 10 ¹⁹ to 2 × 10 ²¹ pieces / cm ³ , the resistance can be further lowered.

In such a semiconductor device, a step of coating a metal film on a silicon semiconductor film and a silicide layer containing a phosphorus or boron element and a hydrogen element is provided between the silicon semiconductor film and the metal film. Since it can be manufactured by a step of implanting phosphorus or boron ions together with hydrogen ions, it can be silicided at a low temperature of 450 ° C. or lower, for example 300 ° C. or lower, without annealing at a high temperature or irradiating strong light such as laser light. Layers can be formed.

Further, even in the thin film transistor of the present invention, since the low resistance silicide layer is provided on the surface of the source / drain portion, the conductivity characteristic can be improved. Further, if the silicide layer contains phosphorus or boron element with a concentration of 2 × 10 ¹⁹ to 2 × 10 ²¹ pieces / cm ^{3, the} resistance can be further lowered. Further, such a thin film transistor can form a silicide layer having a low resistance at a low temperature of 450 ° C. or lower. Conventionally, it was not possible to form a silicide layer or a source / drain part having a low resistance at a low temperature, but according to the present invention, a special annealing treatment is not required, and the temperature is, for example, 300 ° C.
A low resistance silicide layer of about 10 k to 100 Ω / □ can be formed at the following low temperature, and a good source / drain portion can be easily formed. When amorphous silicon is used for the silicon semiconductor, it contains hydrogen so as to terminate the dangling bond of silicon, so that the amorphous silicon is obtained. Since such an amorphous silicon film is usually formed by a plasma CVD method at a substrate temperature of 200 to 300 ° C., a structure change or desorption of hydrogen occurs when a temperature of 300 ° C. or higher is passed. It causes deterioration of transistor characteristics. In the present invention, since all steps of the transistor can be completed in a low temperature step of 300 ° C. or lower, good transistor characteristics can be obtained without deterioration of the transistor characteristics as described above.

Further, since the ion implantation is performed after the metal film is coated, the charge-up caused by the ion implantation can be prevented, the dielectric breakdown of the device can be prevented, and the non-defective rate can be improved.

The silicide layer on the source / drain portion is formed in a self-aligned manner by etching the gate insulating film using the gate electrode as a mask. The resistance value can be made extremely small.

Further, in the liquid crystal display device of the present invention, by using the above-mentioned thin film transistor in the picture element portion, the voltage drop due to the resistance of the electrode wiring portion and the delay due to the time constant of CR are eliminated, and the liquid crystal display device of high display quality is obtained. Can be

As described above, it is intended to provide a semiconductor device having a low-resistance silicide layer, a manufacturing method thereof, a thin-film transistor having a low-resistance source / drain portion, a manufacturing method thereof, and a liquid crystal display device having high display quality. You can

[Brief description of drawings]

1A to 1G are process cross-sectional views showing a method of manufacturing a thin film transistor according to a first embodiment.

FIG. 2 is a front sectional view showing a schematic configuration of an ion implantation device used in the present invention.

FIG. 3 is a graph showing the relationship between the phosphorus element concentration in the silicide layer and the sheet resistance of the silicide layer.

4A to 4E are process cross-sectional views showing the method of manufacturing the thin film transistor of the second embodiment.

5 (b) is a plan view showing another manufacturing process of the thin film transistor of the present invention, and FIG. 5 (a) is a sectional view taken along line AA ′ of FIG. 5 (b).

FIG. 6 is a circuit configuration diagram showing a liquid crystal display device of a third embodiment.

7 is a perspective view showing a display unit of the liquid crystal display device of FIG.

8 is a cross-sectional view showing the display unit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Coating film 3 Silicon semiconductor film 4 Gate insulating film 5 Gate metal electrode 6 Anodized film 7 Metal film 8 Impurity ion containing hydrogen ions 9 _S , 9 _D Silicide layer 10 Interlayer insulating film 11 _S , 11 _D Extraction electrode 12 _S , 12 _D Extraction electrode 21 Substrate 22 Gate metal electrode 23 Anodized film 24 Gate insulating film 25 Silicon semiconductor film 26 Insulating film 27 Metal film 28 Impurity ion containing hydrogen ion 29 _S , 29 _D Silicide layer 30 _S , 30 _D Extraction Electrode 101 Gas inlet 102 Plasma chamber chamber 103 High-frequency power supply 104 High-frequency electrode 105 Magnet 106 First-stage ion acceleration power supply 107 Second-stage ion acceleration power supply 108 Secondary electron suppression power supply 109 Porous Electrode plate 110 Insulator 111 Substrate holder 112 Inject Plate 1001 Display unit 1002 Gate line driving circuit unit 1003 Data line driving circuit unit 1004 Gate line 1005 Data line 1006 TFT 1007 Liquid crystal unit 1008 Auxiliary capacitance 2001 Substrate 2002 Counter substrate 2003 Liquid crystal layer 2007 Pixel electrode 2008 Common electrode 2009 Color filter 2010 Polarizing plate 2011 Polarizing plate 2012 White light 3006 Interlayer insulating film 3008 Second interlayer insulating film 3009 Contact buffer 3011 Protective film 3012 Liquid crystal alignment film 3015 Second liquid crystal alignment film

Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/336 H01L 29/78 616 S

Claims (11)

[Claims] 1. Containing elemental phosphorus or boron, and 1 ×
A semiconductor device having a silicide layer containing a hydrogen element at a concentration of 10 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ . 2. The silicide layer is 2 × 10 ¹⁹ to 2 ×.
The semiconductor device according to claim 1, which contains a phosphorus or boron element at a concentration of 10 ²¹ pieces / cm ³ . 3. A thin film transistor having a semiconductor film containing silicon, a gate insulating film, and a gate electrode covered with an anodized oxide film, wherein phosphorus is formed on each surface of the impurity-doped source part and drain part. Or containing boron element and 1 × 10 ¹⁹
A thin film transistor provided with a silicide layer containing a hydrogen element at a concentration of 4 × 10 ²¹ pieces / cm ³ or less. 4. The silicide layer is 2 × 10 ¹⁹ to 2 ×.
The thin film transistor according to claim 3, wherein the thin film transistor contains phosphorus or boron at a concentration of 10 ²¹ pieces / cm ³ . 5. A step of coating a metal film on a silicon semiconductor film, and a silicide layer containing phosphorus or a boron element and a hydrogen element between the silicon semiconductor film and the metal film, together with hydrogen ions. Alternatively, a method of manufacturing a semiconductor device including a step of providing boron ions by ion implantation. 6. The silicide layer is 2 × 10 ¹⁹ to 2 × 1.
6. The semiconductor device according to claim 5, wherein the ion implantation is performed so as to contain a phosphorus or boron element having a concentration of 0 ²¹ pieces / cm ³ and a hydrogen element having a concentration of 1 × 10 ¹⁹ to 4 × 10 ²¹ pieces / cm ^3. Manufacturing method. 7. A method of manufacturing a thin film transistor, which comprises a step of forming a silicon semiconductor film, a step of forming a gate insulating film, and a step of forming a gate electrode covered with an anodized oxide film. A step of coating a metal film on the semiconductor film; and a step of ion-implanting a silicide layer containing a phosphorus or boron element and a hydrogen element between the silicon semiconductor film and the metal film together with a hydrogen ion and a phosphorus or boron ion. The manufacturing method of the thin-film transistor including the process of providing by doing. 8. The silicide layer is 2 × 10 ¹⁹ to 2 × 1.
8. The thin film transistor according to claim 7, wherein the ion implantation is performed so that the phosphorus or boron element has a concentration of 0 ²¹ pieces / cm ³ and the hydrogen element has a concentration of 1 × 10 ¹⁹ to 4 × 10 ²¹ pieces / cm ³ . Production method. 9. The thin film transistor according to claim 7, wherein the silicide layer on the source portion and the drain portion is formed in a self-aligned manner by etching the gate insulating film using the gate electrode as a mask. Production method. 10. The method of manufacturing a thin film transistor according to claim 7, wherein the step of providing the silicide layer and the subsequent steps are steps performed at a temperature of 450 ° C. or lower. 11. A liquid crystal display device using the thin film transistor according to claim 3 as a thin film transistor in a pixel portion.