JPH08179925A - Synchronization change-put circuit - Google Patents

Abstract

PURPOSE: To minimize the memory capacity and also to reduce the memory propagation delay time without causing any slip error by performing the automatic output control of a read pulse in response to the jitter variance. CONSTITUTION: A memory capacity control part 4 calculates the phase difference between a write pulse (c) received from a write address counter part 2 and a read pulse (d) received from a read address counter part 3. Based on this calculation result, the part 4 produces a control signal (e) for adjustment of the timing to output the pulse (d) and outputs the signal (e) to the part 3. The part 3 outputs the pulse (d) in response to the signal (e) received from the part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous transfer circuit, and more particularly to a synchronous transfer circuit when received data contains jitter in a transmission line.

[0002]

2. Description of the Related Art Conventionally, in this type of synchronous transfer circuit, as shown in FIG. 5, a memory section 10 for inputting / outputting data and a write address counter section 11 for generating a write pulse for the memory section 10 are provided. It is composed of a read address counter section 12 for generating a read pulse of the memory section 10 and a phase comparison section 13 for comparing the phases of the write pulse and the read pulse.

In this synchronous transfer circuit, when the data a input from the input data terminal is written in the memory section 10,
The write address counter unit 11 generates a write address and a write pulse based on the write clock input from the write clock terminal. The data a is written in the memory section 10 by these write address and write pulse.

When the data b is read from the memory unit 10 and output from the output data terminal, the read address counter unit 12 generates a read address and a read pulse based on the read clock input from the read clock terminal. The data b is read from the memory section 10 by the read address and the read pulse and is output from the output data terminal.

The phase comparator 13 compares the phases of the write pulse from the write address counter 11 and the read pulse from the read address counter 12, and outputs the comparison result to the read address counter 12. That is, the read address counter unit 12 outputs a read pulse according to the comparison result of the phase comparison unit 13. This synchronous transfer circuit is described in detail in the prior art of JP-A-4-369029.

[0006]

In the above-mentioned conventional synchronous transfer circuit, the output timing of the read pulse is changed according to the comparison result of the phase comparison unit which compares the phases of the write pulse and the read pulse. When the write pulse for writing the data in the memory section fluctuates greatly due to the jitter and overlaps with the read pulse, a slip error is detected in the phase comparison section.

In order to prevent this slip error, it is necessary to set a large phase difference between the write pulse and the read pulse in consideration of the fact that the amount of jitter varies greatly. However, if the actual amount of jitter is smaller than a preset value, the memory is wastefully operated, and the propagation delay time increases.

Therefore, the object of the present invention is to solve the above-mentioned problems, to automatically control the output of the read pulse by following the fluctuation of the jitter, and to minimize the used capacity of the memory. Another object of the present invention is to provide a synchronous transfer circuit that can reduce the propagation delay time of the memory without causing a slip error.

[0009]

A synchronous transfer circuit according to the present invention writes input data to a memory with a write pulse and reads data from the memory with a read pulse to perform synchronous transfer of input data. A replacement circuit, calculating means for calculating a phase difference between the write pulse and the read pulse, and a minimum value detecting means for obtaining a minimum value from the calculation results of the calculating means within a preset predetermined time, And a control means for controlling the output timing of the read pulse based on the minimum value obtained by the minimum value detection means.

[0010]

In the synchronous transfer circuit for performing the synchronous transfer of input data, the subtraction unit calculates the phase difference between the write pulse from the write address counter unit and the read pulse from the read address counter unit.

The minimum value processing unit obtains the minimum value within the preset constant time among the calculated values calculated by the subtraction unit, and the generation unit controls the output timing of the read pulse based on this minimum value. Generate a control signal.

As a result, the output control of the read pulse can be automatically performed following the fluctuation of the jitter, and the used capacity of the memory can be minimized. Further, the propagation delay time of the memory can be reduced without causing a slip error.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a synchronous transfer circuit according to an embodiment of the present invention includes a memory unit 1 for inputting and outputting data,
A write address counter section 2 for generating a write pulse c of the input data a, a read address counter section 3 for generating a read pulse d of the output data b, and a write pulse c.
And a memory capacity control section 4 for generating a control signal e for controlling the output timing of the read pulse d based on the read pulse d.

In the synchronous transfer circuit, when the input data a input from the input data terminal is written in the memory section 1, the write address counter section 2 writes the write address and the write pulse based on the write clock input from the write clock terminal. produces c. The input data a is written in the memory section 1 by the write address and the write pulse c.

When the output data b is read from the memory unit 1 and output from the output data terminal, the read address counter unit 3 generates a read address and a read pulse d based on the read clock input from the read clock terminal. . The output data b is read from the memory section 1 by the read address and the read pulse d and output from the output data terminal.

The memory capacity control unit 4 calculates the phase difference between the write pulse c from the write address counter unit 2 and the read pulse d from the read address counter unit 3, and outputs the read pulse d based on the calculation result. A control signal e for adjusting the timing is generated and output to the read address counter unit 3. That is, the read address counter section 3 outputs the read pulse d from the memory capacity control section 4 according to the control signal e.

FIG. 2 is a block diagram showing the configuration of the memory capacity control unit 4 of FIG. In the figure, the memory capacity control unit 4 uses the write pulse c from the write address counter unit 2.
And a subtraction unit 5 that calculates the difference between the read pulse d from the read address counter unit 3 and obtains the phase difference between them.
A minimum value processing unit 6 that obtains the minimum phase difference among the phase differences obtained by the subtraction unit 5 within a certain period, and a generation unit 7 that generates a control signal e from the minimum phase difference obtained by the minimum value processing unit 6. It consists of and.

The subtracting section 5 calculates the difference between the write pulse c from the write address counter section 2 and the read pulse d from the read address counter section 3, and the phase difference Y between them.
Is sent to the minimum value processing unit.

The minimum value processing unit 6 sequentially compares the phase differences Y obtained by the subtraction unit 5 within a certain fixed period. That is, the minimum value processing unit 6 compares the phase difference Y1 obtained by the previous subtraction unit 5 with the phase difference Y2 obtained by the current subtraction unit 5, and, for example, the phase difference Y2.
Is smaller than the phase difference Y1, the phase difference Y2 is held. By repeating this, the phase difference Y held until the end is set to the minimum phase difference Ymin.

The generator 7 generates the control signal e corresponding to the minimum phase difference Ymin value obtained by the minimum value processor 6. For example, when the value of the minimum phase difference Ymin is "+2", the load of the read address counter unit 3 is shifted by 2 bits later, that is, the read pulse d output from the read address counter unit 3 by 2 bits at a certain timing. The control signal e for delaying and outputting is generated.

The value of the minimum phase difference Ymin is "-2".
In this case, the load of the read address counter section 3 is shifted by 2 bits before, that is, the control signal e for outputting the read pulse d output from the read address counter section 3 by 2 bits earlier is generated.

Therefore, even if jitter of the transmission line fluctuates, the phase difference between the write pulse c and the read pulse d can be automatically corrected by following the fluctuation, so that the jitter can be reduced with a small memory capacity. Can respond to fluctuations. Therefore, it is possible to automatically cope with a transmission line in which the amount of jitter cannot be predicted, a transmission line in which the amount of jitter fluctuates, and the versatility of the synchronous transfer circuit can be expanded.

FIG. 3 is a diagram showing a variation of the phase difference Y obtained by the subtracting section 5 of FIG. In the figure, the solid line shows the fluctuation of the phase difference Y when it is not corrected by the minimum phase difference Ymin,
The broken line shows the fluctuation of the phase difference Y after the time t1 when the correction is made with the minimum phase difference Ymin at the time t1. In this case, the cycle of the time t1 is revised, for example, every day, one month, or one year depending on the expected phase fluctuation amount and the phase correction interval (which may cause an error after the correction). It has become so.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention. FIG. 4A is a timing chart showing a case where the read pulse d is delayed by 2 bits and outputted, and FIG. 4B is a timing chart showing a case where the read pulse d is outputted earlier by 2 bits.

When outputting the read pulse d with a delay of 2 bits, the control signal e is originally the timing when the read pulse d is output from the read address counter section 3 [FIG.
Since it is output before [] in [a], the output of the read pulse d is prohibited while the control signal e is being output in the read address counter section 3, and the read pulse d is output from the read address counter section 3. The corrected read pulse is output with a delay of 2 bits from the timing [FIG. 4 (a)].

When the read pulse d is output by 2 bits earlier, the control signal e is originally the timing when the read pulse d is output from the read address counter section 3 [FIG. 4].
(A)] is output before the read address counter section 3 outputs the read pulse d while the read signal counter section 3 outputs the control signal e, and the read address counter section 3 outputs the next read pulse d. The corrected read pulse is output [of FIG. 4 (a)] by 2 bits earlier than the output timing [of FIG. 4 (a)].

By these operations, the position of the read pulse d is kept at a minimum delay time from the write pulse c, and a phase difference that does not cause a slip error is secured.

As described above, in the synchronous transfer circuit for performing the synchronous transfer of the input data a, the phase difference between the write pulse c and the read pulse d is calculated by the subtracting unit 5, and a predetermined constant value of the calculated values is calculated. The minimum value in time is calculated by the minimum value processing unit 6, and the generation unit 7 generates a control signal e for controlling the output timing of the read pulse d based on this minimum value, so that the fluctuation of the jitter is tracked. Therefore, the output control of the read pulse can be automatically performed, the used capacity of the memory can be minimized, and the propagation delay time of the memory can be reduced without causing a slip error.

[0030]

As described above, according to the present invention, the phase difference between the write pulse and the read pulse is calculated in the synchronous transfer circuit for performing the synchronous transfer of the input data,
Among these calculation results, the minimum value within a preset time is calculated, and the output timing of the read pulse is controlled based on this minimum value, so that the output control of the read pulse is automatically controlled by following the fluctuation of jitter. Therefore, it is possible to minimize the used capacity of the memory and to reduce the propagation delay time of the memory without causing a slip error.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory capacity control unit in FIG.

FIG. 3 is a diagram showing a variation of a phase difference Y obtained by a subtracting section in FIG.

FIG. 4A is a timing chart showing a case where a read pulse is delayed by 2 bits and outputted, and FIG. 4B is a timing chart showing a case where a read pulse is outputted 2 bits earlier.

FIG. 5 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 memory unit 2 write address counter unit 3 read address counter unit 4 memory capacity control unit 5 subtraction unit 6 minimum value processing unit 7 generation unit c write pulse d read pulse

Claims (3)

[Claims] 1. A synchronous transfer circuit for performing synchronous transfer of input data by writing input data to a memory with a write pulse and reading data from the memory with a read pulse, the write pulse and the read pulse. Based on the minimum value obtained by the minimum value detection means, and a minimum value detection means for obtaining the minimum value from the calculation result of the calculation means within a preset predetermined time And a control unit that controls the output timing of the read pulse. 2. The synchronous transfer circuit according to claim 1, wherein the control means is configured to prohibit the output of the read pulse by the minimum value obtained by the minimum value detection means. 3. The calculation means is configured to perform a subtraction between the write pulse and the read pulse to calculate a phase difference between the write pulse and the read pulse. Item 2. The synchronous transfer circuit according to item 2.