JPH08178690A - Data logging device - Google Patents

Abstract

PURPOSE: To prevent the occurrence of an abnormality, and specify the cause of the abnormality by providing an abnormality judging circuit for outputting the normality and abnormality of an analog input signal. CONSTITUTION: When the voltage or current of an analog input signal exceeds the upper limit of an input condition, the level of the judgment signal of an abnormality judging circuit becomes high, and when it is lower than the upper limit value, the level becomes low. Since the Zener voltage of a Zener diode is set to a value exceeding the upper limit value of a normal voltage range inputted to an A/D converting circuit 9, and lower than the input withstand voltage of the circuit 9, the input voltage of a comparator CP and the circuit 9 is substantially limited to the Zener voltage, and the comparator CP and the circuit 9 are protected from the excessive input. Since counterflow preventing diodes Di1, Di2-Din and Do1, Do2-Don are commonly connected between the input parts of each channel ch1-chn, the abnormality judging circuit is normally worked even when any one of relays Y1, Y2-Yn is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is the result of A / D converting an input voltage signal or current signal, and subjecting the A / D converted value or the A / D converted value to certain data processing. The present invention relates to a data logging device that records

[0002]

2. Description of the Related Art For example, a private substation plant, a building substation plant, a building air conditioning plant, a steel plant,
In various facilities such as water and sewage water treatment plants, traffic information systems, pollution monitoring systems, etc., data logging devices that record the status of each equipment have been used to monitor the equipment and use them efficiently. Has been.

In general, such a data logging device is provided with an input section for inputting a pulse signal, a contact signal and an analog signal at a plurality of points. The analog signal is AD-converted and the AD-converted value is obtained. Record the results of certain data processing. For example, the voltage to be monitored,
The electric current value is detected, the electric power value of the monitoring target for each set time is obtained, and this is displayed and printed out.

[0004]

In the conventional data logging device, the voltage range of the signal to be input to the analog input section is 0 to 5 V or 1 to 5 V, and the current range is 4 to 20.
mA or 0 to 1 mA is standardized, and such a voltage range or current range (hereinafter referred to as "input condition"
Say. ), A transducer for converting the level of the signal under measurement is used.

However, in the conventional data logging device, when the value of the analog input signal to the data logging device exceeds the upper limit of the above standard due to a failure of the transducer or other causes, the value exceeding the maximum value of the measurement range is exceeded. Will be measured. However, since various calculations on the AD conversion value are performed on the assumption that the AD conversion value is within a predetermined measurement range, when the value of the analog input signal to the data logging device exceeds the upper limit of the above standard. , There is a possibility that an abnormality may occur at the time of the arithmetic processing on the AD conversion value. Such an abnormality will be recovered if the value of the analog input signal to the data logging device returns to within the above standard, so whether the cause is the data logging device side, the transducer or the measurement circuit side before it, etc. It was extremely difficult to identify the cause of the abnormality.

An object of the present invention is to provide a data logging device capable of preventing the occurrence of an abnormality and easily identifying the cause of the abnormality even when an analog signal exceeding the above-mentioned input conditions is input. It is in.

[0007]

According to the present invention, the data logging device detects whether or not the magnitude of an analog signal input to the data logging device exceeds a predetermined upper limit value. As described in 1, a reference voltage generation circuit that generates a reference voltage at the input section of the AD conversion circuit,
An abnormality determination circuit that compares a signal proportional to the analog input signal or the analog input signal itself with the reference voltage and outputs a determination signal indicating a normal / abnormal state of the analog input signal is provided.

Further, according to the present invention, in order to detect an abnormality of an analog signal input to a large number of input sections by using a small number of abnormality detection circuits, a plurality of analog input signal input sections and the analog input signal are provided. One of the plurality of analog input signals is selected between the AD conversion circuit and the A
A selection circuit for inputting to the D conversion circuit is provided, and the plurality of input sections are respectively coupled to the input section of the abnormality determination circuit via a backflow prevention diode.

[0009]

In the data logging device according to the first aspect, the AD
The reference voltage generation circuit provided in the input section of the conversion circuit generates the reference voltage, and the abnormality determination circuit compares the analog input signal with the reference voltage to determine whether the analog input signal is normal or abnormal. Is output. Therefore, if the abnormality determination circuit outputs a determination signal indicating an abnormal state when a signal that exceeds the input condition is input, a signal that exceeds the input condition is input from the determination signal output by the abnormality determination circuit. It is possible to determine whether or not it has been performed, and it is possible to prevent occurrence of an abnormal state due to measurement of an abnormal measured signal. In addition, the judgment signal that indicates an abnormal condition is output when an analog input signal that exceeds the input conditions is input.Therefore, when the judgment signal that indicates an abnormal condition is output, the cause of the malfunction is data logging. It becomes possible to immediately know that the device is outside the device.

In the data logging device according to claim 2,
One of the plurality of analog input signals is selected by the selection circuit and input to the AD conversion circuit, and the plurality of analog input signals are input to the input section of the abnormality determination circuit via the backflow prevention diode, so that the same abnormality occurs. The determination circuit makes it possible to determine the state when any of the plurality of analog input signals exceeds the input condition. As a result, it is possible to make an abnormality determination for a large number of analog input signals with a small number of abnormality determination circuits.

[0011]

1 is a block diagram showing the overall configuration of a data logging device according to an embodiment of the present invention. In FIG. 1, a CPU 1 executes a program previously written in the memory 2 and a program loaded from a hard disk device. The display control circuit 3 includes a display memory and a circuit that generates a display signal in accordance with the contents of the display memory. The CPU 1 writes display data corresponding to various monitor display contents into the display memory in the display control circuit 3. The print control circuit 5 controls the printer 6. The CPU 1 controls the print control circuit 5 to print out a daily report or a monthly report, for example. The hard disk control circuit 7 controls the hard disk drive device. C
The PU 1 accumulates and stores the logging data obtained at regular intervals in the hard disk drive device 8 via the hard disk control circuit 7. The AD conversion circuits 9 are provided on separate analog input boards (substrates), and convert analog signals input from the input channels of each board into digital data. The CPU 1 selectively reads the conversion value of each AD conversion circuit. As will be described later, the relay switching circuit 10 is a circuit that switches an analog input signal to the AD conversion circuit in each analog input board.
The CPU 1 selects a relay and selects an analog input signal for a predetermined AD conversion circuit. Judgment signal input circuit 1
Reference numeral 3 inputs the judgment signal output from the abnormality judgment circuit of each analog input board. The CPU 1 reads the determination result of each abnormality determination circuit from the determination signal input circuit 13. The abnormality display circuit 11 is a circuit for displaying which analog input board has an abnormality, and the CPU 1 causes the light emitting unit corresponding to the analog input board considered to be in an abnormal state to emit light. The alarm sound generation circuit 12 is a circuit that generates an alarm sound such as a buzzer, and the CPU 1 activates this alarm sound generation circuit when any of the abnormality determination circuits determines an abnormal state.

Next, FIG. 2 shows the configuration of the main part of one analog input board. In FIG. 2, Y1, Y
2 ,. ． ． Yn is the input channel c of the analog input signal
h1, ch2 ,. ． ． It is a relay that switches which input signal of chn is given to the AD conversion circuit 9. Di
1, Di2 ,. ． ． Din and Do1, Do2 ,. ． ． D
on is a plurality of channels ch1, ch2 ,. ． ． chn
Is a backflow prevention diode that connects an abnormality determination circuit in common to the input section of and also prevents a current (reflux current) flowing between different channels. In the input section of each channel, the resistor R1 is a current − that converts the input current into a voltage signal when the analog input signal is a current input.
It acts as a voltage conversion resistor, but has a high resistance when the analog input signal is a voltage input. Resistors R2, R3
Acts as a current limiting resistor. Since the input parts of the respective channels are commonly connected to the abnormality determination circuit via the diodes, the highest voltage among the voltages generated across the resistors R1 of the plurality of channels is applied to the abnormality determination circuit. In the abnormality determination circuit, the resistors R4 and R5 divide the input voltage to the abnormality determination circuit, and the resistors R6 and R5.
R7 divides the power supply voltage of the comparator CP to generate the reference voltage Vr. The comparator CP compares the reference voltage Vr with the voltage Vz generated by the measurement signal to obtain Vz
When> Vr, the determination signal is set to the high level, and when Vz ≦ Vr, the determination signal is set to the low level. Here, when the voltage or current of the analog input signal is the upper limit value of the input condition, that is, when the normal voltage range input to the AD conversion circuit 9 is 0 to 5 V, for example, it is input to the AD conversion circuit 9. The reference voltage Vr and the resistor R are set so that the divided voltage Vz becomes equal to the reference voltage Vr when an analog signal having a voltage of 5V is input to any of the channels.
The partial pressure ratio of 4, R5 is predetermined. Therefore, when the analog input signal exceeds the upper limit of the input condition, the determination signal becomes high level, and when it is less than the upper limit of the input condition, the determination signal becomes low level. Zener diode ZD includes diodes Di1, Di2 ,. ． ． Din and Do1, Do
2 ,. ． ． Channel ch1, ch via Don
2 ,. ． ． It is commonly connected to the input section of chn. The Zener voltage of the Zener diode ZD exceeds the voltage input to the AD conversion circuit 9 when the analog input signal is the upper limit value of the above input condition, and is less than the input withstand voltage of the comparator CP and the AD conversion circuit 9. Choose to be. For example, if the normal voltage range input to the AD conversion circuit 9 is 0 to 5V and the input withstand voltage of the comparator CP and the AD conversion circuit is less than 20V, the Zener voltage is selected to be 7V or the like.

Next, the operation of the circuit shown in FIG. 2 will be described. First, according to the output signal of the relay switching circuit 10 shown in FIG.
2. ． ． When Yn is opened, the analog input signal input from the channel ch1 is given to the AD conversion circuit 9. When the analog input signal is a voltage signal, the voltage signal is divided by the resistors R4 and R5, and the divided voltage Vz is given to the comparator CP. When the analog input signal is a current signal, the voltage dropped by the resistor R1 is divided by the resistors R4 and R5, and the divided voltage Vz is given to the comparator CP. Here, the resistors R2 and R3 also affect Vz, but since the values of the resistors R2 and R3 are sufficiently smaller than those of R4 and R5, R2 and R3 can be ignored. If the voltage or current of the analog input signal exceeds the upper limit of the above input condition, the determination signal becomes high level, and if it is below the upper limit value, the determination signal becomes low level. The Zener voltage of the Zener diode ZD exceeds the upper limit value of the normal voltage range input to the AD conversion circuit 9 and is set to a value less than the input withstand voltage of the AD conversion circuit 9. The input voltage of the AD conversion circuit 9 is limited to a substantially Zener voltage, and the comparator CP and the AD conversion circuit 9 are protected from excessive input. The backflow prevention diodes Di1, Di2. ． ．
Din and Do1, Do2. ． ． Since the Don is commonly connected between the input parts of the respective channels, the abnormality determination circuit is configured to include the relays Y1, Y2. ． ． It always works regardless of which Yn is selected.

Next, FIG. 3 shows a processing procedure of the CPU shown in FIG. 1 as a flowchart. First, which AD of the AD conversion circuits provided for each analog input board
Whether to input data from the conversion circuit is selected, and the determination signal of the selected input board is read (n1 → n2). If the determination signal is normal (low level), which channel of the selected board is to be input to the AD conversion circuit, that channel is selected, and the AD conversion value is read (n3 → n4 →
n5). Then, a predetermined process is performed on the AD converted value (n6). The processing of steps n5 and n6 is performed for all channels while switching channels. After that, the AD conversion circuits are switched and the processes of steps n2 to n7 are performed for all the AD conversion circuits (n8 → n1 ...). If the judgment signal is abnormal (high level), the number of the analog input board is displayed and an alarm sound is generated (n9 → n10).

Since the AD conversion value is read and processed in such a procedure, even if an analog input signal exceeding the input condition is input, the AD conversion value is not used for the processing, so that the abnormal operation is performed. Is prevented. Also, when an analog input signal that exceeds the input conditions is input, a warning sound is emitted and the board number on which the abnormal analog input signal is input is displayed. It is possible to immediately know whether the input has been made and it becomes easy to identify the defect.

[0016]

According to the data logging apparatus of the first aspect, when the signal exceeding the input condition is input, the abnormality determination circuit outputs the determination signal indicating the abnormal state. From the determination signal output from the circuit, it is possible to determine whether or not a signal exceeding the input condition is input, and it is possible to prevent occurrence of an abnormal state due to measuring an abnormal measured signal. In addition, the judgment signal that indicates an abnormal condition is output when an analog input signal that exceeds the input conditions is input.Therefore, when the judgment signal that indicates an abnormal condition is output, the cause of the malfunction is data logging. It becomes possible to immediately know that the device is outside the device.

According to the data logging device of the second aspect, since the abnormality judgment can be made for a large number of analog input signals by one or a small number of abnormality judgment circuits, the circuit scale by adding the abnormality judgment circuit is provided. There is no significant increase in.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data logging device that is an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of one analog input board.

FIG. 3 is a flowchart showing a processing procedure of a CPU in FIG.

[Explanation of symbols]

9-AD conversion circuit Di1, Di2. ． ． Din, Do1, Do2. ． ． D
on-backflow prevention diode ZD-zener diode CP-comparator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03M 1/12 A

Claims (2)

[Claims] 1. An AD conversion circuit for obtaining an AD conversion value of an analog input signal, and a data logging device for recording the AD conversion value or a result of performing constant data processing on the AD conversion value, wherein a reference voltage is set. Generates a reference voltage generation circuit, compares the analog input signal itself or a signal proportional to the analog input signal with the reference voltage, and
An abnormality determination circuit that outputs a determination signal indicating an abnormal state is
A data logging device, characterized in that the data logging device is provided in an input section of a D conversion circuit. 2. A selection circuit for selecting one of the plurality of analog input signals and inputting the selected analog input signal to the AD conversion circuit is provided between the input unit of the plurality of analog input signals and the AD conversion circuit. 3. The data logging device according to claim 1, wherein the plurality of input sections are respectively coupled to the input sections of the abnormality determination circuit via backflow prevention diodes.