JPH08139089A - Semiconductor device - Google Patents

Abstract

PURPOSE: To make an increase in the integration of a semiconductor device and the speedup of the device compatible by a method wherein an overall pattern is formed in such a way that the pattern can be miniaturized without lessening the number of metal wirings. CONSTITUTION: A lower side polycrystalline Si Layer 22a and an upper side polysilicide layer 23a, which are formed in such a way that one side of the layers 22a and 23a is used as a shunt of the other side, are electrically connected with each other via a polycrystalline Si layer 26b. As a result, the layer 26b and Al layers 34c can be arranged in three dimensions and an overall pattern can be miniaturized without lessening the number of the layers 34c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which one of the lower layer side wiring and the upper layer side wiring is a shunt of the other.

[0002]

2. Description of the Related Art FIG. 2 shows a DINOR type flash EE.
The equivalent circuit of PROM is shown. One group 11 of the DINOR type flash EEPROM is composed of a single selection transistor 12 and a plurality of memory cell transistors 13, and a plurality of memory cell transistors 13 connected in parallel to each other are connected in series to the selection transistor 12. It is connected to the. The main purpose of using the selection transistor 12 is to select the memory cell transistor 13 which is not selected.
Is to prevent disturbance from its drain.

The selection transistor 12 is controlled by a selection gate 14, and the memory cell transistor 13 is controlled by a word line 15 as a control gate. Also,
The main bit line 16 is connected to the drain of the selection transistor 12, and the source of the selection transistor 12 and the drain of each memory cell transistor 13 are connected to the sub bit line 1.
Connected by 7. A common source line 18 is connected to the source of each memory cell transistor 13.

FIG. 3 shows a conventional example of such a DINOR type flash EEPROM. In this conventional example, Si is formed in the element isolation region of the Si substrate by the LOCOS method.
The O ₂ film 21 is selectively formed, and the SiO ₂ film 21 is formed.
A SiO ₂ film (not shown) as a gate oxide film of the transistors 12 and 13 is formed on the surface of a lattice-shaped element active region surrounded by.

In the polycrystalline Si layers 22a and 22b, which are the first wiring layers on the Si substrate, the wiring below the selection gate 14 and the floating gate of the memory cell transistor 13 are formed. Polycrystalline Si layers 22a, 22b
Is covered with an insulating film (not shown). Then, the polycide layer 23a, which is the second wiring layer on the Si substrate, 2
3b, the wiring on the upper layer side of the selection gate 14 and the word line 1
And 5 are formed.

In the device active regions on both sides of the polycide layers 23a and 23b, a diffusion layer 24a as a drain of the selection transistor 12, a diffusion layer 24b as a source of the selection transistor 12 and a drain of the memory cell transistor 13, and a memory cell. The diffusion layer 24c serving as the source of the transistor 13 is formed, and the polycide layer 23 is formed.
The layers a, 23b, etc. are covered with an interlayer insulating film. A connection hole 25 reaching the diffusion layer 24b is provided in this interlayer insulating film or the like.

The sub-bit line 17 connected to the diffusion layer 24b through the connection hole 25 is formed in the polycrystalline Si layer 26a which is the third wiring layer on the Si substrate. A polycide layer may be used instead of the polycrystalline Si layer 26a.

The polycrystalline Si layer 26a and the like are covered with an interlayer insulating film, and the interlayer insulating film and the like have a contact hole 31 reaching the diffusion layer 24a and a contact hole 3 reaching the polycrystalline Si layer 22a.
2 and a connection hole 33 reaching the diffusion layer 24c. A, which is the fourth wiring layer on the Si substrate, is
In the I-layers 34a to 34c, the diffusion layer 24 is formed through the connection hole 31.
a main bit line 16 connected to a, a shunt wiring layer connected to both the polycrystalline Si layer 22a and the polycide layer 23a via a connection hole 32, and a common connected to a diffusion layer 24c via a connection hole 33. The source line 18 is formed.

The following Table 1 shows the operating voltage in the selected group 11.

[Table 1]

Table 2 below shows the operating voltage in the non-selected group 11.

[Table 2]

Table 3 below shows the operating voltages on the main bit line 16 and the Si substrate.

[Table 3]

[0012]

However, in the conventional example shown in FIG. 3, the main bit line 16, the shunt wiring layer and the common source line 18 are formed of the same Al layers 34a to 34c. There is. Therefore, these Al layers 34a to 34c
Must be spaced apart from each other in the extending direction of the word line 15, and since it is difficult to finely pattern the Al layer, the pattern pitch in the extending direction of the word line 15 is large.

On the other hand, in order to improve the operation speed, the common source line 18 is formed at a ratio of 1 to 16 of the main bit lines 16, and the wiring on the lower layer side of the select gate 14 is relatively high. Since it is formed of the polycrystalline Si layer 22a having the resistance, one shunt wiring layer is required for every 16 main bit lines 16 in order not to reduce the operation speed.

Therefore, if the number of common source lines 18 or shunt wiring layers is reduced and the pitch of the pattern in the extending direction of the word lines 15 is reduced, the operating speed is reduced. That is, in the above-mentioned conventional example, it is difficult to achieve both high integration and high speed.

[0015]

According to another aspect of the semiconductor device of the present invention, one of the wirings 22a and 23a on the lower layer side and the wiring on the upper layer side is a shunt of the other, and a conductive layer 26b containing a semiconductor.
The wirings 22a and 23a on the lower and upper layers are electrically connected to each other through the wiring.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, characterized in that the metal wiring 34c extends over the upper layer of the region where the connection is made.

A semiconductor device according to a third aspect is the semiconductor device according to the first or second aspect, characterized in that it has a wiring layer 26a in the same layer as the conductive layer 26b.

A semiconductor device according to a fourth aspect is the semiconductor device according to the second and third aspects.
The semiconductor device is a DINOR type and batch erase type non-volatile semiconductor memory device, the lower and upper wirings 22a and 23a are the selection gate 14 of the selection transistor 12, and the metal wiring is 34
c is a common source line 18 whose main component is Al, and the wiring layer 26a is a sub bit line 17.

[0019]

In the semiconductor device according to the first aspect, the lower and upper wirings 22a and 23a, one of which is a shunt of the other, are electrically connected to each other through the conductive layer 26b containing a semiconductor. Therefore, the metal wiring 34c is added to this semiconductor device.
However, the conductive layer 26b containing a semiconductor and the metal wiring 34c can be arranged three-dimensionally. Therefore, the entire pattern can be miniaturized without reducing the metal wiring 34c.

According to another aspect of the semiconductor device of the present invention, the wirings 22a and 23 on the lower and upper layers, one of which is a shunt of the other.
Since the metal wiring 34c extends above the region where the connection of a is made, the conductive layer 26b containing the semiconductor and the metal wiring 34c are three-dimensionally arranged, and the overall pattern is fine. Is.

In the semiconductor device of claim 3, the conductive layer 26b is provided.
Since the wiring layer 26a of the same layer as the
It is not necessary to provide a new wiring layer for 6b.

In the semiconductor device of claim 4, the select gate 1
Lower layer side and upper layer side wirings 22a and 23a which are 4
Are connected to each other for each common source line 18, the select gate 14 has a low resistance as a whole.

[0023]

EXAMPLE A DINOR type flash EEPRO is described below.
An embodiment of the present invention applied to M will be described with reference to FIGS. Note that, in the embodiment shown in FIG. 1, the components corresponding to those of the conventional example shown in FIG. 3 are denoted by the same reference numerals as those in FIG.

In order to manufacture this embodiment, as shown in FIG. 1, first, a SiO ₂ film 21 is selectively formed by a LOCOS method in an element isolation region of a Si substrate and surrounded by the SiO ₂ film 21. An SiO ₂ film (not shown) as a gate oxide film of the select transistor 12 and the memory cell transistor 13 is formed on the surface of the lattice-shaped element active region.

After that, the first wiring layer is formed on the Si substrate in a pattern that extends in the column direction with the width of the floating gate to be formed later and extends in the row direction with a width wider than that of the select gate 14. By processing the polycrystalline Si layer 22, the polycrystalline Si layer 22 is processed.
Layer 22 is covered with an insulating film (not shown). Then, the polycide layers 23a, 23a, which are the second wiring layers on the Si substrate,
In b, the wiring on the upper layer side of the selection gate 14 and the word line 15 are formed.

At this time, following the patterning of the polycide layers 23a and 23b, the polycrystalline Si layer 22 is continuously patterned to self-align with the upper wiring of the select gate 14 and the word line 15. The wiring below the select gate 14 and the floating gate of the memory cell transistor 13 are formed by the polycrystalline Si layers 22a and 22b. Then, the gate electrode (not shown) in the peripheral circuit portion is patterned, and at the same time, the portion of the polycide layer 23a where the shunt wiring layer will be formed later is removed.

Thereafter, a diffusion layer 24a as the drain of the selection transistor 12, a diffusion layer 24b as the source of the selection transistor 12 and the drain of the memory cell transistor 13, and a memory in the device active regions on both sides of the polycide layers 23a and 23b. A diffusion layer 24c serving as the source of the cell transistor 13 is formed. Then, the polycide layers 23a, 23b, etc. are covered with an interlayer insulating film (not shown), and the connection holes 35, 25 reaching the polycrystalline Si layer 22a and the diffusion layer 24b are opened in the interlayer insulating film, etc.

Next, in the polycrystalline Si layers 26a and 26b which are the third wiring layer on the Si substrate, the sub bit line 17 connected to the diffusion layer 24b through the connection hole 25 and the connection hole 35.
A shunt wiring layer connected to both the polycrystalline Si layer 22a and the polycide layer 23a is formed via. A polycide layer may be used instead of the polycrystalline Si layers 26a and 26b.

Thereafter, the polycrystalline Si layers 26a, 26b, etc. are covered with an interlayer insulating film (not shown), and the diffusion layers 24a, 24c are formed.
The connection holes 31 and 33 reaching the respective positions are opened in the interlayer insulating film or the like. Then, the fourth wiring layer Al on the Si substrate
In the layers 34a and 34c, the diffusion layer 24a is formed through the connection hole 31.
The main bit line 16 connected to the common source line 18 connected to the diffusion layer 24c via the connection hole 33 is formed.

In this embodiment manufactured as described above, the upper layer of the polycrystalline Si layer 26b serving as the shunt wiring layer is replaced by the Al layer 3
Since 4c extends, no planar area is needed for the shunt wiring layer. Moreover, since the polycrystalline Si layer 26b is the same layer as the polycrystalline Si layer 26a, the number of manufacturing steps has not increased and the manufacturing cost has not increased.

Although the present invention is applied to the DINOR type flash EEPROM in the above embodiments, the present invention can be naturally applied to semiconductor devices other than the DINOR type flash EEPROM.

[0032]

According to the semiconductor device of the first and second aspects, since the entire pattern can be miniaturized without reducing the metal wiring, both high integration and high speed can be achieved at the same time.

In the semiconductor device according to the third aspect, since it is not necessary to provide a new wiring layer for the conductive layer, the manufacturing cost does not increase even if the conductive layer is provided.

According to another aspect of the semiconductor device of the present invention, since the select gate has a low resistance as a whole, the operation speed controlled by the select transistor does not decrease.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a DINOR type flash EEPROM to which the invention of the present application can be applied.

FIG. 3 is a plan view of a conventional example of the present invention.

[Explanation of symbols]

 12 selection transistor 14 selection gate 17 sub-bit line 18 common source line 22a polycrystalline Si layer 23a polycide layer 26a polycrystalline Si layer 26b polycrystalline Si layer 34c Al layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (4)

[Claims] 1. One of the lower-layer side wiring and the upper-layer side wiring is a shunt of the other, and the lower-layer side wiring and the upper-layer side wiring are electrically connected to each other through a conductive layer containing a semiconductor. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein a metal wiring extends over an upper layer of the region where the connection is made. 3. The semiconductor device according to claim 1, further comprising a wiring layer which is the same layer as the conductive layer. 4. The semiconductor device is a DINOR type and batch erasing type non-volatile semiconductor memory device, the lower and upper wirings are selection gates of a selection transistor, and the metal wiring contains Al as a main component. 4. The semiconductor device according to claim 2, wherein the wiring layer is a sub-bit line.