JPH0799640B2 - Semiconductor memory device inspection method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly to a PROM (Programabl
The present invention relates to a semiconductor memory device suitable for application to an eROM) and an inspection method thereof.

[Background Art] As a method for inspecting data retention failure of EPROM (Erasable and Programmable ROM), all bits of the memory are once written to set each bit to "0", and then this is set to 150 to 200 ° C. It is conceivable to detect a defect by leaving it in a high temperature atmosphere, then reading all bits, and detecting what has changed from "0" state to "1" state. That is, if a defect or the like occurs in each insulating film between the EPROM substrate and the floating gate or between the floating gate and the control gate, the charge charged in the floating gate by writing (negative charge in the case of N-channel MOSFET). Is moved to the control gate or other portions by being left at a high temperature, the charge is lost (discharged), and the state is changed to the state where writing is not performed.

However, this method is effective for an original EPROM capable of erasing the written information by irradiating the bit, which has been written once, with ultraviolet rays or the like,
Recently proposed OTP (One Time Program) type E
It is impossible to directly use this method for PROM. In other words, this OTP-type EPROM is intended to simplify the product structure and reduce the cost by packaging the EPROM element in plastic or the like. If you do, you cannot erase it. Therefore, it cannot be used after encapsulating the package in the above-mentioned method, which presumes writing to all bits, and another inspection method (for example, writing information is inspected in a wafer state, erased by ultraviolet rays, and then sealed A method such as doing will be required.

The OTP type EPROM is, for example, HN482764P-3 shown in Hitachi, Ltd., May 1984, HITACHI IC MEMORY DATA BOOK, p263.

[Object of the Invention]

An object of the present invention is to provide a programmable semiconductor memory device typified by an OTP type EPROM capable of inspecting a data retention defect.

Another object of the present invention is to provide a semiconductor device inspection method capable of easily inspecting a programmable semiconductor memory device represented by an OTP type EPROM for data retention failure.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the present invention is a method for inspecting a semiconductor memory device including memory cells each having a control gate and a floating gate and connected in a matrix, in which the data line of the memory cell is kept at a low level potential. In this state, a stress applying step of aging under a predetermined condition while applying a write voltage to the word line, and applying a predetermined potential to each of the word line and the data line raises the threshold voltage by the stress application. And a charge gain inspection step of detecting a memory cell in a high threshold voltage state, and by applying a predetermined voltage to the data line while maintaining the low level potential of the word line, the threshold voltage is increased by the stress application. A device provided with a charge loss inspection process for detecting memory cells in a lowered low threshold voltage state There are, can check the memory cell defect without writing to each memory cell, thereby
PROM inspection can be enabled to improve the reliability of this type of PROM.

〔Example〕

FIG. 1 is an embodiment in which the present invention is applied to an OTP type EPROM, and a memory cell MC is constituted by an N channel MOSFET having a floating gate and a control gate. A plurality of word lines WL are connected to the control gate of each memory cell connected in a matrix, and a plurality of data lines DL are connected to the drain of each memory cell. Each word line WL is a depletion type N-channel MOSFET.
Is connected to the X decoder XD via a selection switch Sa. The other end of the word line WL has a write voltage boosted from the write voltage V _{PP of} 12.5V via the pull-up resistor Ra.
It is connected to a write voltage generation circuit WG that generates V _PP ′. Further, the X decoder XD has X address terminals A _{7 to} A _7.
An X address buffer XA having ₁₅ is connected.

On the other hand, each of the data lines DL is connected to a sense amplifier SA and an output circuit OC via a selection switch Sb composed of an N-channel MOSFET. The data line DL has an input circuit.
Connect the IC, and output terminals OC together with data terminals I / O _{0 to} I /
Connected to O ₇ . The gate of each of the selection switches Sb is Y
The Y selection line YL is connected to the selection line YL, and these Y selection lines YL are connected to the Y decoder via a selection switch Sc composed of a depletion type MOSFET.
It is connected to YD. The other of the Y selection lines YL is connected to the write voltage generation circuit WG via a pull-up resistor Rb. Further, the Y decoder YD has Y address terminals A _{0 to} A ₆
Is connected to the Y address buffer YA.

A write enable signal ▲ ▼ is applied to the gates of the selection switches Sa and Sc. The write enable signal ▲ ▼ is the pull-up resistor Ra, Rb.
Is also applied.

Further, a chip selection control circuit CC is connected to the X decoder XD, X address buffer XA, Y decoder YD, Y address buffer YA, sense amplifier SA, output circuit OC and input circuit IC, and a chip enable signal ▲ ▼ or output signal. Each chip is operated by the chip enable signal ▲ ▼. In the X address terminal,
An address control circuit AC is connected to the terminals A ₇ and A ₈ , and this address control circuit AC is connected to the X address buffer XA so that it can be controlled.

Details of the address buffer XA, the chip selection control circuit CC and the address control circuit AC are shown in FIG.

Each of the X address terminals A _{7 to} A ₁₅ has two inverters 1 and 2
Connected to one input terminal of the 2-input NOR circuit 3 via
Further, the output of the circuit 3 is connected to one input terminal of the 2-input NOR circuit 4. The output of the circuit 4 is input to the X decoder XD through the inverter 5 as one of the positive address signals a _{7 to} a ₁₅ and the other as the negative address signal ₇ to ₁₅ as it is.

On the other hand, in the chip selection control circuit CC, two inverters 6, 7, 8 and 9 are connected to the chip enable terminal ▲ ▼ and the output enable terminal ▲ ▼, respectively, and each input terminal of the 2-input NAND circuit 10 is connected. It has a circuit connected to. This ensures that an “H” will always be present when this chip is selected.
A signal will be output.

On the other hand, the address control circuit AC includes a stress judgment circuit ACa and an inspection judgment circuit ACb.

The stress judgment circuit ACa is a P-channel MOSFET 11 and C for load.
It has an inverter 12 for judging the MOS structure. The MOSFET of the inverter 12 has its common gate 13 powered by V _CC (5V).
The source 14 of the P-channel MOSFET is connected to the X address terminal A ₇ via the load MOSFET 11. Also, the output of the common drain 15, that is, the inverter
The output of 12 passes through the two inverters 16 and 17 and
2-input N provided for each of address terminals A _{7 to} A ₁₅
It is connected to the other input terminal of the AND circuit 4. The judgment inverter 12 has the X address terminal A _{7 due to} its structure.
5V or more (actually 7V due to the presence of load MOSFET 11)
The logic threshold voltage is set so that the "H" signal is output when a voltage (~ 8V or more) is applied.

In addition, the inspection / decision circuit ACb similarly uses the P-channel load MOSFE.
It has a T18 and an inverter 19 for judging the CMOS configuration, and connects its common gate 20 to the V _CC power supply, and also a P-channel MOS.
The source 21 of the FET is connected to the X address terminal A through the MOSFET 18.
Connected to ₈ . Similar to the inverter 12, the inverter 19 has its logical threshold voltage set so as to output the “H” signal when a voltage of ₇ to ₈ V or more is applied to the X address terminal A ₈ . The output of the common drain 22, that is, the output of the inverter 19 is connected to one input terminal of the 2-input NAND circuit 24 through one inverter 23. Two
The output of the NAND circuit 10 of the chip selection control circuit CC is connected to the other input terminal of the input NAND circuit 24. Also, 2
The output of the input NAND circuit 24 is connected to the other input terminal of the 2-input NOR circuit 3 provided corresponding to each of the X address terminals A _{7 to} A ₁₅ .

A method of inspecting the OTP type EPROM having the above configuration will be described below.

(1) Stress application process Set the OTP type EPROM to be inspected in a constant temperature bath and
It is aged at ~ 200 ° C.

At this time, the write enable signal is applied to the selection switches Sa, Sc, Ra and Rb, and the X address terminal
Apply 12.5V to A ₇ .

By applying 12.5V to the X address terminal A ₇ , the stress judgment circuit ACa in the address control circuit AC sends a “H” signal from the judgment inverter 12 and this is applied to each X
2-input N provided for each of address terminals A _{7 to} A ₁₅
It is input to one input terminal of the OR circuit 4. Therefore,
The output of each 2-input NOR circuit 4 is output to each X address terminal A ₇
~ The status becomes "H" regardless of the address signal of A ₁₅ a ₇
~ A ₁₅ are all set to "H". As a result, all of the selection switches Sa are opened together with the write enable signal, and the write voltage V _PP ′ of the write voltage generation circuit WG is applied to the word lines WL of all the memory cells MC, that is, the control gates. To be done. At this time, all the data lines DL are in the non-written state, that is, the non-selected state, and the source and drain of each memory cell MC are set to the substrate potential (OV) or a state close thereto (a floating state close to OV). It

When this electric field stress is applied between the control gates, floating gates, and substrates of all the memory cells by continuing this aging for several hours, the following phenomenon occurs in the defective memory cells.

That is, in the memory cell having a defect in the insulating film 102 between the P-type silicon semiconductor substrate 100 and the floating gate 101 as shown in FIG.
The electrons (negative charges) on the substrate 100 side, which are attracted to the electric field of 1, leak through the defects and are charged in the floating gate 101. As a result, the threshold voltage V _th of the memory cell is increased (charge gain) as in the case of so-called writing.

On the other hand, in the memory cell in which the insulating film 104 between the floating gate 101 and the control gate 103 has a defect as shown in FIG. 7B, the positive charge of the control gate 103 is driven to the substrate 100 side, and the floating occurs through the defect. The gate 101 is charged. Control gate 1
It is also considered that the holes in the floating gate 101 left after the electrons in the floating gate 101 are drawn into the control gate 103 by the electric field of 03 are left. As a result, the threshold voltage of that memory cell
V _th is reduced (charge loss) and the memory cell has a depletion characteristic.

These are all defective memory cells that impair the normal operation of EPROMs, and therefore the presence or absence of these memory cells is inspected during or after aging. Then, a chip having such a memory cell is excluded as a defective product.

(2) Charge Gain Inspecting Step The memory cell whose threshold voltage V _th has risen due to the charge gain is the same as in the written state, and therefore the conventional reading method can be used as it is.

That is, the write enable signal WE is sent to each selection switch S
The selection switches Sa and Sc are opened by adding them to a and Sc, and on the other hand, X address terminals A _{7 to} A ₁₅ and Y address terminal A _0.
Input address signals to ~ A ₆ . As a result, the V _CC voltage is applied to the selected one word line WL, one selection switch Sb corresponding to the selected one Y selection line YL is opened, and the selected data line DL is applied to the sense amplifier SA. Connecting. Then, the sense amplifier SA detects a change in the potential of the data line DL. The potential of each data line is precharged to, for example, 2V in advance. As shown in FIG. 4A, in the normal memory cell MC1, the word line WL is turned on when the V _CC voltage (= 5 V), so that the read voltage to the sense amplifier is set to 0 V. However, in the defective memory cell MC2, the precharge voltage (2V) can be directly detected as the read voltage because the word line WL is in the off state due to the rise of the threshold voltage even when the voltage is the V _CC voltage. By doing this for all memory cells, defective memory cells in the charge gain state can be inspected.

Even when the threshold voltage of the memory cell does not rise to the voltage applied to the word line (when the charge gain is small), a slight change in the potential of the data line is detected and the memory cell is defective. You can know that.

(3) Charge loss inspection process When inspecting charge loss, 1 at X address terminal A ₈ .
Apply 2.5V. As a result, the judgment inverter 19 of the inspection judgment circuit ACb outputs the "H" signal, and the inverter 23 makes it the "L" signal. The 2-input NAND circuit 24 receives the "L" signal and the "H" signal of the NAND circuit IC in the chip selection control circuit CC, and outputs the "H" signal. The output of this circuit 24 is input to the 2-input NOR circuit 3 corresponding to each X address terminal A _{7 to} A ₁₅ . As a result, the circuit 3 outputs the "L" signal regardless of the level of the address signal. Then, in the 2-input NOR circuit 4,
Output of circuit 3 and stress judgment circuit obtained in the same manner as above
"H" is output signal at the "L" signal ACa, and a state of "L" and a ₇ ~a ₁₅ signals by passing through an inverter 5.

As a result, each word line WL is set to 0V. On the other hand, signals are input to the Y address terminals A _{0 to} A _{6 as} in the case of normal reading, and the respective data lines DL are sequentially connected to the sense amplifier SA. Then, by the sense amplifier SA, for example, 2V in advance
The change in the potential of the data line DL precharged to is detected. Therefore, if there is a defective memory cell MC3 with a low threshold voltage (depletion state) in the charge loss state as shown in FIG. The potential of the line drops, and the read voltage in the sense amplifier SA becomes 0V. On the other hand, the normal memory cell MC4 is in the OFF state because the word line is 0V, and the precharge voltage (2V) remains as it is.
It can be detected by SA. By performing this for each data line, the defective memory cell in the charge loss state can be inspected.

In the case of this inspection, the read inspection may be performed on all the data lines DL at the same time, and if even one defective memory cell exists, the read voltage in the sense amplifier SA is
It becomes 0V.

Further, as in the charge gain inspection step, even a small change in the threshold voltage of the memory cell can be detected.

As described above, by inspecting the charge gain and the charge loss, it is possible to reliably inspect two types of defects that occur in the memory cell due to aging. And
Even if this test is performed, normal memory cells are not charged with positive or negative charges. Therefore, normal (non-defect) OTP type EPROM is not written, and the red writing state Can be supplied to the user at.

Further, in the above-mentioned configuration, 12.5V is applied to the X address terminals A ₇ and A ₈ during the stress application process and the charge loss inspection process, respectively.
By applying a voltage (7 to 8 V or more), the peripheral circuit of the EPROM can be automatically set to the stress application state or the charge loss inspection state, and for that purpose, it is not necessary to provide a new terminal. It goes without saying that the terminals used for the inspection may be address terminals other than A ₇ and A ₈ .

〔effect〕

(1) Since an address control circuit is attached to an address circuit that selects a word line of a memory cell, and this address control circuit is configured to be able to apply a write voltage to all the word lines, it is possible to apply it to all the word lines. High temperature aging can be performed in the state where the write voltage is applied, and a defective memory cell can be caused to have a charge gain and a charge loss.

(2) Since the address control circuit is configured to control all of the word lines to the 0V state, the presence of the memory cell in the charge loss state can be detected promptly by simply detecting the read voltage applied to the data line. it can.

(3) The stress judgment circuit and the inspection judgment circuit for controlling the above (1) and (2) of the address control circuit are both configured to control the address circuit according to the voltage applied to the address terminal. Therefore, the address control circuit can be arranged without increasing the number of address terminals.

(4) Applying a write voltage to the word line of the memory cell, while applying a stress while aging the data line at 0V level, and applying a predetermined voltage to the word line and the data line to increase the voltage. Charge gain inspection process for inspecting memory cells with threshold voltage and word line 0V
A memory cell defect is inspected by a charge loss inspection process that inspects depleted memory cells by applying a predetermined voltage to the data line while maintaining the level, so write to all memory cells as before. OTP type EPROM that can detect defective memory cells
As described above, it is possible to highly reliably inspect a semiconductor memory device that cannot be inspected for writing.

(5) In the stress application process, the address control circuit acts to simultaneously apply the write voltage to all the word lines to perform aging. In the charge loss inspection process, the address control circuit also acts to simultaneously set all the word lines to 0V. Since the data line is read, the stress application step and the charge loss inspection step can perform the stress application and the inspection for all the memory cells simultaneously or substantially at the same time, and the inspection time can be shortened.

(6) The defect inspection of the memory cell can be performed even after sealing in a package such as plastic which is opaque to ultraviolet rays.

(7) According to the above (6), it is possible to detect a defect of the memory cell caused by various causes (mechanical stress during dicing, mold stress, etc.) after completion of the wafer.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the scope of the invention. Nor.

For example, the X decoder XD may be controlled when stress is applied. For example, as shown in FIG. 5, X decoder XD
In order to configure the above, a switch MOSFET 60 is provided in series in a part of a CMOS 50a to n column composed of a plurality of P channel MOSFETs 30a to 30n and N channel MOSFETs 40a to 40n.
Is turned off, the selection switches Sa of all the word lines WL can be opened regardless of the address signal, and 12.5 V of the write voltage generating circuit can be applied to each word line WL. In addition, without the above X decoder XD configuration and without additionally providing the address control circuit described above,
It is also possible to select a word line based on a normal address signal at the time of stress application or charge loss inspection and apply 12.5V to 0V. However, this method requires more time than the previous example in order to secure the required stress application time for each memory cell, especially in the stress application process.

[Field of application]

In the above description, the case where the invention mainly made by the present inventor is applied to the OTP type EPROM which is the field of application which is the background has been described, but the present invention is not limited thereto and is applied to a normal EPROM. Good. Further, the present invention can be widely applied to a semiconductor memory device including a MISFET having a floating gate and a semiconductor memory device using various types of charge storage type transistors such as an EEPROM.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a logic circuit diagram of essential parts, and FIGS. 3A and 3B are charge gains of memory cells.
A schematic cross-sectional view showing the state of charge loss, FIGS. 4 (A) and 4 (B) are partial circuit diagrams for explaining each inspection method of charge gain and charge loss, and FIG. 5 is a modification example. FIG. 3 is a partial circuit diagram for MC ... Memory cell, WL ... Word line, DL ... Data line, Sa, Sb,
Sc ... Selection switch, Ra, Rb ... Pull-up resistance, WG ... Write voltage generation circuit, XD ... X decoder, XA ... X address circuit,
YD ... Y decoder, YA ... Y address circuit, SA ... Sense amplifier, OC ... Output circuit, IC ... Input circuit, AC ... Address control circuit, ACa ... Stress determination circuit, ACb ... Inspection determination circuit, CC ...
Chip selection control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Minor Fukuda 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor, Rei Meguro 1450, Kamimizuhonmachi, Kodaira, Tokyo Hitachi, Ltd. Musashi Factory (56) References JP-A-59-36400 (JP, A) JP-A-57-103195 (JP, A)

Claims (3)

[Claims] 1. A method for inspecting a semiconductor memory device including memory cells each having a control gate and a floating gate and connected in a matrix, wherein a data line of the memory cell is kept at a low level potential. A stress applying step of aging under a predetermined condition while applying a write voltage to the word line, and applying a predetermined potential to each of the word line and the data line raised the threshold voltage by the stress application. A charge gain inspection step of detecting a memory cell in a high threshold voltage state, and a threshold voltage is lowered by the stress application by applying a predetermined voltage to the data line while maintaining the low level potential of the word line. And a charge loss inspection step of detecting a memory cell in a low threshold voltage state. Method for inspecting semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein in the stress applying step, the write voltage is applied to all the word lines at the same time while keeping all the data lines at a low level potential at the same time. Inspection method. 3. The semiconductor memory device according to claim 1, wherein in the charge loss inspection step, a predetermined voltage is applied to each data line while simultaneously maintaining all word lines at a low level potential. Inspection method.