JPH0766524A - Printed board - Google Patents

Printed board

Info

Publication number
JPH0766524A
JPH0766524A JP5216355A JP21635593A JPH0766524A JP H0766524 A JPH0766524 A JP H0766524A JP 5216355 A JP5216355 A JP 5216355A JP 21635593 A JP21635593 A JP 21635593A JP H0766524 A JPH0766524 A JP H0766524A
Authority
JP
Japan
Prior art keywords
chip
components
common land
land
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5216355A
Other languages
Japanese (ja)
Inventor
Takashi Usuha
隆 薄葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Group Corp
Original Assignee
Aiwa Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aiwa Co Ltd filed Critical Aiwa Co Ltd
Priority to JP5216355A priority Critical patent/JPH0766524A/en
Publication of JPH0766524A publication Critical patent/JPH0766524A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To provide a printed board in the increased package density in the long direction by shortening the chip component interval keeping in-series arrangement state of chip components furthermore enhancing the solderability of the chip components onto a common land. CONSTITUTION:Within the printed substrate comprising two each of chip type circuit components arranged in-series, the two each of chip type circuit components are provided in almost contact state on a common land 20a capable of holding the electrical connection to the two each of chip type circuit parts in common. At this time, the common land 20a is provided to be protruded from both sides of respective two each of chip components 11a, 11b.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種の電子機器に適用
されるプリント基板に係り、特にチップ状回路部品を直
列に配置させたプリント基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board applied to various electronic devices, and more particularly to a printed circuit board in which chip-shaped circuit components are arranged in series.

【0002】[0002]

【従来の技術】抵抗やコンデンサ等のチップ状回路部品
(以下チップ部品と称す)を用いて基板上に配線パター
ンを形成する場合、チップ部品実装密度が高い程、すな
わちチップ部品間隔が狭い程、多くのチップ部品を一枚
の基板上に実装することができ、基板の小型化が図れ
る。図5に小型の角形チップコンデンサ(チップ部品)
の斜視図を示す。このような角形チップコンデンサの1
つのタイプである2125タイプのチップコンデンサ1
は図5に示した、長さ(L)が約2mm、幅(W)が約
1.25mmそして厚さ(t)が約0.6mmの規格で
形成される。
2. Description of the Related Art When a wiring pattern is formed on a substrate by using chip-shaped circuit components such as resistors and capacitors (hereinafter referred to as chip components), the higher the chip component mounting density, that is, the narrower the chip component spacing, Many chip components can be mounted on one board, and the board can be miniaturized. Figure 5 shows a small rectangular chip capacitor (chip component).
FIG. One of such rectangular chip capacitors
Two types of 2125 type chip capacitors 1
Is formed according to the standard shown in FIG. 5 having a length (L) of about 2 mm, a width (W) of about 1.25 mm and a thickness (t) of about 0.6 mm.

【0003】上記コンデンサ1等のチップ部品を長手方
向に直列配置する構成を図6に示す。特に、図6(a)
は平面図を示し、図6(b)は図6(a)のX−X′断
面図である。図6(a)では特にランド配置をわかり易
くするため、半田(図6(b)の4)の図示を省略して
示す。図6(a)及び図6(b)に示すように、プリン
ト基板2上に配設されたそれぞれランド3a,3bとラ
ンド3c,3d上に、チップ部品1aとチップ部品1b
の2つのチップ部品が直列に半田付け(半田:4)接続
配置されている。このようなチップ部品1aと1bの直
列配置では、上記2125タイプのチップ部品を使用し
た場合、各チップ部品に関連するランドのセンターライ
ン(従って各チップ部品間のセンターライン)間の間隔
が3.5mm,従って長さが2mmのチップ部品では部
品間の間隔が1.5mmとなる。
FIG. 6 shows a configuration in which chip components such as the capacitor 1 are arranged in series in the longitudinal direction. In particular, FIG. 6 (a)
Shows a plan view, and FIG. 6B is a sectional view taken along line XX ′ in FIG. In FIG. 6A, the solder (4 in FIG. 6B) is omitted in order to make the land arrangement particularly easy to understand. As shown in FIGS. 6A and 6B, the chip component 1a and the chip component 1b are provided on the lands 3a and 3b and the lands 3c and 3d, respectively, which are arranged on the printed circuit board 2.
The two chip components are soldered (solder: 4) and connected in series. In such a serial arrangement of the chip components 1a and 1b, when the above-mentioned 2125 type chip components are used, the distance between the center lines of the lands associated with the respective chip components (and thus the center lines between the respective chip components) is 3. For a chip component having a length of 5 mm and a length of 2 mm, the distance between the components is 1.5 mm.

【0004】[0004]

【発明が解決しようとする課題】上記各チップ部品1
a,1b間の間隔は、従来、半田量の適正化のためのラ
ンドパターン設計部品配置を含む基板設計精度、チップ
部品を基板に実装するための実装機の実装精度等による
種々の制限から、上述した約1.5mmより短くするこ
とができなかった。従って、図6に示したような従来の
チップ部品1aと1bの直列配置構成では実装密度の向
上が困難であった。
Each of the above chip parts 1
The spacing between a and 1b has conventionally been limited due to various restrictions due to board design accuracy including land pattern design component placement for optimizing the amount of solder, mounting accuracy of a mounting machine for mounting chip components on a substrate, and the like. It could not be made shorter than about 1.5 mm described above. Therefore, it is difficult to improve the mounting density in the conventional serial arrangement configuration of the chip components 1a and 1b as shown in FIG.

【0005】また、プリント基板上へのチップ部品の半
田付け実装は当然のことながらプリント基板上のランド
への半田付け性が要求されている。
Further, as a matter of course, the soldering mounting of the chip component on the printed board is required to be solderable to the land on the printed board.

【0006】本発明はチップ部品の長手方向での直列配
置状態で、チップ部品間隔を縮小して実装密度を向上
し、且つチップ部品のランドへの半田付け性を向上した
プリント基板を提供することを目的とする。
The present invention provides a printed circuit board in which chip components are arranged in series in the longitudinal direction to reduce the interval between the chip components to improve the mounting density and to improve the solderability of the chip components to the land. With the goal.

【0007】[0007]

【課題を解決するための手段】請求項1に記載された本
発明に係るプリント基板は、2個のチップ状回路部品を
直列に配置してなるプリント基板において、前記2個の
チップ状回路部品に対して電気的接続を共有し得る共通
ランド上で前記2個のチップ状回路部品を互いに接した
状態で設けてなり、且つ前記2個のチップ部品を前記共
通ランド上に配置した際、該共通ランドが該2個のチッ
プ部品のそれぞれの両側に突出するように設けられてな
ることを特徴とする。
A printed circuit board according to a first aspect of the present invention is a printed circuit board in which two chip-shaped circuit components are arranged in series. The two chip-shaped circuit components are provided in contact with each other on a common land capable of sharing electrical connection with each other, and when the two chip components are arranged on the common land, A common land is provided so as to project on both sides of each of the two chip components.

【0008】請求項2に記載された本発明に係るプリン
ト基板は、前記共通ランド上で接する2個のチップ状回
路部品の直列配置長手方向全長に、該長手方向の両側に
所定の半田付け代長さを加えた長さを、前記2個のチッ
プ状回路部品の直列配置実装長さとすることを特徴とす
る。
According to a second aspect of the present invention, in a printed circuit board according to the present invention, two chip-shaped circuit components which are in contact with each other on the common land are arranged in the entire length in the longitudinal direction, and predetermined soldering margins are provided on both sides in the longitudinal direction. It is characterized in that a length obtained by adding the lengths is set as a serial arrangement mounting length of the two chip-shaped circuit components.

【0009】[0009]

【作用】請求項1記載のプリント基板によれば、2個の
チップ状回路部品に対して電気的接続を共有し得る共通
ランド上で前記2個のチップ状回路部品を互いに接した
状態で設けられているため、チップ状回路部品の部品間
隔をほぼ0に抑えることが可能となり、実装密度の向上
が実現できる。しかも本プリント基板によれば前記2個
のチップ部品を前記共通ランド上に配置した際、該共通
ランドが該2個のチップ部品のそれぞれの両側に突出す
るように設けられているため、その突出部を半田付けに
有効に適用でき、チップ部品の側面での半田付け性を向
上させることができる。
According to the printed circuit board of the present invention, the two chip-shaped circuit components are provided in contact with each other on a common land capable of sharing electrical connection with the two chip-shaped circuit components. Therefore, it is possible to suppress the component interval of the chip-shaped circuit components to almost zero, and the packaging density can be improved. Moreover, according to the present printed circuit board, when the two chip components are arranged on the common land, the common land is provided so as to project to both sides of the two chip components. The portion can be effectively applied to soldering, and the solderability on the side surface of the chip component can be improved.

【0010】請求項2のプリント基板によれば、前記共
通ランド上で接する2個のチップ状回路部品の直列配置
長手方向全長に、該長手方向の両側に所定の半田付け代
長さを加えた長さを、前記2個のチップ状回路部品の直
列配置実装長さとしているため、チップ状回路部品の部
品間隔をほぼ0に抑えることが可能となり、しかもチッ
プ部品の直列配置の半田付け性をより向上した状態で実
装密度の向上が実現できる。
According to the printed circuit board of claim 2, a predetermined soldering margin length is added to both sides in the longitudinal direction of the total length in the longitudinal direction of the two chip-shaped circuit components in contact with each other on the common land in series. Since the length is set to the mounting length of the two chip-shaped circuit components arranged in series, it is possible to suppress the component interval of the chip-shaped circuit components to almost 0, and further, to improve the solderability of the chip components arranged in series. It is possible to improve the mounting density in an improved state.

【0011】[0011]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0012】図1は本発明に係るチップ部品直列配置構
成のプリント基板を説明するための平面図であり、特に
図1(a)は直列配置されたしかもペースト状半田上に
装着された2個のチップ部品の高密度装着状態を示し、
図1(b)は図1(a)の高密度装着状態からリフロー
法による半田付けを行った後の本発明に係る高密度実装
プリント基板を示す。図2は図1(b)のY−Y′断面
図であり、図3は図1(b)のZ−Z′断面図である。
FIG. 1 is a plan view for explaining a printed circuit board having a chip component serial arrangement according to the present invention. In particular, FIG. 1A shows two printed circuit boards arranged in series and mounted on paste-like solder. The high-density mounting state of the chip parts of
FIG. 1B shows a high-density mounting printed circuit board according to the present invention after soldering by a reflow method from the high-density mounting state of FIG. 1A. 2 is a sectional view taken along the line YY 'of FIG. 1 (b), and FIG. 3 is a sectional view taken along the line ZZ' of FIG. 1 (b).

【0013】まず図1(a)に示すように、プリント基
板12上にパターン導体としてそれぞれ長方形のランド
13a、共通ランド20a、ランド13bが設けられて
おり、共通ランド20aには、長さL1、幅W1の長方
形状のチップ部品11aと長さL2、幅W2の長方形状
のチップ部品11bがそれぞれ一端を共通ランド20a
に共有するように半田ペースト15を介して装着されて
いる。一方、チップ部品11aと11bの他の一端はそ
れぞれランド13aとランド13bに半田ペースト15
を介して装着されている。共通ランド20aの幅W3
は、側面での半田付け性を向上させるため、チップ部品
11aの幅W1及びチップ部品11bの幅W2の幅より
も大きい。この実施例では共通ランド20aはチップ部
品11a,11bより片側で若干広いものを使用した。
なお実施例ではランド13a,13bの幅も共通ランド
20aの幅W3と同等にした。
First, as shown in FIG. 1A, a rectangular land 13a, a common land 20a, and a land 13b are provided on the printed circuit board 12 as pattern conductors, and the common land 20a has a length L1. A rectangular chip part 11a having a width W1 and a rectangular chip part 11b having a length L2 and a width W2 have one end at a common land 20a.
It is mounted via the solder paste 15 so as to be shared. On the other hand, the solder paste 15 is applied to the lands 13a and 13b at the other ends of the chip components 11a and 11b, respectively.
Is installed through. Width W3 of common land 20a
Is larger than the width W1 of the chip part 11a and the width W2 of the chip part 11b in order to improve the solderability on the side surface. In this embodiment, the common land 20a is slightly wider on one side than the chip parts 11a and 11b.
In the embodiment, the widths of the lands 13a and 13b are also equal to the width W3 of the common land 20a.

【0014】チップ部品11a,11bは例えばチップ
コンデンサであり、そのチップ部品11aと11bとの
間の間隔W5は、ペースト状半田上へのチップ部品の装
着の最小間隔とした。このように共通ランド20aを用
いることによって2個のチップ部品の直列配置で従来の
約1/3の部品間隔を得た。
The chip components 11a and 11b are, for example, chip capacitors, and the distance W5 between the chip components 11a and 11b is the minimum distance for mounting the chip components on the paste-like solder. By using the common land 20a in this manner, a component interval of about 1/3 of the conventional one can be obtained by arranging two chip components in series.

【0015】図1(a)に示した直列配置にチップ部品
を装着し、プリント基板を通常のリフロー法による半田
付けを行い、図1(b)、図2に示したようにより高密
度実装を得る。図1(b)と図2に示したように、リフ
ロー半田付け後は、リフロー時に融解した半田の表面張
力によりチップ部品が引き寄せられ、チップ部品11a
とチップ部品11bとが共通ランド20aのほぼ中央で
互いにほぼ接する状態となる。図1(b)において、チ
ップ部品11aと11bの間は隙間がなく、半田がチッ
プ間には入り込まず、半田付けが不安定になるかのよう
に描かれているが、実際はチップ部品11aと11bが
接する部分には微細な凹凸があるため、毛細管現象によ
りリフローの際に溶けた半田が入り込み、半田付け性に
問題はない。従って、図1(b)に示したチップ部品1
1aの左端からチップ部品11bの右端までの長さL1
0は、それぞれの部品長さL1とL2をほぼ合わせた長
さとなる。このようにチップ部品11a,11bが互い
にほぼ中央で接するため、図1(a)におけるチップ部
品11aの左端とランド13aの左端の間の長さをP
1、一方チップ部品11bの右端とランド13bの右端
の間の長さをP2とすると、リフロー半田後の状態を示
す図1(b)において、上記P1,P2に対応する長さ
P1′,P2′は、チップ部品11aとチップ部品11
bとの間の間隔W1分だけP1,P2より長くなる。P
1′,L10,P2′の合計長さをL12とすると、チ
ップ部品11aと11bの直列配置の実装密度を上げる
にはL12を可能な限り最小にすることを要する。L1
とL2は固定なので、P1′,P2′を最小にする。そ
のためには、P1,P2の長さをそれぞれ0とし、W1
を部品実装機精度の最小値、例えば上記2125タイプ
の場合0.5mm、従ってP1′を0.25mm、P
2′を0.25mmとした。
Chip components are mounted in the serial arrangement shown in FIG. 1A, the printed circuit board is soldered by a normal reflow method, and higher density mounting is performed as shown in FIGS. 1B and 2. obtain. As shown in FIGS. 1B and 2, after the reflow soldering, the chip components are attracted by the surface tension of the melted solder during the reflow, and the chip components 11a
The chip component 11b and the chip component 11b are substantially in contact with each other at substantially the center of the common land 20a. In FIG. 1B, there is no gap between the chip components 11a and 11b, and the solder does not enter between the chips, and it is drawn as if the soldering becomes unstable. Since the portion where 11b contacts has fine irregularities, melted solder enters during reflow due to the capillary phenomenon, and there is no problem in solderability. Therefore, the chip component 1 shown in FIG.
Length L1 from the left end of 1a to the right end of chip component 11b
0 is a length that is a combination of the component lengths L1 and L2. Since the chip components 11a and 11b are in contact with each other substantially at the center in this manner, the length between the left end of the chip component 11a and the left end of the land 13a in FIG.
1. On the other hand, if the length between the right end of the chip component 11b and the right end of the land 13b is P2, the lengths P1 'and P2 corresponding to P1 and P2 in FIG. 'Is the chip component 11a and the chip component 11
It is longer than P1 and P2 by the distance W1 from b. P
If the total length of 1 ', L10 and P2' is L12, it is necessary to minimize L12 as much as possible in order to increase the mounting density of the series arrangement of the chip components 11a and 11b. L1
Since L2 and L2 are fixed, P1 'and P2' are minimized. To do this, set the lengths of P1 and P2 to 0, and set W1
Is the minimum value of the component mounting machine accuracy, for example, 0.5 mm in the case of the above 2125 type, so P1 'is 0.25 mm, P
2'is set to 0.25 mm.

【0016】このランドの0.25mmの部分は、図2
によく示されているように半田14によりチップ部品1
1a,11bが固定されるために必要な半田代となる。
この半田代長さはチップ部品の大きさ、半田量等によ
り、所定の長さに選択することができる。またチップ部
品11aと11bの接触部の間隙には半田14が下方か
ら上昇して入り込む。従って、チップ部品11aと11
bの接触部はチップ部品11aと11bのそれぞれの側
面の表面状態により接触状態が若干変わるが、通常のリ
フロー半田等の半田付けによりチップ部品が互いに近接
しほぼ接触する。
The 0.25 mm portion of this land is shown in FIG.
As shown in FIG.
It serves as a soldering margin necessary for fixing 1a and 11b.
This soldering length can be selected as a predetermined length depending on the size of the chip component, the amount of solder, and the like. Further, the solder 14 rises from below and enters the gap between the contact parts of the chip components 11a and 11b. Therefore, the chip components 11a and 11
Although the contact state of the contact portion of b slightly changes depending on the surface state of the side surfaces of the chip components 11a and 11b, the chip components come close to each other and are almost in contact with each other by soldering such as ordinary reflow soldering.

【0017】このように、L12をL1+L2+W5と
なるようにランド13a、共通ランド20aそしてラン
ド13bをプリント基板12上に配置してチップ部品1
1a,11bを実装することにより直列配置のチップ部
品の高密度実装をほぼ理想的なレベルにまで向上させる
ことができた。
In this way, the land 13a, the common land 20a, and the land 13b are arranged on the printed circuit board 12 so that L12 becomes L1 + L2 + W5.
By mounting 1a and 11b, it was possible to improve the high-density mounting of chip components arranged in series to an almost ideal level.

【0018】図3は図1(b)のZ−Z′断面図であ
る。図1(b)及び図3に示すように、チップ部品11
a,11bの側面が共通ランド20aの両側に広げられ
た領域を利用して半田付け(半田14)され、チップ部
品11a,11bの共通ランド20aへの半田付けをよ
り強固なものとしている。本実施例ではランド13a,
13bの幅も共通ランド20aと同様に大きくして上述
した長さ方向のチップ部品側面の半田付け性に対し幅方
向のチップ部品の半田付け性も向上させている。
FIG. 3 is a sectional view taken along the line ZZ 'of FIG. As shown in FIG. 1B and FIG.
The side surfaces of the a and 11b are soldered (solder 14) by utilizing the regions expanded on both sides of the common land 20a, and the soldering of the chip components 11a and 11b to the common land 20a is made firmer. In this embodiment, the land 13a,
Similarly to the common land 20a, the width of 13b is also increased to improve the solderability of the chip component in the width direction as compared with the solderability of the chip component side surface in the length direction described above.

【0019】リフロー半田付け後の共通ランド上での2
個のチップ部品の接触は上述したようにほぼ共通ランド
の中央で行なわれる。従って、少なくともその接触部及
びその近傍側面を特に堅固に半田付けする必要がある。
図4は本発明に係る種々の形状の共通ランドを説明する
ための図であり、特に図4(a1)、(b1)、(c
1)は平面図であり、図4(a2)、(b2)、(c
2)はそれぞれ図4(a1)のA−A′断面図、図4
(b1)のB−B′断面図、図4(c1)のC−C′断
面図である。
2 on common land after reflow soldering
The contact of the individual chip parts is performed approximately at the center of the common land as described above. Therefore, it is necessary to solder at least the contact portion and the side surface in the vicinity thereof particularly firmly.
FIG. 4 is a diagram for explaining common lands of various shapes according to the present invention, and in particular, FIG. 4 (a1), (b1), (c)
1) is a plan view, and FIG. 4 (a2), (b2), (c)
2) is a sectional view taken along the line AA ′ of FIG.
It is a BB 'sectional view of (b1), and CC' sectional view of FIG.4 (c1).

【0020】図4(a1)に示した共通ランド20bは
その側部がチップ部品11a,11bから外側(両側)
に湾曲状に突出した形状をとり、その湾曲状に突出した
共通ランド20b領域で半田付け(半田14)が強固に
なされている(図4(a2))。同様に、図4(b1)
では、チップ部品11a,11bから外側に三角形状に
突出した側部を有する共通ランド20cが設けられ、そ
の突出領域で半田付けが強固になされており(図4(b
2))、図4(c1)では、チップ部品11a,11b
から外側に左右対称の階段状に突出した共通ランド20
dが設けられ、その突出領域で半田付けが強固になされ
ている(図4(c2))。
The common land 20b shown in FIG. 4 (a1) has its side portions outside the chip parts 11a and 11b (both sides).
In the common land 20b region protruding in a curved shape, the soldering (solder 14) is firmly performed (FIG. 4 (a2)). Similarly, FIG. 4 (b1)
In this case, a common land 20c having side portions projecting outward in a triangular shape from the chip parts 11a and 11b is provided, and soldering is firmly performed in the projecting region (see FIG.
2)), and in FIG. 4 (c1), the chip components 11a and 11b.
Common land 20 protruding from the outside in a symmetrical stepwise manner
d is provided, and soldering is firmly made in the protruding region (FIG. 4 (c2)).

【0021】上述したように、半田付け性を向上させる
べく図1(b)、図4(a1)、図4(b1)、図4
(c1)に示した形状の共通ランドを使用したが、これ
らの形状に限らずその他同様の機能を有する形状であれ
ば使用することができる。なおこの場合、片側の突出長
さはチップ部品の形状、電極部の寸法等により選択す
る。
As described above, in order to improve solderability, FIG. 1 (b), FIG. 4 (a1), FIG. 4 (b1), FIG.
Although the common land having the shape shown in (c1) is used, the shape is not limited to these shapes and any other shape having a similar function can be used. In this case, the protruding length on one side is selected according to the shape of the chip component, the size of the electrode portion, and the like.

【0022】[0022]

【発明の効果】以上説明したように、本発明によれば2
個のチップ部品がほぼ接した状態で直列配置されるた
め、直列配置のチップ部品の実装密度がより向上し、し
かも半田付け性を向上させたプリント基板を得ることが
できる。
As described above, according to the present invention, 2
Since the individual chip components are arranged in series so that they are almost in contact with each other, the mounting density of the chip components arranged in series can be further improved, and a printed circuit board with improved solderability can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るチップ部品の直列配置構成プリン
ト基板を説明するための平面図である。
FIG. 1 is a plan view for explaining a printed circuit board in which chip components are arranged in series according to the present invention.

【図2】図1(b)のY−Y′断面図である。FIG. 2 is a sectional view taken along line YY ′ of FIG.

【図3】図1(b)のZ−Z′断面図である。FIG. 3 is a sectional view taken along line ZZ ′ of FIG.

【図4】本発明に係る種々の共通ランドを説明するため
の図である。
FIG. 4 is a diagram for explaining various common lands according to the present invention.

【図5】チップコンデンサの形状を説明するための斜視
図である。
FIG. 5 is a perspective view for explaining the shape of a chip capacitor.

【図6】従来の実装方式によりチップ部品を直列配置し
たプリント基板を示す図である。
FIG. 6 is a diagram showing a printed circuit board in which chip components are arranged in series by a conventional mounting method.

【符号の説明】[Explanation of symbols]

1a,1b,11a,11b チップ部品 2,12 プリント基板 3a,3b,3c,3d,13a,13b ランド 14 半田 15 半田ペースト 20a,20b,20c,20d 共通ランド 1a, 1b, 11a, 11b Chip parts 2, 12 Printed circuit boards 3a, 3b, 3c, 3d, 13a, 13b Land 14 Solder 15 Solder paste 20a, 20b, 20c, 20d Common land

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 2個のチップ状回路部品を直列に配置し
てなるプリント基板において、 前記2個のチップ状回路部品に対して電気的接続を共有
し得る共通ランド上で前記2個のチップ状回路部品を互
いにほぼ接した状態で設けてなり、且つ前記2個のチッ
プ部品を前記共通ランド上に配置した際、該共通ランド
が該2個のチップ部品のそれぞれの両側に突出するよう
に設けられてなることを特徴とするプリント基板。
1. A printed circuit board in which two chip-shaped circuit components are arranged in series, wherein the two chips are mounted on a common land that can share electrical connection with the two chip-shaped circuit components. Circuit components are provided in a state of being in close contact with each other, and when the two chip components are arranged on the common land, the common land projects on both sides of each of the two chip components. A printed circuit board characterized by being provided.
【請求項2】 前記共通ランド上で接する2個のチップ
状回路部品の直列配置長手方向全長に、該長手方向の両
側に所定の半田付け代長さを加えた長さを、前記2個の
チップ状回路部品の直列配置実装長さとすることを特徴
とする請求項1記載のプリント基板。
2. A length obtained by adding a predetermined soldering allowance length on both sides in the longitudinal direction to the total length in the longitudinal direction of the serial arrangement of the two chip-shaped circuit components in contact with each other on the common land. The printed circuit board according to claim 1, wherein the chip-shaped circuit components are arranged in series and mounted.
JP5216355A 1993-08-31 1993-08-31 Printed board Pending JPH0766524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5216355A JPH0766524A (en) 1993-08-31 1993-08-31 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5216355A JPH0766524A (en) 1993-08-31 1993-08-31 Printed board

Publications (1)

Publication Number Publication Date
JPH0766524A true JPH0766524A (en) 1995-03-10

Family

ID=16687263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5216355A Pending JPH0766524A (en) 1993-08-31 1993-08-31 Printed board

Country Status (1)

Country Link
JP (1) JPH0766524A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173256A (en) * 2004-12-14 2006-06-29 Murata Mfg Co Ltd Surface mounting structure of component
CN112586093A (en) * 2018-06-15 2021-03-30 Lg伊诺特有限公司 Printed circuit board and camera device including the same
US12144103B2 (en) 2018-06-15 2024-11-12 Lg Innotek Co., Ltd. Printed circuit board and camera device comprising same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173256A (en) * 2004-12-14 2006-06-29 Murata Mfg Co Ltd Surface mounting structure of component
JP4501668B2 (en) * 2004-12-14 2010-07-14 株式会社村田製作所 Surface mounting structure of parts
CN112586093A (en) * 2018-06-15 2021-03-30 Lg伊诺特有限公司 Printed circuit board and camera device including the same
US12144103B2 (en) 2018-06-15 2024-11-12 Lg Innotek Co., Ltd. Printed circuit board and camera device comprising same

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