JPH0759026A - Picture-in-picture circuit - Google Patents

Abstract

PURPOSE:To eliminate ruggedness of a contour line by generating a slave screen signal based on a clock signal synchronously with a horizontal synchronizing signal so as to reproduce an original picture with fidelity when a black/white signal without a burst signal is received as an input signal for a slave screen. CONSTITUTION:A horizontal synchronizing signal extracted and separated from an input signal SS is fed to a 2nd clock generating circuit 32, from which a line clock signal CH locked to a horizontal synchronizing signal is generated. A color killer signal outputted from a color killer circuit 30 provided in relation to a color demodulation circuit 28 is fed to a changeover circuit 33 as a burst discrimination signal. The signal CH is used for a signal processing clock when no burst signal is included in the input signal SS. Since the relation between the signal CH and the horizontal synchronizing signal is made constant by synchronizing the signal CH with the horizontal synchronizing signal in this way, data with an arranged time relation are written as they are to a field memory 40 even when no burst signal is in existence. Thus, the position of the clock signal between adjacent lines, that is, the position of the picture element is decided definitely and white and black edges (longitudinal lines) are completely arranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a television receiver,
Particularly, the present invention relates to a picture-in-picture circuit suitable for application to a television receiver in which a sub-screen can be fitted into a main screen for display, and more particularly to a picture-in-picture circuit in which the screen disorder of the sub-screen is improved.

[0002]

2. Description of the Related Art In recent television receivers, the screen (parent screen) M has been displayed as shown in FIG.
A picture-in-picture circuit that allows another screen (child screen) S to be inserted has come to be mounted in part of the device.

FIG. 8 shows an outline of the picture-in-picture circuit 10. The terminal 11 is supplied with an input signal (TV signal, etc.) SM for the main screen, and the terminal 1
2 includes an input signal (TV signal, etc.) S for the sub screen.
S is supplied, and both are supplied to the switching circuit 50.

The input signals SM and SS are further supplied to the screen switching signal generation circuit 60 to input the parent screen input signal SM.
A screen switching signal that is synchronized with the synchronization signal of is generated, and the input signals SM and SS are switched by this screen switching signal. The terminal 70 is supplied with a control signal at which position on the parent screen the child screen is fitted.

The child screen signal is generated as follows, for example. First, the input signal for the child screen is digitized,
After that, the screen size is reduced by thinning the input signal according to the size of the child screen to be inserted and writing it in the field memory. Then, the input signal written in the field memory is read at a predetermined timing while being synchronized with the horizontal synchronizing signal and the vertical synchronizing signal of the main screen (main screen) television signal, and the CRT is used instead of the main screen television signal. Supplied. As a result, the child screen S can be inserted (fitted) in place of the parent screen M at a predetermined position of the parent screen M.

[0006]

As a signal for a child screen, a burst signal inserted in its input signal is usually extracted, and a clock (burst clock) of, for example, four times locked to this burst signal is generated. Input signals are digitally converted by clocks and written to field memory. The reading from the field memory is performed based on the clock signal locked to the burst signal of the main screen television signal.

In any case, data writing to the field memory or the like is performed by the burst clock signal locked to the input burst signal. Various types of signals may be input as the input signals for the sub screen.

In some cases, a black and white signal without a burst signal may be supplied as an input signal. In the conventional picture-in-picture circuit 10, when the sub-picture input signal is a black and white signal that does not include a burst signal, the burst clock signal to be locked to this burst signal does not lose its reference. The frequency cannot be uniquely determined. Therefore, the relationship between the burst clock frequency and the horizontal frequency that should be originally satisfied, that is, the relationship that the integral multiple of the horizontal frequency is the burst clock frequency cannot be satisfied.

The fact that the relationship between the burst clock frequency and the horizontal frequency does not satisfy the integral multiple relationship means that the sampling clock, that is, the position of the pixel shifts for each horizontal line in the child screen shown in FIG. The border (vertical line) becomes jagged as shown in the figure, and the screen becomes unsightly.

Incidentally, this jagged width is 1/3 the width of the read clock. Read clock is 14.3
When the frequency is MHz (= 4 fsc; fsc is a subcarrier frequency), it is about 25 nsec, and when it is 18 MHz (= 5 fsc), it is about 20 nsec.

Therefore, the present invention solves the above-mentioned conventional problem, and a picture-in-picture circuit is provided so that the screen does not become uncomfortable even when an input signal in which a burst signal is not inserted is supplied. Is proposed.

[0012]

In order to solve the above problems, according to the present invention, in addition to a conventional picture-in-picture circuit, a clock generation circuit synchronized with a horizontal synchronizing signal of a child screen input signal and the presence / absence of a burst signal are provided. A detection circuit is newly provided, and an input signal having a burst signal is processed by a conventional operation, that is, a signal is processed by a burst clock signal locked to the burst signal.

On the other hand, when an input signal without a burst signal is supplied, a line clock signal synchronized with the horizontal synchronizing signal of the input signal is generated and the signal processing is performed by this line clock signal. It is what

[0014]

As shown in FIG. 1, the burst clock signal CB locked to the burst signal of the input signal is generated by the first clock generation circuit 31 and the horizontal synchronization signal of the input signal is generated by the second clock generation circuit 32. A line clock signal CH locked to is generated.

The burst clock signal CB and the line clock signal CH are switched by the color killer signal, and only when there is no burst signal, the line clock signal C
H is selected as the clock for signal processing.

By synchronizing the line clock signal CH with the horizontal synchronizing signal only when the burst signal does not exist in the input signal, the relationship between the line clock signal CH and the horizontal synchronizing signal becomes constant, so that the burst signal is Even when there is no data, the time-related data is written in the field memory 40 as it is.

As a result, the position of the clock between adjacent lines, that is, the position of the pixel is uniquely determined, and the white and black edges (vertical lines) are perfectly aligned as shown in FIG. as a result,
Even when a black-and-white signal without a burst signal is input, the unsightly appearance of the child screen is eliminated.

[0018]

EXAMPLE Next, a picture-in
An example of the picture circuit will be described in detail with reference to FIG.

In the picture-in-picture circuit 10 shown in FIG. 1, the terminal 11 is supplied with the input signal SM serving as the parent screen as described above. The input signal is a television signal which is normally on air. Terminal 1
In addition to the on-air television signal (standard signal), the VTR is used as the sub-screen input signal SS supplied to
A non-standard signal such as a video signal reproduced by a reproduction apparatus or other reproduction apparatus can be considered.

The sub-screen input signal SS is converted into a sub-screen signal SS 'which has been subjected to various signal processing for screen fitting and changed to a predetermined screen size and is output. The input signal SM and the input signal SM are supplied to the switching circuit 13, and both are switched based on the screen switching signal output from the memory control circuit 35 and output to the terminal 14. If the switched signal is output to the CTR, for example, a two-screen display as shown in FIG. 7 is displayed.

Next, a circuit system for generating the sub-picture signal SS 'will be described. The input signal (composite video signal) from the tuner or VTR (not shown) supplied to the terminal 12 is the A / D converter 21.
Is converted into a digital signal. The digitized composite video signal is first supplied to the horizontal digital low-pass filter 22 for Y / C separation, and the luminance signal is extracted.

The separated luminance signal Y is supplied to a digital low pass filter 23 for further vertical filtering. Since the filtering in the vertical direction is performed using the luminance signals of several adjacent lines, the line memory 25 is used. In this example, since the filtering process is performed using 3 lines, two line memories are used as the line memory 25 to store the line information of the immediately preceding 2 lines.

Vertical filtering is particularly effective when a nonstandard signal is input as an input signal. In the case of a non-standard signal, its horizontal frequency and vertical frequency are often slightly different from those specified, so when the sub-screen signal SS 'is formed with reference to the burst signal inserted in the non-standard signal, As shown in FIG. 2A, clock positions (pixel positions) between lines are not constant.

If this is left as it is, the contour of the image becomes jagged, and the unsightly screen is fitted as it is.

To improve this, a filtering process in the vertical direction is performed. For example, if three adjacent lines are used and their average is used as the line information after the filtering process, the line information of FIG. 2A becomes like the line information of FIG. This is because the fluctuation amount can be suppressed.

The filtering processing in the horizontal and vertical directions also has a function of suppressing aliasing distortion caused by data thinning processing performed to generate the sub-picture signal SS 'as described later.

The filtered luminance signal Y is supplied to the multiplexer 24 and is combined with the color signal described later.

The color signals are separated by a 3.58 MHz band pass filter (BPF) 26. Since the color signal is a modulated signal, it is clamped by the digital clamp circuit 27 and then returned to the R and B component signals (color difference signals of RY and BY) in the color signal demodulation circuit 28.

These component signals are supplied to the horizontal digital low-pass filter 29 and subjected to horizontal filtering processing. Since it is necessary to perform data decimation processing in order to generate the child screen signal SS ′ to be inserted in the parent screen, the data is preliminarily processed by performing the filtering processing in the low frequency region before the data decimation processing. This is because it is necessary to keep them around.
By doing so, it is possible to prevent the lack of contour data in the thinning process.

The filtered component signal is supplied to the multiplexer 24 and time-division multiplexed with the luminance signal Y.

Now, the series of digital processes described above are all performed based on the clock generated from the input signal SS. Therefore, the input signal SS supplied to the terminal 12
The burst signal extracted and separated from is supplied to the first clock generation circuit 31 and is locked to the burst signal. In this example, a burst clock signal CB of 4 fsc (fsc is a burst frequency) is generated.

In addition to the above, according to the present invention, the input signal S
In this example in which the horizontal synchronizing signal extracted and separated from S is supplied to the second clock generating circuit 32 and locked to the horizontal synchronizing signal, a line clock signal CH of 610 fH (fH is a horizontal frequency) is generated.

The burst clock signal CB is the input signal SS
The line clock signal CH is used as a signal processing clock when there is no burst signal in the input signal SS, and is used as a signal processing clock when there is no burst signal in the input signal SS.

By synchronizing the line clock signal CH with the horizontal synchronizing signal only when the burst signal does not exist in the input signal, the relationship between the line clock signal CH and the horizontal synchronizing signal becomes constant, so that the burst signal Even when there is no data, the time-related data is written in the field memory 40 as it is.

As a result, the position of the clock between adjacent lines, that is, the position of the pixel is uniquely determined, and white and black edges (vertical lines) are perfectly aligned as shown in FIG. as a result,
Even when a black-and-white signal without a burst signal is input, the unsightly appearance of the child screen is eliminated.

The burst clock signal CB and the line clock signal CH are supplied to the switching circuit 33, and one of them is selected based on the burst discrimination signal. In this example, the color killer circuit 30 is used as a detection circuit for detecting the presence / absence of a burst signal, and the color killer signal output from the color killer circuit 30 provided in association with the color demodulation circuit 28 is switched as a burst discrimination signal. Circuit 33
Is supplied to.

The selected clock signal is the above-mentioned A / D.
The clock signal is supplied to all necessary processing circuits including the converter 21 and the memory control circuit 3
5 is also supplied.

The memory control circuit 35 is a control system required to generate a child screen signal SS 'having a specified size and capable of inserting the child screen at the specified position of the parent screen. Therefore, in the input signal SS supplied to the terminal 12, the horizontal drive signal (same as the horizontal synchronizing signal) HD separated from this is the memory control circuit 35.
And a vertical drive signal (which is the same as the waveform of the vertical sync signal Vsync) VD generated from the horizontal drive signal HD and the vertical sync signal Vsync.
Reference numeral 37 is a vertical drive signal VD generation circuit.

Input signal S for parent screen supplied to terminal 11
Even in M, the horizontal drive signal HD and the vertical drive signal VD are supplied. The terminal 36 is supplied with a control signal for designating the size and insertion position of the small screen. In this example, as shown in FIG. 6, the child screen having a size of 1/9 of the parent screen can be inserted at any position indicated by diagonal lines. This control signal is input from a commander (not shown) or the like provided in the television receiver.

The sub-screen signal SS 'is generated by the data thinning process as described above. A specific example will be described below.

Since the child screen is 1/9 the size of the parent screen, two lines out of every three lines are thinned out in the vertical direction. In the horizontal direction, it is only necessary to thin out 2 pixels out of 3 pixels, but in the horizontal direction, data can be increased by interpolation processing after memory reading. Is performed. That is, the original data is compressed to 1/6.

Luminance signal and color signal (component signal)
And the thinning rate is different. Since the information of the component signal is about 1/4 of that of the luminance signal, the component signal is 1/12 in this example by the thinning process.
Is compressed to.

By compressing the luminance signal data to 1/6 and the component signal data to 1/12,
The capacity of the field memory 40 used can be significantly reduced.

The above-mentioned compression / interpolation processing is shown in FIGS.
Will be described with reference to. FIG. 4 shows an example of compression processing, and FIGS. 4A and 4B show original luminance signals and chrominance signals (component signals). When the same figure B is shifted by one clock, it becomes the same figure C. The multiplexer 24 takes out a luminance signal of 6 samples (which is synonymous with 6 clocks, and this clock signal is the burst clock signal CB or the line clock signal CH) every 1 sample, and 12 samples for the R and B component signals. The sample is taken out every 1 sample and the time division multiplexing process is performed. The time division multiplexed signal is shown in FIG. 4D.

Since the component signal is time-division-multiplexed at a rate of 1 sample out of 12 samples, R of the component signal is read in the first 12 clock cycles.
Component signal RY of B is multiplexed, and the component signal BY of B is multiplexed in the next 12 clock cycles.

The time division multiplexed signal is written in the memory, in this example the field memory 40, by the write enable signal WE shown in FIG. Therefore, the thinned data Yi, RYi, and BYi are sequentially written in the corresponding addresses of the field memory 40 in the state shown in FIG. The write clock output from the memory control circuit 35 is the burst clock signal CB or the line clock signal CH.

The read operation of the time-division multiplexed signal will be described with reference to FIG. The data written in the field memory 40 is the horizontal drive signal H of the parent screen input signal SM when the scanning of the parent screen reaches the inset position of the child screen.
It is read in synchronization with D and the vertical drive signal VD. The data written in the field memory 40 is A in FIG. 4 (= FIG. 4F), and the read enable signal RE shown in B in FIG.
As a result, the data is read only during the low level period, and as a result, the time division multiplexed signal of the data string as shown in FIG. The reason why such a data string is used is for the sake of interpolation processing described later.

As the read clock signal CB ', a clock frequency locked to the burst signal or the horizontal synchronizing signal of the input signal SM for the parent screen is used. In this example, it is 4 fsc, but its frequency is the input signal S for the parent screen.
Frequency locked to M burst signal (eg 5 fsc)
May be used.

The read time-division multiplexed signal is supplied to the signal separation circuit 41 in the subsequent stage and separated into a luminance signal Y and R and B component signals (D and E in the same figure). The separated luminance signal Y is delayed by one clock and then supplied to the luminance signal interpolation circuit 42 to be linearly interpolated (average value interpolation) from the preceding and following luminance data. In the linear interpolation, the linearity after the interpolation is improved as compared with the previous value interpolation (previous value hold).

The result of interpolation is shown in FIG. This interpolation process doubles the luminance data, which is equivalent to just compressing the data to 1/3 in the horizontal direction.

Similarly, the R and B component signals are also supplied to the interpolation circuit 43 to be subjected to linear interpolation processing. However, since the component signals of the same color component are obtained every 12 clock cycles, the interpolation processing is also shown in FIG. This is done using component signals of the same color component as G.

Interpolation processing is not performed where there is a component signal, and the component signal is used as it is. Since the B component signal is located next to the R component signal, the interpolation processing alternates for each same color component. Done. At that time, the arithmetic processing is performed on the preceding and following component signals in a weighted state according to the interpolation distance.

In FIG. G, as the distance from the component signal of the same color component increases, the weighting coefficient becomes “3 → 2 →
1 ”. Therefore, the interpolation at the pixel closest to RY1 is calculated as (3RY1 + RY25) / 4 by setting the weighting factor of RY1 to 3 and the weighting factor of RY25 12 clocks ahead.

By this interpolation processing, the color data is 2
Since it will double, the data will be 1/6 in the horizontal direction.
It is equivalent to compressing to.

As is clear from FIGS. 6A and 6B, the luminance signal Y
The ratio of R and B component signals is Y: RY-BY: BY = 4: 1: 1.

The interpolated luminance signal and component signal are supplied to the control circuit 44 for the image quality and the image frame, and the image quality (brightness, sharpness, etc.) of the sub-screen.
In addition to the control of (1), the image frame signal (white frame etc.) when the sub-screen is fitted is generated. After these controls are performed, the synthesizing circuit 45 frequency-multiplexes the composite video signal. Composite video signal is D
The signal is converted into an analog signal by the / A converter 46 and supplied to the above-mentioned switching circuit 13 as the sub-screen signal SS '.

The memory control circuit 35 outputs a switching signal (a signal synchronized with the signal SM) according to the fitting position, and the switching circuit 13 is controlled by this so that a two-screen display as shown in FIG. 7 is made.

[0058]

As described above, in the picture-in-picture circuit according to the present invention, even when a black-and-white signal without a burst signal is input as an input signal for a child screen, a clock synchronized with the horizontal synchronizing signal is generated. However, this clock is used to generate the child screen signal.

According to this, even when a black-and-white signal without a burst signal is input, it is possible to fit a sub-screen that more faithfully reproduces the original image, and the unsightly contour line is jagged. There is a real benefit that can be completely wiped out.

Further, even if the input signal for the small screen is a non-standard signal, it is possible to fit a screen without disturbance as a small screen.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a picture-in-picture circuit according to the present invention.

FIG. 2 is a diagram for explaining screen disorder when a non-standard signal is input.

FIG. 3 is a diagram illustrating a contour portion of a child screen when there is no burst signal.

FIG. 4 is a timing chart showing an example of a child screen data write operation.

FIG. 5 is a timing chart showing an example of a child screen data reading operation.

FIG. 6 is a diagram illustrating an insertion position of a child screen.

FIG. 7 is a diagram showing a relationship between a parent screen and a child screen.

FIG. 8 is a system diagram of a conventional picture-in-picture circuit.

FIG. 9 is a diagram illustrating a contour portion of a child screen when there is no burst signal.

[Simple explanation of symbols]

 10 picture-in-picture circuit 13 switching circuit 22, 23, 29 low-pass filter 30 color killer circuit 31 first clock generation circuit 32 second clock generation circuit 35 memory control circuit 40 field memory 42, 43 interpolation circuit SM parent screen Input signal for SS SS input signal for child screen SS 'signal for child screen

Claims (2)

[Claims] 1. A first clock generation circuit for a child screen that generates a clock locked to a burst signal of an input signal, and a second clock generation circuit for a child screen that generates a clock locked to a horizontal synchronizing signal of the input signal. It has a clock generation circuit, a burst discrimination circuit that discriminates the presence or absence of a burst signal, and a clock switching circuit that switches between a clock locked to the burst signal and a clock locked to the horizontal synchronization signal based on this burst signal discrimination signal. A picture-in-picture circuit characterized in that the input signal can be displayed more faithfully on the screen even when a black-and-white signal without a signal is input. 2. A clock generation circuit for a sub-screen that generates a clock locked to a burst signal of an input signal, and a low-pass filter for the vertical direction of the input signal. The low-pass filter performs vertical filtering. Thus, the picture-in-picture circuit is characterized in that the sub-screen can be inserted without disturbing the screen even when a non-standard signal is input as the input signal.