JPH0757395A - Reproducing device - Google Patents

Abstract

PURPOSE:To reduce power consumption while realizing high-speed operation by changing the operation speed of a circuit incorporated in a device in accordance with a reproducing frequency in the reproducing device for reproducing with a different frequency according to the reproducing position on a magnetic recording medium. CONSTITUTION:The magnetic recording/reproducing device comprises current control circuits 2001-2256 for changing over the operating current of the comparators 1001-1256 of an AD converter 7 and an AD converter control circuit 15 for receiving the instruction of changing speed in accordance with the reproducing frequency. The current control circuits 2001-2256 make the operating state of the AD converter 7 the state of low power consumption when they receive the instruction for slowing down the changing speed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a constant density recording (Constant D
The present invention relates to a playback device that employs an ensity recording method.
Further, the present invention relates to an AD converter, and particularly to an AD converter that achieves both high speed and low power consumption.

[0002]

2. Description of the Related Art In order to make effective use of a recording medium, there is a method of changing the recording / reproducing frequency according to the recording / reproducing position, as disclosed in Japanese Patent Laid-Open No. 63-200306.
The amount of data recorded / reproduced in a unit time is proportional to this frequency. Generally, in this method, the recording density on the outer circumference side (the amount of data recorded per unit length on the recording medium)
To record data on the outer circumference side in order to make
The reproduction frequency is higher than the inner frequency.

At this time, in a filter or the like in which the change in frequency directly affects the reproduced waveform, the circuit parameters are changed according to the reproduced frequency. However, in other circuits, in many cases, if the circuit is designed to operate at the highest frequency on the outermost circumference, the low frequency on the inner circumference side does not cause a problem in terms of performance. Even if it changed, the operation of the circuit was not particularly changed.

A high-speed AD converter, for example,
It may be used in a reproducing circuit of a magnetic recording device adopting the above-mentioned uniform density recording method. The AD converter used in this type of magnetic recording device needs to convert data having different frequencies.

The AD converter is used in a reproducing circuit of a magnetic recording device by using an RLL code such as a (1,7) code on a recording medium as seen in Japanese Patent Laid-Open No. 2-182032. This is because a high magnetic recording density can be obtained by a method in which an analog signal corresponding to coded binary data is converted by an AD converter and reproduced.

With regard to the AD converter, it is expected that a large capacity magnetic recording device can be obtained by using the above two methods together.

[0007]

In an analog circuit, the operating speed generally increases as the current consumption (operating current) increases. Therefore, in the magnetic recording / reproducing apparatus described above, the operation is performed at the highest frequency used in the outermost circumference. If the circuit is designed to be high speed, a large current corresponding to the high frequency will flow regardless of the position on the medium. On the other hand, the operating speed of the circuit may be low at a low frequency on the inner circumference side, but the operating speed of the circuit hardly changes because a current is applied to the analog circuit regardless of the position on the medium. Therefore, there is an excessive speed margin at the low reproduction frequency on the inner circumference side. That is, an excessive current is flowing.

However, the demand for low power consumption of the magnetic recording / reproducing apparatus is increasing year by year, so that it is desirable to reduce the unnecessary current consumption.

A first object of the present invention is to provide a reproducing apparatus which realizes high-speed operation and has low power consumption.

By the way, in general, a high-speed AD converter is required to convert and reproduce binary data by an AD converter. Furthermore, if a method of changing the frequency at the time of recording / reproducing of the magnetic disk device is used together, the recording frequency of the data on the outer periphery becomes higher, so that a faster AD converter is required. However, the higher the speed of the AD converter, the greater the power consumption. Therefore, if the high speed AD converter is used as it is, the power consumption becomes large, which is not suitable for the recent needs for lower power consumption.

A technique for changing the power consumption of the AD converter according to the change in conversion speed is disclosed in, for example, Japanese Patent Laid-Open No. 62-62.
There is a technique disclosed in Japanese Patent No. 204621. However, this relates to a low-speed integration type AD converter, and in the case of the integration system, there is a problem that the conversion level changes when the integration time changes, and a countermeasure therefor is an object. Therefore, it has been proposed to change the integration capacitance of the integrator and to switch the current value of the constant current source for taking charge from the capacitor, and there is no description about the reduction of current in a high-speed AD converter that is not an integration method. Absent.

Further, as a technique for realizing a high-speed AD converter, there is a method of operating a plurality of AD converters in parallel.
This technique is described in Japanese Patent No. 70213 and Japanese Patent Laid-Open No. 4-72919.

Among them, the techniques described in Japanese Patent Laid-Open No. 60-183819 and Japanese Patent Laid-Open No. 4-72919 have no description about low power consumption. In addition, JP-A-3
The technology disclosed in Japanese Patent Publication No. 70213 only states that the power of an unused AD converter is turned off in order to reduce the power consumption, and there is no description about a specific method for realizing the power consumption.

A second object of the present invention is to provide an AD converter which realizes high-speed AD conversion and has low power consumption.

A third object of the present invention is to provide an AD converter system having a plurality of AD converters, which consumes less power.

[0016]

In order to achieve the above-mentioned first object, in a reproducing apparatus for reproducing at a reproducing frequency different depending on a reproducing position on a recording medium, the reproducing apparatus is built in the reproducing apparatus according to the frequency. It was decided to have a control means for controlling the operating speed of the circuit.

In order to achieve the second object, in the AD converter having a comparison means for comparing the input analog signal with a reference voltage and a signal generation means for generating a digital signal from the comparison result, the comparison means is provided. The operating speed of is determined by an operating current flowing at the time of operation, which is controlled from the outside, and receiving means for receiving an instruction to instruct any one of a plurality of speeds for converting an analog signal into a digital signal; , And a current control means for controlling the operating current in accordance with the speed.

Further, in order to solve the third object, in an AD converter system having m (m ≧ 2) AD converters for converting an inputted analog signal into a digital signal, each of the m AD converters. Has a comparing means for comparing the input analog signal with a reference voltage and a signal generating means for generating a digital signal from the comparison result. The operating speed of the comparing means is controlled from the outside and flows during operation. Accepting means for accepting an instruction for instructing any one of a plurality of speeds for converting an analog signal into a digital signal, which is determined by the operating current, and n (n ≦ n) from the m AD converters in response to the instruction.
m) a distribution means for distributing the analog signal to the AD converter in time series, an output means for receiving the digital signals output from the n AD converters and outputting them in time series, and receiving the instruction, AD converter control means for suppressing the above operating current of (m−n) AD converters excluding n AD converters is provided.

[0019]

In the first structure, the operating speed of the circuit is switched according to the reproduction frequency. When reproducing at a high frequency on the outer peripheral side, the circuit is set to operate at high speed. On the other hand, when reproduction is performed at a low frequency on the inner circumference side, for example, the current value of the circuit is lowered or some circuits are switched to set the operating speed of the circuit low. In this way, since it operates at low speed, power consumption is reduced.

In the second configuration, when the conversion speed is increased, the current control means receives the instruction and operates so as to flow a large amount of operating current of the AD converter. In general, the circuit operates faster as more current flows, so the AD converter at this time can perform high-speed AD conversion.

When the conversion speed is reduced, the current control means receives the instruction and sets the operating current of the AD converter to a small value. At this time, since the operating current of the AD converter is small, it is possible to reproduce the data with low power consumption.

In the second configuration, when the conversion speed is increased, the number of AD converters in operation is increased in response to the above instruction, and the input and output destinations are sequentially connected to the AD converters in operation in time division. To do. Therefore, m A
When a D converter is provided and each AD converter operates at the frequency f, it is possible to reproduce at a frequency of m × f.

In order to reduce the conversion speed, the number of AD converters in the low power consumption state is increased in response to the above instruction. Also, the means for switching the input and output destinations are sequentially connected in time division only between the AD converters that are operating.
Therefore, n out of m AD converters (1 ≦ n
When only the AD converter of <m) is operated and each of the n AD converters operates at the frequency f, it is possible to reproduce n × f frequencies. In this case, data reproduction can be performed with lower power consumption as the number of AD converters in operation decreases.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

First, the first embodiment is shown in FIGS.
2 is used for the explanation.

FIG. 1 is a block diagram of a magnetic recording apparatus using the present invention. The magnetic recording device 1 includes a recording medium 2 and
Head 3, read / write amplifier 4, AGC (Au
toGain Control) 5 and signal processing circuit 6
An AD converter 7, a data discrimination circuit 8 for equalizing and digitizing signals digitized by the converter 7, an encoder / decoder 9, and an HDC (H
ard Disk Controller) 10 and I /
F (Interface) circuit 11 and buffer 12
And a microcomputer (microcomputer) 13. The AD converter 7 receives the instruction from the current control circuit 14 and the microcomputer 13, and the current control circuit 14 receives the instruction.
AD converter control circuit (reception means) 15 for controlling
Built in.

FIG. 2 shows an example of recording / reproducing frequency divisions of the magnetic recording medium 2. Here, the frequency is divided into three categories. Assuming that the sections are A, B, and C in order from the outer periphery, the section A reproduces at the frequency f1, the section B reproduces at the frequency f2, and the section C reproduces at the frequency f3.
The higher the frequency, the higher the frequency

[0028]

## EQU00001 ## Let f1: f2: f3 = 4: 3: 2.

FIG. 3 is a block diagram of the AD converter 7. In this embodiment, the AD converter 7 is an 8-bit parallel AD converter. The AD converter 7 includes the AD converter control circuit 15, the resistor string 16, the encoder 17 as a signal generating unit, the clock generating circuit 18,
It comprises a switch 19, an OR 20, and 256 comparators (comparing means) 1001-1256. Comparator 1001-1
Each of the 256's has a built-in current control circuit 2001 to 2256, and can change the operating current of the differential amplifier circuit of each comparator. The 256 current control circuits 2001-
2256 corresponds to the current control circuit 14 shown in FIG.
Switching is performed according to a control signal from the AD converter control circuit 15. Furthermore, the AD converter control circuit 15
Reduces the power consumption by controlling the switch 19 and the OR 20 as well. In accordance with the control signal of the AD converter control circuit 15, the switch 19 switches the voltage applied to the resistor string 16 from VH to VL, and the OR 20 fixes the clock. The AD converter control circuit 15 converts the data written in the register 21 from the microcomputer 13 into the inverter 22,
23 and AND24 to 27 are used for decoding to generate a control signal to the circuit group. In this embodiment, a clock proportional to the reproduction frequency is input from the signal processing circuit 6 as an operation clock of the AD converter.

FIG. 4 shows an example of the configuration of the current control circuit 2001. The current control circuit 2001 includes a constant voltage source 28, a switch 29, an operational amplifier 30, a transistor 31, a resistor 3
It consists of two. The switch 29 operates according to the control signal from the AD converter control circuit 15, and supplies one of the voltages V (1) to (4) from the constant voltage source to the input of the operational amplifier 30. Here, V (1)> V (2)> V (3)> V
(4) = 0, for example,

[0031]

## EQU00002 ## V (1): V (2): V (3) = 4: 3:
2 Note that the total current of the comparator 1001 becomes a value proportional to the current I flowing through the circuit due to the current mirror. By the way, the magnitude of the operating current I is given by the following equation.

[0032]

## EQU00003 ## I = V (k) /R.sub.k=1 to 4 As can be seen from the equation 3, the most current flows when the highest voltage V (1) is applied. The comparator 1001 operates faster as more current flows, and thus operates faster at the voltage V (1). When the voltage is lowered to V (2) and V (3), the current decreases and the operation speed slows down.
When connected to (4), almost no current flows and the comparator does not work. Current control circuit 2 of comparators 1002-1256
002 to 2256 have the same configuration.

FIG. 21 shows a configuration example of a main circuit of the comparator 1001 shown in FIG. The circuit is a differential amplifier circuit portion of the comparator 1001. The circuit includes transistors 2102-
2109, resistance switch 2101, current sources 2110, 2
It is composed of 111. The sampling mode and the hold mode of the circuit are switched by CLK 'and CLK. In FIG. 21, a CLK with a bar is indicated by adding “′”. First, when CLK '= H (CLK = L),
That is, the operation in the sampling mode will be described. The analog input is input to the transistor 2102 and the reference voltage is input to the transistor 2103, and a voltage difference obtained by amplifying the difference voltage is generated in the base voltage of the transistors 2104 and 2105. Further, the result of amplifying the difference voltage is output to V _OUT .

At this time, the gain A of the output voltage of each amplification stage is A = I.R / V _T. Here, I is the current value of the current source 2110 or the current source 2111, R is the resistance value, V _T is the threshold voltage, and is about 26 mV at room temperature.

Therefore, the output voltage of each amplification stage = (I · R /
V _T ) × (input differential voltage).

When the difference voltage is larger than V _T , the output voltage = IR.

Next, when CLK = H (CLK '= L), that is, when the hold mode is selected, V _OUT is completely I.
・ Amplifies to R voltage and outputs. Since the transistors 2104 and 2105 are off, even if the analog input changes and the magnitude relationship with the reference voltage reverses during the hold mode, the output according to the magnitude relationship in the previous sampling mode is held. .

Here, each of the current sources 2110 and 2111 causes a current proportional to the current value generated by the current control circuit 2001 to flow through a current mirror or the like. At this time I
・ Switch the resistance according to I to keep R constant. The operation speed of the circuit changes depending on the current, and it operates at high speed when a large current is passed and at low speed when a small current is passed. The comparators 1002 to 1256 also include similar circuits. As a result, the resistor R is also switched according to the switching of the current, so that the gain of the comparator can be kept constant. The comparators 3001 to 256 described later can be similarly configured.

Table 1 shows the state of the circuit of the AD converter at each reproduction frequency.

[0040]

[Table 1]

The microcomputer writes different data in the register of the AD converter control circuit according to the reproduction frequency, and the circuit in the AD converter operates according to the data as shown in Table 1. The operation of this embodiment will be described below with reference to this table and FIGS.

First, the case of reproducing the data included in the section A will be described. The data 11 instructing the data reproduction of the section A is transferred from the microcomputer 13 to the AD converter control circuit 15. The circuit decodes the data to generate a control signal. In this case, the control signal a1 = 1,
a2 to a4 = 0. OR2 according to the control signal
The input signal to 0 is set to 0, and the switch 19 is connected to VH and the switch 29 is connected to V (1). By inputting V (1) to the operational amplifier 30, the current value of the AD converter becomes maximum, and the AD converter operates at the highest speed.

Next, the case of reproducing the data included in the section B will be described. Similarly to the above, a control signal is generated in the AD converter control circuit 15, the input signal to the OR 20 is set to 0 by the control signal, and the switch 19
To VH and switch 29 to V (2). The operating current at this time is as small as about 75% of that in the data reproduction of the section A, as can be seen from the simple calculations from Equations 2 and 3, and the power consumption can be reduced accordingly. Although the AD converter operating speed is slowed down accordingly, the playback frequency is also slowed down, so that the speed is sufficiently high.

Thirdly, when the data included in the section C is reproduced, as shown in Table 1, the switch 29 is connected to V (3), and the others are the same as above. The operating current at this time is even smaller, about 50% of the maximum current, and the power consumption can be further reduced. Although the operation speed of the AD converter is also slow, it operates faster than the reproduction frequency f3 of C.

Finally, when the reproduction is not being performed, the switch 29 is connected to V (4) and the switch 19 is connected to VL. At this time, the currents flowing through the comparators 1001 to 1256 and the resistor string 16 are almost zero. Become. At the same time, the clock is fixed by setting the input signal to the OR 20 to 1, so that the power consumption becomes extremely small.

In this embodiment, the magnitude of the current is changed by switching the bias voltage of the current source of the comparator, thereby realizing the operating speed of the comparator according to the reproduction frequency. In this way, it is possible to reproduce data at a high frequency, while suppressing data consumption by reproducing data at a low frequency with a low current.

Next, an embodiment will be described in which the current control circuit uses a circuit having a configuration different from that of the above embodiment.

FIG. 5 shows another configuration example of the current control circuit 2001. The circuit shown in FIG. 5 has a plurality of resistors 38-40.
Is prepared, and the resistance to be connected is switched by the switch 37 in accordance with the frequency during data reproduction. here,

[0049]

## EQU00004 ## R1: R2: R3 = 3: 4: 6, and the switches 37 are set to R1, R2, R in descending order of frequency.
Switching to 3 reduces the current at the same rate as in the previous embodiment. Further, during non-reproduction, the switch 34 is turned off to interrupt the current path so that no current flows. The current control circuits 2002 to 2256 have the same configuration.

Table 2 shows the operation of the current control circuit when this embodiment is used.

[0051]

[Table 2]

The bias voltage switching function of the first embodiment is different from that of the previous embodiments in that the resistance switching and the current path interruption are realized. That is, in the above-described embodiment, the switch 29 is operated to switch the bias voltage in four ways for the case of three frequencies during reproduction and the total of four cases during non-reproduction. On the other hand, in the present embodiment, in the case of three frequencies at the time of reproduction, the switch 37 switches three kinds of resistance to cope with it, and in the case of non-reproduction, the current path is cut off by the switch 34. To do. This embodiment is the same as the above embodiment in the generation of the control signal except for the above points and the other operations of the switches and the like. Further, in terms of power consumption and conversion speed, the same effects as those of the above-described embodiment can be obtained.

In this embodiment, the parallel type AD converter is used, but another type of AD converter may be used. Further, the number of recording sections on the magnetic recording medium and the number of current switching of the AD converter may be arbitrary.

The current control circuits 2001 to 2256
May be combined into one or several and current may be distributed to each comparator.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to Table 10 and Table 3.

FIG. 6 is similar to FIG. 1 except for the AD converter 41.
Is the same as. The AD converter 41 outputs the outputs of the AD converters 42 to 45 and the AGC 5 to the AD converter 42.
To switch 45, switches 47 connecting outputs of the AD converters 42 to 45 to inputs of the data discrimination circuit 8, AD converters 42 to 45 and switches (distribution means) 46 in response to an instruction from the microcomputer 13. , And an AD converter control circuit (AD converter control means) 48 for controlling the switch 47. The AD converters 42 to 45 have low power consumption circuits 49 to 52, respectively. Four AD converters 42 according to the reproduction frequency
To 45, n (0 ≦ n ≦ 4) AD converters are operated, and the other AD converters are set to the low power consumption state. Switch the active AD converter to switches 46, 4
The data is exchanged by sequentially connecting at 7, and A / D conversion is performed. The frequency division of the magnetic recording medium 2 is the same as that shown in FIG.

FIG. 7 is an internal block diagram of the AD converter 42. Here, the AD converter 42 is an 8-bit parallel AD converter. The AD converter 42 is
Resistor string 53, encoder 54, sample / hold amplifier 55, switches 56, 256 comparators 3001 to 300
Built-in 256. The sample / hold amplifier 55 and the comparators 3001 to 256 are respectively the current control circuit 5
7, 4001 to 4256 are built in, and the operating current can be made almost zero by the circuit. The switch 56 and the current control circuits 57, 4001 to 4256 correspond to the power consumption reduction circuit 49 of FIG. 6, and reduce the power consumption of the AD converter 42 in accordance with the power consumption reduction instruction signal b1 from the AD converter control circuit 48. This is the circuit to be realized. Switch 5
6 switches the voltage applied to the resistor string 53 to reduce the current flowing through the resistor string, and the current control circuits 57, 4001 to 425.
Reference numeral 6 switches the internal bias voltage to change the currents of the sample / hold amplifier 55 and the comparators 3001 to 256. The AD converters 43 to 45 also have the same configuration as the AD converter 42.

FIG. 8 shows a configuration example of the current control circuit 4001. The circuit includes a constant voltage source 58, a switch 59, an operational amplifier 60, a transistor 61, and a resistor 62, and has a function of turning on / off the operating current of the comparator 3001. When the switch is switched according to the control signal from the AD converter control circuit 48 to connect the voltage V (2) = 0, the current becomes almost zero. Current control circuit 57, 4002
4256 has the same configuration as the current control circuit 4001. However, the voltage value and resistance value of the current control circuit 57 are
The values of the current control circuits 4001 to 4256 do not always match.

FIG. 9 is an internal block diagram of the AD converter control circuit 48. The circuit includes a register 63 for latching data from the microcomputer 13, and low power consumption instruction signals b1 to b to the AD converters 42 to 45 based on the data.
3 and decoder 6 for generating control signals for counter 65
4, a counter 65 that counts the order of switching the switches 46 and 47, a decoder 66 that generates the control signals c1 to c4 of the switch 46 from the value of the counter, and a control signal of the switch 46 delayed by the conversion time of the AD converter. A delay circuit 67 that generates the control signals d1 to d4 of the switch 47, and a clock generation circuit 68 that generates an operation clock of the AD converters 42 to 45, the counter 65, and the delay circuit 67 from the clock of the signal processing circuit 6.

[0060]

[Table 3]

Table 3 shows the control signal at each reproduction frequency and the operation circuit of the AD converter. The higher the reproduction frequency, the more AD converters are operated in parallel to perform high-speed conversion, and all the AD converters are brought into the low power consumption state during non-reproduction. The switches 46 and 47 control the control signal c1.
.About.c4 and d1 to d4, the AD converters in operation are sequentially switched.

FIG. 10 shows how data is output from the AD converter in each section. In section A, the four AD converters 42 to 45 are operated in parallel to obtain an output result corresponding to a high speed frequency. In sections B and C, since low-speed conversion is sufficient, the number of operating AD converters is reduced.

The operation of this embodiment will be described below with reference to FIGS.

First, the case of reproducing the data included in the section A will be described. When receiving the data from the microcomputer 13, the decoder 6 in the AD converter control circuit 48
4, the low power consumption instruction signals b1 to b3 and the counter 65
Generate the control signal of. In this case, b1 = b2 = b3 =
Since it is 1, all the AD converters 42 to 45 perform normal operations. In the initial state, the control signals c and d1 = 1
The switches 46 and 47 are both connected to the AD converter 42. Then, the read / write amplifier 4 reads the data from the magnetic recording medium 2 through the head 3. Then, when data is input from the AGC 5 to the AD converter 42 through the switch 46, the sample / hold amplifier 42 of the AD converter 42 samples the data,
Hold on. On the other hand, the counter 65 of the AD converter control circuit 48 performs a counting operation, and at the next timing, the control signal c2 = 1 output from the decoder 46 is set and the switch 46 is switched to be connected to the AD converter 43. Similarly, the switches 46 are sequentially moved to the AD converter 44 and the AD converter 4 by the control signals c1 to c4.
5, AD converter 42, AD converter 43, ... On the other hand, the switch 47 similarly switches using the control signals d1 to d4 obtained by delaying the control signal of the switch 46 by the delay circuit 67 by the conversion time of the AD converters 42 to 45. In this way, by operating the four AD converters in parallel and switching the switches to transfer data, the conversion speed of the AD converter as a whole can be four times as high as that of one AD converter as shown in FIG.

Next, the case of reproducing the data included in the section B will be described. Similarly to the above, the AD converter control circuit 48 decodes the signal from the microcomputer 13,
The control signals b1 to b3 are generated. In this case, b1 = b2
= 1 and b3 = 0, the AD converters 42 to 44
Is a normal operation, but the AD converter 45 is in a low power consumption state. That is, the operation clock of the AD converter 45 is fixed by the power consumption reduction circuit 52, and the bias voltage of the current source is set to a low voltage (= 0 V). On the other hand, the switch 46 is connected to the AD converter 42 in the initial state, and switches the AD converters 42 to 44 excluding the AD converter 45 by the control signals c1 to c3 for each data. The control signal c4 for instructing the AD converter 45 in the low power consumption state to connect the switch 46 is 0.
It is fixed. The switch 47 delays the switching timing with respect to the switch 46 by the conversion time of the AD converter and performs the same operation. Thus, as shown in FIG. 10 (2), the data is reproduced at the frequency of the 3 × f AD converter. At this time, since the AD converter 45 is in the low power consumption state, the power consumption is reduced accordingly, and the power consumption of the entire AD converter 41 becomes about 75%.

Thirdly, the case of reproducing the data included in the section C will be described. Similar to the above, the control signal b1
~ B3 are generated, in this case b1 = 1, b2 = b3 = 0
Is. Therefore, the AD converters 42 and 43 are in normal operation, and the AD converters 44 and 45 are brought into the low power consumption state by the power consumption reduction circuits 51 and 52. on the other hand,
Switches 46 and 47 alternately switch the AD converters 42 and 43 to connect them, and at this time, control signals c3, c4, d
3 and d4 are fixed to 0. In this way, the data is reproduced at the frequency of the 2 × f AD converter and the power consumption is classified as Category A.
It becomes about 50% of the case of reproduction.

Finally, when reproduction is not performed, b1
= B2 = b3 = 0 and all the AD converters 42 to 45 are in the low power consumption state.

In this embodiment, there are four AD converters and two AD converters.
An AD converter with a built-in magnetic recording device adapted to reproduce data of different frequencies is provided by providing a single switch, a power consumption reducing circuit with a built-in AD converter, and an AD converter control circuit. In particular, data reproduction at high frequencies can be realized by operating a plurality of AD converters in time division, and power consumption is reduced by stopping the operation of some AD converters at the time of data reproduction at low frequencies. be able to.

Although four AD converters are used in the above embodiment, any number may be used and any number of recording sections on the magnetic recording medium may be used. Furthermore, as a method of reducing power consumption, a method of cutting off the power supply may be used,
Only one method of stopping the clock or reducing the current value of the current control circuit may be used. Further, although the parallel type AD converter is used in the present embodiment, another method A
A D converter may be used.

In FIG. 7, the current control circuit 400
It is also possible to combine 1 to 4256 into one or several and distribute the current to each comparator.

Further, the first embodiment and the second embodiment may be combined.

Next, a third embodiment of the present invention will be described with reference to FIGS.
0 and Table 4 will be described.

FIG. 11 is an overall block diagram of the inside of the magnetic recording / reproducing apparatus 1000 according to the third embodiment. The magnetic recording / reproducing apparatus 1000 includes a recording medium 2, a head 3, and a read / write device.
A write amplifier 4, an AGC 5, a signal processing circuit 6, an analog equalizer 71, an analog data discrimination circuit 81, an encoder / decoder 9, an HDC 10, an I / F circuit 11, a buffer 12 and a microcomputer 13 are built in.

At the time of writing, the read / write amplifier 4 sends a signal from the built-in driver to the head 3, and the head 3 magnetically records data on the recording medium 2.
During reading, the waveform reproduced from the recording medium 2 by the head 3 is amplified and the signal is sent to the AGC 5. A
The GC 5 adjusts the amplitude of the reproduction waveform amplified by the read / write amplifier 4 so that a constant amplitude signal can be obtained. The signal processing circuit 6 detects the head of the recording data and the like.

The analog equalizer 71 obtains a desired signal waveform by deleting high frequency components of the reproduced signal.
In order to explain the operation of the analog equalizer 71, the recording method in this embodiment will be described.

In the present embodiment, the signal to be magnetically recorded is recorded by using the Viterbi decoding and the PR (Partial Response) system.

Viterbi decoding is a decoding method in which data at different times are correlated with each other, that is, data obtained by performing a predetermined calculation between data at different times is recorded and reproduced. Looking at this playback signal in time series,
Ideally, the fact that only a limited time series pattern appears is used. That is, it is utilized that, when a reproduction value exists at a certain time, only a limited reproduction value determined by the reproduction value appears at the next time. The actual playback waveform including noise is
Although a pattern other than this limited pattern can be adopted, the error of the signal can be corrected to some extent by selecting the limited time series pattern closest to the time series pattern of the reproduced signal.

In the PR system, as a measure against intersymbol interference that occurs in a magnetic recording / reproducing device during high density recording, the entire device is constructed so that the intersymbol interference becomes a predetermined interference. Specifically, at the time of recording, 1 / (1
Perform the operation represented by -DxD). Where D is 1
It is a delay operator that delays the sampling time. DxD
Means to delay by 2 sampling times. When this signal is recorded and reproduced by the magnetic recording system, the reproduction signal becomes a signal obtained by performing 1 / (1 + D) operation on the original signal because the magnetic recording system has the characteristic of (1-D). . Therefore, the analog equalizer 71 is an equalizer having a characteristic of (1 + D), whereby the original signal is obtained. The output signal of the analog equalizer 71 is shown in FIG.

The analog data discrimination circuit 81 determines 0/1 data (Viterbi decoding) from the signal waveform. The encoder / decoder 9 performs code conversion between the data on the HDC 10 or the host side and the data recorded on the recording medium 2 with the limited word length. The HDC 10 controls the output timing of data so that the data is recorded on the recording medium 2 in a specific format, and ECC (Error
Add data such as Correcting Code). In addition,
Generally, the transfer speed of the host and the read / write speed of the recording medium 2 do not match, so the data is temporarily stored in the buffer 12 during data transfer. I / F circuit 11
Performs protocol processing for transferring data and the like between the host and the magnetic recording device 1000. The microcomputer 13 controls the magnetic recording / reproducing apparatus 1000 as a whole.

FIG. 12 shows a configuration example of the analog equalizer 71 shown in FIG. In this configuration example, a 4-tap transversal type equalizer is used, and the voltage value of the product sum of the voltage for three cycles obtained by sampling the analog input signal from AGC5 and the voltages c1 to c4 corresponding to the coefficient is calculated. Then, the output signal is output to the analog equalizer 71. One cycle corresponds to one time in FIG. One cycle is also called one clock. In addition, the voltages c1 to c4 are classified into the category A shown in FIG.
It is a fixed value in each category of ~ C, and if the category is different, voltage c
1 to c4 are also different.

The circuit 71 is a delay circuit 7114 to 7116 for delaying an input signal by one cycle, respectively, and a multiplier 7 for obtaining a product of input data and constants c1 to 4 respectively.
117-7120, an adder 7121 that calculates the sum of the output results of the multipliers 7117-7120, and a register 7 that sets an operating current value according to the reproduction frequency by the microcomputer 13.
122 and a decoder 7123 for generating signals s1 to s5 for controlling the operating current of each circuit inside the analog equalizer 71 according to the set values of the register 7122. The signals s1 and s2 are input to the delay circuits 7114 to 7116. The signals s1 to s1 to the multipliers 7117 to 7120 are
s5 is input. The signal s1,
s2 is inputting.

Further, the delay circuit 7114 is composed of two sample / hold circuits 7124 and 7125. The sample / hold circuits 7124 and 7125 each have a function of delaying a signal by half a clock, and clocks of opposite phases to each other. Since one is sampling, the other is holding. The sample / hold circuits 7124 and 7125 are current sources 712, respectively.
6, 7127 are incorporated, and in FIG.
7127 and other circuit parts.

The delay circuits 7115 and 7116 are also the delay circuit 7
The configuration is the same as 114.

In operation, first, the magnetic recording device 1000
Sets the current value in the register 7122 while the head seeks the target track for reading. The decoder 7123 generates the control signals s1 to s5 from the set value, and the current set in each circuit flows in response to the control signal. Further, the voltages c1 to c4 are also determined from the settings of the microcomputer 13 and the like. The above is the operation for preparation, and the operation from generation of an output signal from an input signal sent by reading next will be described. The differential signal sent from the AGC 5 is input to the delay circuit 7114 and the multiplier 7117, and the delay circuit 7114 delays the input signal by one cycle, and the multiplier 7
At 117, the product of the input voltage and the constant voltage c1 is obtained. At the same time, the multiplier 7118 outputs 1 which is the output of the delay circuit 7114.
The product of the input signal voltage before the cycle and the constant voltage c2 is obtained, and the multiplier 7119 multiplies the product of the input signal voltage before the two cycles output from the delay circuit 7115 and the constant voltage c3 by the multiplier 7
At 120, the product of the input signal voltage three cycles before, which is the output of the delay circuit 7116, and the constant voltage c4 is obtained. And
The output voltage of each of the multipliers 7117 to 7120 is added to the adder 712.
Add 1 and output to the analog data discrimination circuit.

FIG. 13 shows a circuit example of the main part of the multiplier 7117. The circuit consists of transistors 7128-713.
3, resistors 7134, 7137, 7140, switch 71
39, 7141, 7142, and a current source 7143 for supplying two currents. The control signals s1 and s2 are received to change the current value of the current source 7143 to change the operation speed, and the switches 7141 to s3 to s5 are used. , 714
2, 7143 is also switched to select a resistor to keep the circuit gain constant.

The multiplier 7117 determines the resistance value and the current value by the control signals s1 to s5 during the seek period, and also determines the differential voltage c1 applied to Vin2.
Transistors 7132, 71 depending on the difference voltage of voltage c1
There will be a difference in the current flowing through 33. Then, the differential output signal of AGC5 is applied to Vin1 as an input signal. At this time, depending on the difference voltage, the transistor 71
28 and 7129 and transistors 7130 and 7131 have different current values. As a result, as the output Vout, a differential voltage corresponding to the product of Vin1 and Vin2 can be obtained. The multiplication circuits 7118 to 7120 also include similar circuits.

In this embodiment, the multiplier 7117 is used.
In addition to the circuit shown in FIG. 13, it is assumed to have a function of converting the output signal to the adder 7121 from a differential signal to a single end signal. What is a differential signal?
It is x (t) shown in (a), and is the difference voltage of two signals. The single-ended signal is y shown in FIG.
(T), which is the voltage of one signal (usually ground reference). The differential signal is used to cancel common mode noise when there is an influence of noise or the like.

Next, FIG. 14 shows a circuit example of the main part of the adder 7121. The circuit includes an operational amplifier 44, a resistor 71
45 to 7149 and a current source 7150. The input voltages Vin1 to Vin4 of the circuit are multiplied by the multiplication circuit 7 respectively.
These are output voltages of 117 to 7120, and currents corresponding to the respective voltages flow through the resistors 7145 to 7148. Then, the total current of the current values flows through the resistor 7149, so that the voltage Vo proportional to the total current is obtained. Note that the resistances 7145 to 7148 have the same value here, but the resistance values can be changed and weighted. The circuit changes the current value of the current source 7150 by receiving the control signals s1 to s2. The adder 7121 is configured by adding a level shifter or the like to the circuit. Since the operation speed of the adder 7121 largely depends on the speed of the operational amplifier 44, by changing the current value to change the speed of the operational amplifier 44,
The operation speed of the entire adder 7121 can also be changed.

FIG. 15 shows a configuration example of the current source 7150 shown in FIG. The current source 7150 is used for the currents I1 to In necessary for all circuits in the adder 7121 as well as the operational amplifier 44.
Shall be generated. The current I1 is the constant current source 7151.
With the current Io supplied by the reference current as a reference current, transistors 7154 to 7157 forming a current mirror with the transistor 7152, a control signal s1 to s2, and a transistor 715 switching with a standby signal.
8-7161. Control signals s1, s
2. For the standby signal, VH (= power supply voltage) is applied when 1 is set, and VL (= ground voltage) is set when 0 is set.
When the voltage of 1 is set, each MOS transistor 7153, 7158 to 7161 operates in the saturation region and a current flows, and when the value of 0 is set, the MOS transistor 7153, 7158 to 7161 operates in the non-saturation region, and the current is cut off. Transistors 7152, 7154-
Assuming that the size of 7157 is the same, the current I1 is 4 times the maximum Io when the control signals s1 and s2 and the standby signal are set to 1, and 3 × Io, 4 depending on the settings of the control signals s1 and s2. A current of × Io can be set. Furthermore, the current of I1 can be set to 0 by setting the standby signal to 0. Similarly, the currents I2 to In are composed of transistors that form a current mirror and transistors that perform switching. However, since the currents I2 to In do not always have the same value as I1, the number and size of transistors differ accordingly. The operation is similar to I1. Of the n currents, m (1 ≦ m ≦ n) is used in the operational amplifier 7144, and the remaining (nm) currents are used in other circuits.

Current sample / hold circuits 7124, 7
125 current sources 7126, 7127 (FIG. 12), multiplier 7117 current source 7143 (FIG. 3), and delay circuit 71.
14, 7115, 7116 (FIG. 2), multiplier 7118-
The current source incorporated in the 7120 (FIG. 2) is also a circuit having the same configuration as the current source 7150 incorporating a current mirror and a switch, although the current value and the number of supplied currents are different.

FIG. 16 shows a configuration example of the analog data discrimination circuit 81 shown in FIG. This circuit is basically
"Application of Probabili
stic decoding to Digital
Magnetic Recording System
s "IBM J. RES. DEVELOP. Jan.
(1971) H.A. According to Kobayashi.

The circuit 81 includes a switch 8162, metric operation circuits 8163 and 8164, the circuit 8163,
A logic circuit 8165 for generating an output signal from the calculation result of 8164, a register 8166 and a register 8166 for setting data according to the reproduction frequency by the microcomputer 13.
A decoder 8167 for generating signals s6 and 7 for controlling the operating current of each circuit in the analog data discriminating circuit 81 according to the set value of is built in. Further, the metric operation circuit 8163 includes an adder 8168 and subtractors 8169 to 817.
1, comparators 8172, 8173, switches 8174, 8
175 and sample / hold circuits 8176 and 8177, and the metric operation circuit 8164 has the same configuration. The comparators 8172 and 8173 and the sample / hold circuits 8176 and 8177 have built-in current sources 8178 to 8181, which receive the control signals s6 and s7 and switch the current values. The operation of the analog data discrimination circuit 81 will be described. First, as a preparation, a current value is set in the register 8166, the control symbols s6 to s7 generated by the decoder 8167 are received from the set value, and the current set in each circuit is supplied. , Determine the operating speed of the circuit. Then, the analog signal output from the analog equalizer 71 is input, and the switch 8
162 alternately sends input signals to the metric operation circuits 8163 and 8164. For example, an odd-numbered cycle input signal is input to the metric calculation circuit 8163, and an even-numbered input signal is input to the metric calculation circuit 8164. This is shown in FIGS. 20 (b) and 20 (c).

In this way, the reason why the odd-numbered data and the even-numbered data are independently discriminated from each other is that in the present embodiment, intersymbol interference is caused between the data shifted by two sampling times. This is because it is possible to discriminate data independently.

The so-called metric amount is calculated by the adder 8168 and the subtractors 8169-8171 from the signal input to the metric calculation circuit 8163. sample/
The hold circuits 8176 and 8177 hold past metric amounts, respectively, and the adder 8168 and the subtractor 8169 perform calculation of input signals and their amounts.
Further, in the subtractors 8170 to 8171, a constant voltage A / 2
Is subtracted to obtain the metric amount. The comparators 8172 and 8173 respectively compare the calculated result in the current cycle thus obtained with the metric amount held in the sample / hold circuits 8176 and 8177. The comparators 8172 and 8173 are 1 /
The binary digital value of 0 is output to the logic circuit 8165. In addition, the switches 8174, 8
175 allows sample / hold circuits 8176, 8
The metric amount held in 177 is switched as it is or is updated to the amount calculated from the input signal in the current cycle. Metric calculation circuit 816
Also in No. 4, the same operation as the metric operation circuit 8163 is performed. The logic circuit 8165 performs a check by word length limitation, a combination of data alternately input from the metric operation circuits 8163 and 8164, and outputs the 0/1 reproduced data obtained as a result to the encoder / decoder 9.

The adder 8168 is equivalent to the adder 71.
21. The subtractor 8169 has an operational amplifier 82 and a resistor 83 as shown in FIG.
˜86, current source 87. As described above, Vin1 = (input signal), Vi
n2 = (output signal of sample / hold circuit 8176)
Input the signal. If the resistors 83 to 86 have the same resistance value, the difference voltage Vin2-Vin1 is output Vout.
Obtained as. The subtracters 8170 and 8171 are also the circuit 8
The configuration is similar to that of 169.

The current source in the analog data discrimination circuit 81 has the same configuration as the current source 7150 shown in FIG. 15, and the control signals s6 and s7 generated by the decoder 8167 are generated.
To switch the current.

FIG. 18 shows an example of recording / reproducing frequency divisions of the magnetic recording medium 2. From the outer circumference, each section is designated as A, B, and C, and section A reproduces at frequency f1,
The section B reproduces at the frequency f2, and the section C reproduces at the frequency f3.
Shall be reproduced. Here, f1>f2> f3. Table 4 shows an example of switching register settings, decoder output signals, circuit currents, and speeds in each section.

[0098]

[Table 4]

In section A, when "11" is set in the register, control signals s1 = s2 = s3 = 1, s4 = s5 =
By setting 0 and s6 = s7 = 1, the current value of the analog equalizer 8171 and the analog data discrimination circuit 81 is increased, that is, the operating speed is set high. In section B, "10" is set in the register, the current value is slightly reduced and the operation speed is set slightly slower. Register 0 in category C
0 "is set to further reduce the current value and further reduce the operation speed.

The operation of this embodiment will be described with reference to FIGS. 11 to 20 and Table 4 above.

First, the case of reproducing the data included in the section A will be described. The microcomputer 13 is the I / F circuit 11
The host receives a read request for the data included in the category A from the host. Then, the microcomputer 13 gives an instruction to the HDC 10 and the like, and also writes the data “11” to the register 7122 in the analog equalizer 8171 and the register 816816 in the analog data discrimination circuit 81. The decoder 23 in the analog equalizer 71 controls the control signals s1 = s2 = 1 and s3 = 1, s according to the data.
4 = s5 = 0. At this time, the current source 7150 (see FIG.
Since the transistors 7158 to 7161 (FIG. 15) of 4) are all turned on, the current value becomes the largest, I1≈4Io, and the currents I2 to In are also set to the largest value. Therefore, the operational amplifier 7144 (FIG. 14) operates at the highest speed, and the adder 7121 (FIG. 12) is operated.
Will also be the fastest. Similarly, the delay circuits 7114 to 7116 (FIG. 12) and the multiplier 7117
The current sources of ˜7120 (FIG. 12) are also set to have the largest current value, so that the circuit group also operates at the highest speed. Therefore, at this time, the analog equalizer 71 operates at the highest speed. Similarly, the analog data discrimination circuit 81 operates at the highest speed.

On the other hand, the signal reproduced by the head 3 from the section A of the recording medium 2 is the read / write amplifier 4, the AGC.
5. The signal processing circuit 6 performs amplification and other waveform processing, and inputs the analog equalizer 71. Since the analog equalizer 71 is set to operate at high speed as described above, it is possible to perform the calculation at a speed corresponding to the high frequency signal of the section A. Similarly, the analog data discrimination circuit 81 also performs a high-speed operation, and the output result is the encoder / decoder 9, the HDC 10, the buffer 12,
It is transferred to the host through the I / F circuit 11.

Next, when reproducing the data included in the section B, the microcomputer 13 registers the registers 7122 and 8166.
Write the data of "10". The decoder 7123 controls the control signals s1 = 0, s2 = 1, and s according to the data.
It is assumed that 3 = 0, s4 = 1, and s5 = 0. At this time, the transistors 7158 to 7160 of the current source 7150 (FIG. 14) are used.
(FIG. 15) is turned on and the transistor 7161 is turned off, so that I1≈3Io, and similarly, the current value of I2 to In is equal to or smaller than that in the case of section A. Therefore, the analog equalizer 71 operates at a slower speed than in the case of section A, but maintains an operation speed sufficient to perform calculation at a speed corresponding to the frequency of the data in section B.
The same applies to the analog data discrimination circuit 81. The reproduction data is transferred to the host through the same route as described above. In this case, the power consumption can be reduced by the amount of the reduced current.

Finally, when reproducing the data included in the section C, the microcomputer 13 sets the registers 7122 and 8166.
Write the data of "00" to. The decoder 23 controls signals s1 = s2 = 0 and s3 = 0 according to the data.
It is assumed that s4 = 0 and s5 = 1. At this time, the current source 7150
Transistors 7158 and 7159 are turned on, and transistors 7160 and 7161 are turned off. Therefore, I1≈
It becomes 2 Io, and similarly, the current value of I2 to In is set low, and the power consumption is suppressed to a low level. At this time, the analog equalizer 71 operates at the lowest speed, but is assumed to have a speed sufficient for reproducing the data of the section C. The same applies to the analog data discrimination circuit 81. The reproduction data is transferred to the host through the same route as described above. The current can be suppressed most during the reproduction of the data of the section C.
When it is not necessary to operate the circuit, the standby state is set and the current is suppressed to almost zero. The standby state means a non-read state, and the standby state can be achieved by setting s1 = s2 = 0.

Although a 4-tap transversal equalizer is assumed in this embodiment, other types of equalizer may be used as long as the circuit can control the operating speed by the current.

Similarly, the data discriminating circuit may have a configuration different from that of this embodiment as long as the circuit can control the operating speed by the electric current.

The registers 7122 and 8166 may be shared, or the decoders 23 and 8167 may be shared.

Furthermore, in the above embodiment, the frequency division of the recording medium is divided into three, and the processing speed switching of the circuit is also divided into three.
Although the number of stages is set to any number, the number of frequency divisions and the number of processing speed switching may be different.

In this embodiment, the analog equalizer 7 is used.
1 delay circuits 7114 to 7116 and multipliers 7117 to 7
The circuits up to 120 are configured to handle differential signals, and the subsequent circuits in the adder 7121 and the analog data discrimination circuit 81 are configured to handle single-ended signals. However, it is possible to increase the number of circuits that operate by differential signals, or convert all the analog circuits of the analog equalizer 71 and the analog data discriminating circuit 81 to single-end by converting them into single-ended signals at the input of the analog equalizer 71. It may be configured by a circuit. That is, as a countermeasure against noise, as many circuits as possible to handle differential signals should be used, but in consideration of cost, it is desirable to reduce the circuit scale by increasing the number of circuits to handle single-ended signals.

[0110]

According to the present invention, A
It is possible to provide a reproducing device in which the operation of the D converter is changed. That is, by increasing the operating current of the AD converter, it is possible to reduce the power consumption of the reproducing device by reducing the operating current of the AD converter at a low frequency while realizing the conversion of high frequency data. is there. Alternatively, by operating a plurality of AD converters in parallel, conversion of high-frequency data can be realized, while at the low frequency, the operation of some AD converters can be stopped to reduce the power consumption of the reproducing apparatus. is there. In general, the frequency of the outermost circumference is about twice the frequency of the innermost circumference, so using the present invention,
The power consumption of the AD converter during reproduction can be reduced by about 25%.

Further, it is possible to provide a reproducing apparatus in which the operating speed of a circuit such as an equalizer or a data discriminating circuit incorporated in the reproducing apparatus is changed according to the reproducing frequency. That is, it is possible to realize a high-speed operation corresponding to a high frequency by flowing a relatively large current value, while reducing the current value at a low frequency to reduce the operation speed and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing recording / reproducing frequency divisions of a magnetic recording medium.

FIG. 3 is a block diagram of an AD converter.

FIG. 4 is a block diagram of a current control circuit.

FIG. 5 is another block diagram of the current control circuit.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a block diagram of an AD converter.

FIG. 8 is a block diagram of a current control circuit.

FIG. 9 is a block diagram of an AD converter control circuit.

FIG. 10 is a timing chart of data output of the AD converter.

FIG. 11 is a block diagram of a third embodiment of the present invention.

12 is a block diagram of the analog equalizer 7 of FIG.

13 is a block diagram of a main circuit of a multiplier 17 of FIG.

14 is a block diagram of a main circuit of an adder 21 shown in FIG.

15 is a block diagram of the current source 50 of FIG.

16 is a block diagram of the data discrimination circuit 8 of FIG.

17 is a block diagram of a main circuit of the subtractor 69 shown in FIG.

18 is an explanatory diagram showing recording / reproducing frequency divisions of the magnetic recording medium of FIG.

FIG. 19 is an explanatory diagram of a differential signal and a single end signal.

20 is an explanatory diagram showing signals of main parts of the analog data discrimination circuit 8 of FIG. 11. FIG.

21 is a circuit diagram of a main part of the comparator 1001 of FIG.

[Explanation of symbols]

1 ... Magnetic recording device, 2 ... Magnetic recording medium, 3 ... Head, 4
... Read / write amplifier, 5 ... AGC, 6 ... Signal processing circuit, 7, 41-45 ... AD converter, 8 ... Data discrimination circuit, 9 ... Encoder / decoder, 10 ... HDC, 11
... I / F circuit, 12 ... Buffer, 13 ... Microcomputer, 1
4, 57, 2001 to 2256, 4001 to 4256 ...
Current control circuit, 15, 48 ... AD converter control circuit,
16, 53 ... Resistance train, 17, 54 ... Encoder, 18,
68 ... Clock generation circuit, 19, 29, 34, 37, 4
6, 47, 56, 59 ... Switch, 20 ... OR, 100
1-1256, 3001-3256 ... Comparator, 21, 6
3 ... Register, 22, 23 ... Inverter, 24-27 ...
AND, 28, 33, 58 ... Constant voltage source, 30, 35, 6
0 ... operational amplifier, 31, 36, 61 ... transistor, 3
2, 38-40, 62 ... Resistor, 49-52 ... Low power consumption circuit, 55 ... Sample / hold amplifier, 65 ... Counter, 64, 66 ... Decoder, 67 ... Delay circuit, 71 ...
Analog equalizer, 81 ... Data discrimination circuit, 7114
~ 7116 ... Delay circuit, 7117-7120 ... Multiplier,
7121, 8168 ... Adder, 7122, 8166 ... Register, 7123, 8167 ... Decoder, 7126, 7
127, 7176, 7177 ... Sample / hold circuit, 7126, 7127, 7143, 7150, 817
8-8181, 8187 ... Current source, 7144, 8182
... operational amplifier, 8163, 8164 ... metric operation circuit, 8165 ... logic circuit, 8172, 8173 ... comparator, 8169-8171 ... subtractor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ken Urakami, 111 Nishiyote-cho, Takasaki-shi, Gunma General Semiconductor Division, Hitachi, Ltd. (72) Inventor Shoichi Miyazawa 1099 Ozenji, Aso-ku, Kawasaki, Kanagawa Stock Company Hitachi Systems Development Laboratory (72) Inventor Ryutaro Hotta 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Stock Company Hitachi Systems Development Laboratory

Claims (11)

[Claims] 1. A reproducing apparatus for reproducing at a reproducing frequency different depending on a reproducing position on a recording medium, characterized by comprising control means for controlling an operating speed of a circuit incorporated in the reproducing apparatus according to the frequency. Playback device. 2. A reproducing apparatus for reproducing a signal recorded on a recording medium by a uniform density recording method, wherein the operating speed of a circuit incorporated in the reproducing apparatus is controlled in accordance with the radial position on the recording medium. A reproducing apparatus having a control means. 3. The reproducing apparatus according to claim 1, wherein the control means controls an operating current of the built-in circuit. 4. The reproducing apparatus according to claim 1, 2 or 3, wherein the built-in circuit is an equalizer for equalizing the waveform of a signal reproduced from the medium, and the control means is an operation of the equalizer. A reproducing apparatus comprising: a unit for setting a current value; and a unit for controlling the equalizer according to the set value. 5. A reproducing apparatus according to claim 1, 2 or 3, wherein said built-in circuit is a data discriminating circuit for discriminating data from a signal reproduced from said recording medium, and said control means is said data. A reproducing apparatus having means for setting a value of an operating current of the discrimination circuit and means for controlling the data discrimination circuit according to the set value. 6. An AD converter having a comparing means for comparing an input analog signal with a reference voltage and a signal generating means for generating a digital signal from the comparison result, wherein the operating speed of the comparing means is controlled from the outside. Receiving means for receiving one of a plurality of speeds for converting an analog signal into a digital signal, which is determined by an operating current flowing at the time of operation, and the operating current according to the speed for receiving the instruction. An AD converter, comprising: 7. The AD converter according to claim 6, wherein the comparison means has a differential amplifier circuit, and the operating current is an operating current flowing through the differential amplifier circuit. . 8. An AD converter system having m (m ≧ 2) AD converters for converting an input analog signal into a digital signal, wherein each of the m AD converters receives the input analog signal as a reference voltage. And a signal generating means for generating a digital signal from the comparison result. The operating speed of the comparing means is determined by an operating current flowing at the time of operation, which is controlled from the outside, and an analog signal is converted to a digital signal. Receiving means for receiving any one of a plurality of speeds for converting the analog signal to n (n ≦ m) AD converters from among the m AD converters according to the instruction. Distributing means for distributing in time series, and output for receiving digital signals output from the n AD converters and outputting in time series And the step, upon receiving the instruction, the AD converter system, comprising an AD converter control means for inhibiting (m-n) pieces of the operating current of AD converter excluding the n-number of AD converters. 9. A reproducing apparatus for reproducing at a reproduction frequency different depending on a reproducing position on a recording medium and converting an analog signal read from the recording medium into a digital signal by an AD converter, wherein the AD converter is an input analog signal. It has a comparing means for comparing the signal with the reference voltage and a signal generating means for generating a digital signal from the comparison result. The operating speed of the comparing means is determined by an operating current flowing at the time of operation, which is controlled from the outside, Receiving means for receiving an instruction to instruct any one of a plurality of speeds for converting an analog signal into a digital signal according to the frequency at the time, and receiving the instruction, controlling the operating current according to the speed. And a current control unit for controlling the reproduction. 10. A reproducing apparatus for reproducing at a reproducing frequency different depending on a reproducing position on a recording medium and converting an analog signal read from the recording medium into a digital signal by m (m ≧ 2) AD converters. Each of the m AD converters has a comparison means for comparing the input analog signal with a reference voltage and a signal generation means for generating a digital signal from the comparison result. The operating speed of the comparison means is controlled from the outside. A receiving means for receiving an instruction to instruct any one of a plurality of speeds for converting an analog signal into a digital signal, which is determined by an operating current flowing at the time of operation, and in accordance with the instruction from the m AD converters. And a distribution means for distributing the analog signal in time series to n (n ≦ m) AD converters, and Output means for receiving the input digital signals and outputting them in time series, and an AD converter control for receiving the instruction and suppressing the operating current of (mn) AD converters excluding the n AD converters. And a reproducing device. 11. The reproducing apparatus according to claim 9 or 10, wherein the comparison means has a differential amplifier circuit, and the operating current is an operating current flowing through the differential amplifier circuit. Playback device.