JPH0750293A - Manufacture of semiconductor substrate and liquid crystal image display device using the substrate - Google Patents

Abstract

PURPOSE:To provide stable and excellent element characteristics by using tetramethylanmonium hydride for etching a single crystal semiconductor layer. CONSTITUTION:Tetramethylanmonium hydride is used for etching a single crystal semiconductor layer 103 so as to isolate an element on a semiconductor substrate which has the single crystal semiconductor layer 103 on an insulating plane 102. Thus, accurate etching is performed and accuracy of the dimensions and shape of the element area is improved. (As a result, for example, the channel width of a transistor can be stably formed.) The element separating side planes can be uniformly etched, which allows less influence from charges, etc., and an integrated circuit which allows small nonuniformity of characteristics is provided on an SOI substrate 101 at low cost. Etching can be performed without deteriorating the characteristics of the element within a thickness that allows light permeation and a liquid crystal image display device is provided with high yield.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor substrate and a liquid crystal image display device using the same, and more particularly to an electronic device integrated circuit formed by dielectric isolation or a single crystal semiconductor layer on an insulator. And a liquid crystal image display device using the same.

[0002]

BACKGROUND OF THE INVENTION The formation of single crystal Si semiconductor layers on insulators is widely known as the silicon-on-insulator (SOI) technology and is unattainable in bulk Si substrates that make conventional Si integrated circuits. Much research has been done because devices utilizing SOI technology have advantages.

In other words, by using the SOI technology ,. Dielectric isolation is easy and high integration is possible.

.. Excellent resistance to radiation.

.. The stray capacitance can be reduced and the speed can be increased.

[0006] The well process can be omitted.

[0007]. Latch-up can be prevented.

[0008] A fully depleted FET is possible. It is possible to create a device with advantages such as.

Currently, the method for producing an SOI substrate is as follows: (1). SiO ₂ was introduced into the Si substrate by oxygen ion implantation.
Form the layers. (2). A semiconductor substrate is attached to the insulating film and the semiconductor substrate is ground. These two methods are influential.

[0010]

When an actual device is produced using the above SOI substrate, element isolation is performed in order to electrically isolate the devices. As a method for element isolation, there are a selective oxidation method, a groove isolation method and the like. However, each separation method has the following problems.

That is, in the separation by the selective oxidation, since the separation interface is covered with the thermal oxide film, good characteristics can be obtained as the interface characteristics, but the lateral spread of the selective oxidation region changes due to the variation of the Si thickness. This results in changing the dimensions of the semiconductor element (for example, the channel width of the MOS transistor).

Further, in trench isolation, since the Si is etched in the RIE mode, the dimensions of the semiconductor element (for example, MOS
This is good for controlling the transistor channel width), but traps such as charges occur at the separation interface, causing apparent variations in the concentration on the semiconductor surface, and further, leakage current between the source and drain due to damage, etc. And other problems occur.

[0013]

A method of manufacturing a semiconductor substrate according to the present invention is a method of manufacturing a semiconductor substrate having a single crystal semiconductor layer provided on an insulating surface, wherein TMAH (Tetra) is used for etching the single crystal semiconductor layer. Methylammonium hydride) is used.

The liquid crystal image display device of the present invention is characterized by using a semiconductor substrate manufactured by the above method for manufacturing a semiconductor substrate.

[0015]

According to the present invention, by using TMAH for etching a semiconductor substrate having a single crystal semiconductor layer provided on an insulating surface, etching can be performed with high accuracy to improve the accuracy of the dimensional shape of the element region. (For example, the channel width of a transistor can be formed stably.) In addition, it is possible to uniformly etch the side surface of the element isolation to make it less susceptible to the influence of electric charges and the like.
It is possible to provide an integrated circuit on an OI substrate at low cost.

The present invention is suitably used for a liquid crystal image display device using an SOI substrate, and when light is transmitted to the element isolation region, even if the Si thickness is non-uniform, a thickness that allows light transmission. Further, it becomes possible to perform etching without impairing the characteristics of the element, and it is possible to provide a liquid crystal image display device with a high yield.

A feature of the present invention is that anisotropic etching peculiar to an alkaline solution is applied to an SOI substrate.

Regarding the etching by TMAH used in the present invention, Technical Digest
of the 9th Sensor Symposs
Anisotropic etching has been confirmed as described in ium 1990 p15-18. However, all of them are applied to pressure sensors and the like in the field of micromechanics, and the application of this etching solution to an integrated circuit on an SOI substrate has been clarified for the first time by the present invention.

By using an oxide film obtained by thermally oxidizing the semiconductor substrate as a mask material for etching by TMAH, the adhesion between the mask material and the material to be etched can be improved and the processing accuracy can be improved. The present invention is more preferable when applied to an integrated circuit.

[0020]

EXAMPLES First, examples of embodiments of the present invention will be described.

FIG. 1 is a sectional view showing a preferred embodiment of the present invention. In FIG. 1, 101 is a support substrate, 1
02 is an insulating film, 103 is a semiconductor single crystal layer, and 104 and 10.
5 is an insulating film as a mask material of TMAH, and 106
Is a region where the semiconductor single crystal layer is separated by using TMAH. When TMAH is used, the Si single crystal having the (100) plane as the surface is etched to form the (111) plane at the etching end face. Compared with the etching rate in the (100) plane direction, the etching in the (111) plane direction is orders of magnitude slower, so that the lateral spread of the separation region is suppressed. However, when the insulating film as the mask material is a CVD type film, the adhesion between the semiconductor single crystal layer 103 and the insulating layer 204 in FIG. 2 becomes a problem, and the lateral spread as shown in FIG. 2 occurs. Therefore, in the present embodiment, lateral spread is suppressed by using a thermal oxide film having good adhesion with the semiconductor single crystal layer 103 as the insulating film 104.

Incidentally, the lateral spread caused by the etching may cause a problem such that the insulating film serving as the mask material is peeled off to form particles or the like, and the etching is not uniformly performed. It is also effective as a countermeasure against such a problem, and uniform etching becomes possible.

A method of manufacturing an SOI substrate that can be preferably used in the present invention will be described below with reference to FIGS. Note that, here, an SOI substrate by bonding is taken up, in which variations in the layer thickness of the semiconductor layer are likely to occur due to warpage of the substrates to be bonded, but the present invention can of course be applied to other than such SOI substrates.

As shown in FIG. 3, first, a Si single crystal substrate is prepared and the whole is made porous to form a porous Si substrate 1. Then, epitaxial growth is performed on the surface of the porous substrate to form a thin film single crystal layer 2 of non-porous Si.

Here, the porous Si will be described. S
The i single crystal substrate can be made porous by an anodization method using an HF solution. The porous Si layer has a density of 1.1 to 0.6 g / cm ³ by changing the density of the single crystal Si from 2.33 g / cm ³ to an HF solution concentration of 50 to 20%. It can be changed into a range. The porous layer is easily formed on the P-type Si substrate for the following reasons. According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer.

Porous Si has been described by Uhir et al.
It was discovered in the research process of electropolishing of semiconductors in 1981 (A. Uhril, Bell System. Tech.
J. , Vol 35, p. 333 (1956)). Also, Unami et al. Studied the dissolution reaction of Si in anodization, and reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T Unagami: J. Electrochem. So
c. , Vol. 127, p. 476 (1980)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- where _{SiF 4 + 2HF → H 2 SiF} 6, e + and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the numbers of holes required for dissolving one silicon atom, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied. From the above, P-type silicon having holes is likely to be made porous.

The selectivity in this porosification has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno,
Ohnaka, Kajiwara; IEICE Technical Report, vol 7
9, SSD 79-9549 (1979), (K. Imai; Solid-State Electronics)
vol 24, 159 (1981)). Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area increases dramatically compared to the volume, so the chemical etching rate is
The etching rate is remarkably increased as compared with the etching rate of a normal single crystal layer.

Next, as shown in FIG. 4, a light-transmissive substrate 3 typified by glass as an amorphous substrate is prepared, and a porous S
After the surface of the single crystal Si layer on the i substrate is oxidized, the light transmissive substrate 3 is attached to the formed oxide layer 4. The oxide layer plays an important role in making a device. That is, the interface level generated by the underlying interface of the Si active layer can be lower at the interface level of the oxide film than at the glass interface, and the characteristics of the electronic device are significantly improved. As shown in FIG. 4, as the etching prevention film (protective material), S
An i ₃ N ₄ layer 5 is deposited to cover the entire two bonded substrates, and the Si ₃ N ₄ layer on the surface of the porous silicon substrate is removed. The protective material is coated to protect the thin film single crystal layer 2, the light transmissive substrate 3, and the oxide layer 4 from the etching solution, and is not particularly limited to the Si ₃ N ₄ layer. For example, instead of the Si ₃ N ₄ layer, apiezon wax may be used. It is desirable that the protective material is a material having excellent chemical etching resistance, particularly a material having strong resistance to hydrofluoric acid. After this, the porous Si substrate 1
Are completely etched to form the thin-film single crystal silicon layer 2 on the light-transmissive substrate 3 so as to remain.

The obtained semiconductor substrate is shown in FIG. That is, by removing the Si ₃ N ₄ layer 5 as the etching prevention film in FIG. 4, the single crystal Si layer 2 having the crystallinity equivalent to that of the silicon wafer is flattened on the light transmissive substrate 3,
Moreover, the layer is uniformly thinned and formed in a large area over the entire wafer. The semiconductor substrate thus obtained can be suitably used from the viewpoint of manufacturing an electronic element that is insulated and separated.

The SOI semiconductor substrate thus manufactured is subjected to etching as shown in FIG. 1 according to the present invention to separate elements.

Examples of the present invention will be described below.

FIGS. 6A to 6C are sectional views showing the manufacturing steps of an embodiment of the method for manufacturing a semiconductor substrate of the present invention.

First, a Si epitaxial layer was grown to 0.5 μm on a P-type (100) Si substrate having a thickness of 200 μm by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 1 / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 1 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was about 8.4 μm / min.
And P-type (100) S with a thickness of 200 microns
The entire i-substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer remained unchanged.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidation was performed. Optically polished fused silica glass substrate 601 was placed on the formed thermal oxide film 602 and heated in an oxygen atmosphere at 800 ° C. for 0.5 hour, whereby both substrates were firmly bonded. Si ₃ N ₄ was deposited to a thickness of 0.1 μm by the low pressure CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate was removed by reactive ion etching. As described above, the etching rate of a normal Si single crystal hydrofluoric acid / nitric acid solution is about 1 micron / min (fluorine / nitric acid / acetic acid solution 1: 3: 8), but the etching rate of the porous layer is 100 times that rate. The speed is increased. That is, the porous Si substrate having a thickness of 200 microns was removed in 2 minutes. After removing the Si ₃ N ₄ layer, as shown in FIG. 6A, a single crystal Si layer (Si epitaxial layer) 603 having a thickness of 0.5 μm could be formed on the glass substrate 601. As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

Subsequently, as shown in FIG. 6B, this substrate is subjected to thermal oxidation at 600 ° C. or higher to form a thermal oxide film 604 having good adhesion on the single crystal Si. Next, the thermal oxide film at a desired place is patterned to obtain the opening 605. Here, using TMAH, which is a feature of the present invention, Si
Anisotropic etching of layer 603 is performed. FIG. 7 shows the etching rate of Si with respect to the TMAH concentration. The roughness of the (111) plane changes depending on the TMAH concentration.
% Or less, a good interface can be obtained. Since there is a thermal oxide film on the bottom surface and the surface, this stops etching. In this way, the element isolation region 60 of FIG.
An SOI substrate with 6 is obtained.

The temperature of the TMAH solution is preferably 80 ° C. or lower. This is because when the etching is performed at a temperature higher than 80 ° C., the facet-like residue of the (111) plane is formed on the oxide film, and the residue remains even after overetching.

The (111) Si surface thus obtained is uniform, and the controllability of the separation width is also good.

Next, as a concrete application example, FIG.
On the SOI substrate created by the manufacturing method shown in (c), M
FIG. 8 shows the manufacturing process for forming the OS transistor.
A description will be given using (a) to (c).

First, by the manufacturing process shown in FIGS. 6A to 6C, the SOI having the element region shown in FIG.
Create the board.

Subsequently, as shown in FIG. 8B, a thermal oxide film 607 of 500 Å or less is formed as a gate oxide film. Although the impurity concentration in the single crystal region is different between the enhancement type MOS transistor and the depletion type MOS transistor, when forming an enhancement type PMOS transistor, the concentration of P ⁺ ions is controlled to be about 5E16 cm ⁻³ . Next, the gate electrode 608 is formed and patterned.

Subsequently, as shown in FIG. 8C, the source and drain regions 609 are formed by ion implantation with the gate electrode 608 as self-alignment. After that, an interlayer insulating film 610 is formed, and a source / drain electrode 611 and a gate electrode 608 are drawn out to form a MOS transistor.

Thus, the MO prepared by using the present invention
The V _G -I _D characteristic of the S transistor shown in FIG. The OFF current is orders of magnitude smaller than in the conventional example. This indicates that the charge on the side wall of the element isolation contributes to the control.

When this MOS transistor is applied as a switching transistor of a liquid crystal image display device, the element isolation region becomes a light transmission region (opening), and Si
Even if the single crystal thickness distribution is poor, it is possible to suppress variation in the aperture ratio. Furthermore, since the above-mentioned OFF current is small, a good image can be displayed. FIG. 10 shows a cross-sectional structure of the light transmissive liquid crystal image display device. In FIG. 10, 1001
Is a support of an optically transparent SOI substrate, 1002 is an insulating film,
1003 is a channel portion of a MOS transistor, 1004
Is a gate electrode, 1005 is a source / drain region, 10
Reference numeral 06 is an interlayer insulating film, 1007 is a source electrode (Al, etc.),
Reference numeral 1008 is an interlayer insulating film, 1009 is an ITO (transparent electrode), 1010 is a storage capacitor film, 1011 is a drain electrode ITO (transparent electrode), 1012 is a liquid crystal, 1013 is a counter electrode ITO (transparent electrode), 1014 is a glass substrate. ,
Reference numeral 1015 is a light-shielding Al, and 1016 is a region made light-transmitting by element isolation.

[0046]

As described above, according to the present invention,
By using TMAH to perform element isolation of a semiconductor substrate having a single crystal semiconductor layer provided over an insulating surface, stable and favorable element characteristics can be obtained.

Further, by using the thermal oxide film as the mask material of TMAH, side etching of TMAH is suppressed, and stable and good dimensional accuracy can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example in which a mask material has poor adhesion.

FIG. 3 is a sectional view showing a process flow for producing an SOI substrate that can be preferably used in the present invention.

FIG. 4 is a sectional view showing a process flow for producing an SOI substrate that can be preferably used in the present invention.

FIG. 5 is a sectional view showing a process flow for producing an SOI substrate that can be preferably used in the present invention.

6A to 6C are cross-sectional views showing a manufacturing process of an embodiment of the method for manufacturing a semiconductor substrate of the present invention.

FIG. 7 is a characteristic diagram showing the Si etching rate of a TMAH solution.

8A to 8C are cross-sectional views showing a method for manufacturing a MOS transistor to which the present invention is applied.

FIG. 9 is a V _G − of a MOS transistor to which the present invention is applied.
It is an _ID characteristic figure.

FIG. 10 is a cross-sectional view showing an example in which the present invention is applied to a liquid crystal image display device.

[Explanation of symbols]

101 Support Substrate 102 Insulating Film 103 Semiconductor Single Crystal Layer 104, 105 Insulating Film as Mask Material for TMAH 106 Region where Semiconductor Single Crystal Layer is Separated Using TMAH 1001 SOI Substrate (Light Transmittance) 1002 Insulating Film 1003 Channel part of MOS transistor 1004 Gate electrode 1005 Source / drain region 1006 Interlayer insulating film 1007 Source electrode (Al etc.) 1008 Interlayer insulating film 1009 ITO (transparent electrode) 1010 Storage capacitor film 1011 ITO (transparent electrode) of drain electrode 1012 Liquid crystal 1013 Counter electrode ITO (transparent electrode) 1014 Glass substrate 1015 Light-shielding Al 1016 Area made light transmissive by element isolation

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor substrate having a single crystal semiconductor layer provided on an insulating surface, wherein TMAH (tetramethylammonium hydride) is used for etching the single crystal semiconductor layer. Manufacturing method. 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the single crystal semiconductor layer is silicon and the surface thereof is a (100) plane. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein an oxide film obtained by thermally oxidizing silicon is used as a mask material for TMAH. 4. The method of manufacturing a semiconductor substrate according to claim 3, wherein the TMAH solution temperature is 80 ° C. or lower. 5. A liquid crystal image display device using a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1.