JPH0734471B2 - Field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a field-effect semiconductor device, here, a power MO.
S field effect transistor (hereinafter referred to as power MOS FET)
More specifically, the present invention relates to improvement of a high-breakdown-voltage power MOS FET with low on-resistance.

[Prior Art] In recent years, a power MOS FET of this kind has attracted attention as a switching element for electric power.

FIG. 2 shows an outline of a sectional structure schematically showing a power MOS FET having a general vertical D-MOS structure according to a conventional example.

That is, in the conventional configuration shown in FIG. 2, n ⁺
In this case, the shaped substrate 21 is generally about 10 ¹⁹ atom / cm ³
In such a slow diffusion speed Sb is used and the n n ⁺ is epitaxially grown on the shape the substrate 21 ^- -type epitaxial layer 22, Yotsute the blocking voltage V _B that is required in the device structure, its resistivity and The thickness is set, for example, in the device configuration of 500 V, the specific resistance is about 25 Ω-cm and the thickness is about
It is set to about 45 μm.

The p-type base layer 23 selectively formed on the main surface (second main surface) of the n ⁻ -type epitaxial layer 22 is a relatively shallow diffused second region portion forming the channel region 25. 23b and n formed on the surface of the p-type base layer 23
And a first region portion 23a formed relatively deeply to prevent latch-up of a parasitic transistor constituted by the ^{+ type} source layer 24, the p type base layer 23, and the n ^{− type} epitaxial layer 22. ing.

Then, the n ^{+ type} source layer 24 and the n ^{− type} epitaxial layer 22
A gate electrode 27 covering the n ⁻ -type epitaxial layer 22 and a gate insulating film 26 is formed on the channel region 25 formed between the first and second regions 23a to 23a of the p-type base layer 23.
^The source electrode 28 straddles the ^{+ type} source layer 24, and the n ^{+ type} substrate 2
Drain electrodes 29 are formed on the back surface of 1 respectively.

Then, the power MO in the conventional example configured as described above
In the S FET, the source electrode 28 is grounded and the gate electrode 2
When a positive voltage is applied to 7 and the drain electrode 29, p
The channel region 25 in the n-type base layer 23 is inverted to the n-type, and the inverted channel region 25 from the n ^{+ -type} source layer 24 and the n ⁻ -type epitaxial layer 2 as shown by the broken line e in the figure.
Electrons flow through the drain electrode 29 through 2 to be in the ON state.

At this time, the on-resistance R _on of the element can be approximately represented by the following equation. _{That, R on = R ch + R} ac + R j + R Epi However, R _ch: the resistance of the channel region 25, R _ac: n ^- Akyamu Configuration resistance of the surface of the -type epitaxial layer 22, R _j: p-type base layer resistance -type epitaxial layer 22, R _Epi ^- n indicating the JFET effect which is sandwiched by the 23: n ^- resistance -type epitaxial layer 22. Is.

Here, each of the resistors R _ch and R _ac can be reduced together by miniaturizing the unit cell of the MOS FET, and the resistor R _j can be separated from each other between the p-type base layers 23. It can be reduced by spreading it properly,
Since R _Epi is determined by the relationship with the blocking voltage V _B, it occupies most of the on-resistance R _on in the high breakdown voltage element. In this case, for example, in the element configuration of 500 V, 1000 V, Since R _Epi / R _on is about 0.8 and 0.9, how to reduce the resistance R _Epi is a major point for improving the characteristics of this type of high breakdown voltage MOS FET.

[Problems to be solved by the invention]

As described above, in the power MOS FET having the conventional configuration, when the breakdown voltage of the element increases, the on-resistance in the n ^{− type} epitaxial layer that defines the blocking voltage V _B increases, and the on-loss increases. Atsuta

Therefore, the purpose of this invention is
In view of such problems in the MOS FET, the resistance R _Epi in the n ^{− type} epitaxial layer is reduced and the resistance R _j is also reduced to improve the characteristics of the element structure. This type of field-effect semiconductor device has a low on-resistance and a high withstand voltage, and this is to provide a high withstand voltage power MOS FET with a low on-resistance.

[Means for solving problems]

To achieve the above object, a field-effect semiconductor device according to the present invention is an n ^{+ -type} substrate doped with an impurity having a smaller impurity diffusion coefficient than P, and a P-doped substrate disposed on the substrate. Formed n-type buffer layer, an n ⁻ -type epitaxial layer disposed through a junction surface with the buffer layer, and a n-type epitaxial layer formed in the junction surface of the epitaxial layer and between the substrate and the epitaxial layer. A floating region for giving a gradual impurity concentration distribution, a first region portion that is selectively formed on the main surface of the epitaxial layer, and a central portion thereof, and a depth to the bottom portion provided at the periphery of the first region portion. A p-type base region consisting of a second region portion shallower than the first region portion, an n-type source region selectively formed on the surface of the base region, the source region and the epitaxial layer. A gate electrode formed on the surface of the second region portion of the base region sandwiched by a gate insulating film, a source electrode formed over the first region portion of the base region and the source region, and formed on the substrate. And a drain electrode.

[Action]

Therefore, in the present invention, the on-resistance R in the element configuration is
The on-resistance R _on can be sufficiently reduced because the layer thickness of the n ^{− type} epitaxial layer that most significantly affects _on is reduced to about 1/2, and in this case, n
Forms a buffer layer, and the n ^- type it is necessary to consider the resistance in the raised area of the n-type buffer layer on the epitaxial layer side, but the average specific resistance of the same the raised region, the n ^- type epitaxial layer The on-resistance R _on in the floating region is set to 1/10 or less of the specific resistance of
The influence on the impurity concentration distribution at the n ⁺ , n ^- junction is determined by the electric field of the depletion layer extending when a high voltage is applied to the device. to be by connexion relaxed Yururu Ya kana inclined, though, n ^- even when the thickness of the -type epitaxial layer is thin, the blocking voltage
V _B is not likely to be impaired, and as a result, a power MOS FET with low on-resistance and high element breakdown voltage can be obtained.

〔Example〕

An embodiment of a field effect semiconductor device according to the present invention, a power MOS FET here, will be described in detail below with reference to FIG.

FIG. 1 is a sectional view schematically showing a schematic structure of a power MOS FET to which this embodiment is applied. In the structure of the embodiment of FIG. 1, the same symbols as those of the structure of the conventional example of FIG. Represents a part.

That is, even in the configuration of the embodiment shown in FIG.
In this case, the n ^{+ -type} substrate 21 is generally about 10 ¹⁹ atom / c.
m ³ of about n-type impurity, for example, such as slow Sb is doped diffusion speed, on the n ⁺ -type substrate 21 is about 0.05
About 0.5 ~ 0.5Ω-cm phosphorus-doped n-type buffer layer 10
Epitaxially grow to a thickness of about 0 μm, and
On the n-type buffer layer 10, n has a high resistivity of about 30 [Omega-cm ^- to form the shape epitaxial layer 22 to a thickness of about 20 [mu] m, followed by heat treatment, the n-type buffer layer 10 Are raised toward the n ⁻ -type epitaxial layer 22 side to form a floating region 11, and a gentle impurity concentration distribution is provided between the n ^{+ -type} substrate 21 and the n ⁻ -type epitaxial layer 22.

Next, the first region of each p-type base layer 23 is opposed to the second main surface of the n ⁻ -type epitaxial layer 22 by a depth of about 6 to 10 μm by an ion implantation method or a selective diffusion method. part
After selectively forming 23a respectively, a gate insulating film 26 is formed on them, and a polysilicon layer to be a gate electrode 27 later is selectively formed via the gate insulating film 26, and Using this polysilicon layer as a mask, the second region portions 23b of each p-type base layer 23 are selectively formed. And each of these second area portions 23
Since b becomes the channel region 25 later, it is necessary to select its impurity concentration and diffusion depth in relation to the threshold voltage V _th , and normally, the value is 5
The depth may be about 4 to 8 μm in the range of about 10 ^{13 to} 5 × ¹⁴ .

Next, each of the p-type base layers 23 has a surface concentration of about 3 × 10 ²⁰ atom / cm ³ by the D-MOS method using the above-mentioned polysilicon layer as a mask. The n ^{+ type} source layer 24 is selectively formed to a depth of about 0.5 to 1 μm. Each first sandwiched between each of these n ⁺ -type source layer 24 and the n-type epitaxial layer 22 above 2
The surface portion of the region portion 23b becomes the above-mentioned channel region 25, and normally, the length of this channel region 25 is high withstand voltage MO.
S FET has a thickness of about 3 to 5 μm.

Further, each of the n ^{+ type} source layer 24 and the n ^{− type} epitaxial layer
On the respective channel regions 25 formed between the gate insulating film 26 and the n-type epitaxial layer 22,
The gate electrode 27 through the first electrode of each p-type base layer 23.
The source electrode 28 extends from the region 23a to the n ^{+ -type} source layer 24.
And a drain electrode 29 is formed on the back surface of the n ^{+ -type} substrate 21, respectively.

Therefore, the power of this embodiment configured as described above
In the MOS FET, the thickness of the n ⁻ -type epitaxial layer 22 is reduced, that is, specifically, in the case of this embodiment,
It is set to about 15 to 20 μm, and when compared with the thickness of the same layer of about 35 to 40 μm in the case of the conventional example, the value of the resistance R _Epi is drastically reduced because it is thinned to about 1/2. It can be reduced. At this time, the total thickness of the n-type buffer layer 10 and the floating region 11, which is formed instead of this, is about
Although it is about 40 μm, its average specific resistance is 1/10 or less, so even if it is converted into the n ⁻ -type epitaxial layer 22, it is only about 4 μm at the most. When compared to the example, the on-resistance R _on can be reduced to about 30%.

That is, as described above, according to the power MOS FET in the configuration of this embodiment, the value of the on-resistance R _on is improved by about 35 to 40% as compared with that of the configuration of the conventional example. You can do it.

Incidentally, in the above-mentioned examples, the element structure having a breakdown voltage of 500 V was described, but even with a high breakdown voltage element having a breakdown voltage of 500 V or more, the specific resistance and thickness of the n ^{− type} epitaxial layer corresponding to each breakdown voltage, resistivity and thickness of the n-type buffer layer, and the n of the n-type buffer layer ^- of such thickness the raised to form an epitaxial layer by appropriately setting, in which similar action, the effect is obtained Although, in this embodiment, the case where the p-type is used as the first conductivity type and the n-type is used as the second conductivity type, it is needless to say that it is effective to reverse these conductivity types.

〔The invention's effect〕

As described above in detail, in the field effect semiconductor device according to the present invention, an n ^{+ -type} substrate doped with an impurity having a smaller impurity diffusion coefficient than P and a P-doped substrate disposed on this substrate are doped. A n-type buffer layer and an n ⁻ -type epitaxial layer formed through a junction surface with the buffer layer, and a n-type epitaxial layer formed in the junction surface between the epitaxial layer and the substrate and the epitaxial layer. A floating region for giving an impurity concentration distribution, and a first region portion which is selectively formed on the main surface of the epitaxial layer and which is a central portion thereof and a peripheral portion of the first region portion, the depth to the bottom is It is sandwiched between a p-type base region including a second region portion shallower than the first region portion, an n-type source region selectively formed on the surface of the base region, and the source region and the epitaxial layer. A gate electrode formed on the surface of the second region portion of the base region via a gate insulating film, a source electrode formed over the first region portion of the base region and the source region, and a drain formed on the substrate. Since it is provided with an electrode, it is possible to sufficiently reduce the on-resistance R _on in the element configuration, and also with respect to the breakdown voltage in this element configuration, the electric field of the depletion layer extending when a high voltage is applied,
Since the impurity concentration distribution at the junction is moderated by a gentle slope, even if the epitaxial layer is made thin, its blocking voltage V _B is not likely to be impaired. Low power MOSFET with high breakdown voltage
In addition, it has the excellent features that it can be obtained and is relatively simple in structure and can be easily implemented.

[Brief description of drawings]

FIG. 1 shows a power MOS to which an embodiment of the device of the present invention is applied.
FIG. 2 is a cross-sectional view schematically showing the general structure of the FET, and FIG. 2 is a cross-sectional view schematically showing the general structure of the same power MOS FET as the conventional example. 10 …… n-type buffer layer, 11 …… floating region, 21 …… n ⁺
Form substrate, 22 ...... n ^- -type epitaxial layer, 23 ...... p-type base layer, 24 ...... n ⁺ -type source layer 25 ...... channel region, 26 ...
… Gate insulating film, 27 …… Gate electrode, 28 …… Source electrode, 29 …… Drain electrode.

Claims (1)

[Claims] 1. An n ^{+ -type} substrate doped with an impurity having an impurity diffusion coefficient smaller than P, an n-type buffer layer doped with P and disposed on the substrate, and the buffer layer. And an n ⁻ -type epitaxial layer formed via the junction surface of the epitaxial layer, and a floating region formed in the junction surface of the epitaxial layer for providing a gentle impurity concentration distribution between the substrate and the epitaxial layer. And a first region portion which is selectively formed on the main surface of the epitaxial layer and which is provided at the center of the first region portion and at the periphery of the first region portion and has a depth to the bottom that is shallower than that of the first region portion. A p-type base region composed of two regions, an n-type source region selectively formed on the surface of the base region, and a second region portion sandwiched between the source region and the epitaxial layer. A gate electrode formed on the surface via a gate insulating film, a source electrode formed over the first region of the base region and the source region, and a drain electrode formed on the substrate. Field effect semiconductor device.