JPH07263575A - Mos-type semiconductor memory device and manufacture thereof - Google Patents
Mos-type semiconductor memory device and manufacture thereofInfo
- Publication number
- JPH07263575A JPH07263575A JP6055485A JP5548594A JPH07263575A JP H07263575 A JPH07263575 A JP H07263575A JP 6055485 A JP6055485 A JP 6055485A JP 5548594 A JP5548594 A JP 5548594A JP H07263575 A JPH07263575 A JP H07263575A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- type semiconductor
- semiconductor memory
- memory device
- mos type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 29
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 230000010354 integration Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000003071 parasitic effect Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳ型半導体記憶装
置及びその製造方法に関する。特にＳＯＩ構造を有する
ＭＯＳ型半導体記憶装置及びその製造方法に関するもの
である。ＳＯＩ（Ｓｉｌｉｃｏｎ ｏｎ Ｉｎｓｕｌａ
ｔｏｒ）構造とは、絶縁材料上に島状にＳｉ部分が形成
され、このＳｉ部分（ＳＯＩ層）に各種デバイス等を形
成するものを通常指すが、本明細書においては、一般
に、絶縁材料上に半導体材料が形成されて周囲と素子分
離された構造をＳＯＩ構造の語をもって総称する。また
本明細書においては、「ＭＯＳ」の語は、メタル−酸化
物絶縁材−半導体のみならず、一般に導電材−絶縁材−
半導体の構造のものを含む概念として用いられる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor memory device and a method of manufacturing the same. In particular, it relates to a MOS type semiconductor memory device having an SOI structure and a method for manufacturing the same. SOI (Silicon on Insula)
The (tor) structure generally refers to a structure in which island-shaped Si portions are formed on an insulating material, and various devices are formed on the Si portion (SOI layer), but in the present specification, generally, on the insulating material. A structure in which a semiconductor material is formed and is isolated from the surroundings is collectively referred to as an SOI structure. Further, in the present specification, the term "MOS" generally refers to not only metal-oxide insulating material-semiconductor but also conductive material-insulating material-
It is used as a concept including those of a semiconductor structure.
【０００２】[0002]
【従来の技術】図１２は、従来の方法を用いて作製した
ＳＯＩ構造の素子を有するＭＯＳ型半導体記憶装置の断
面図である。素子分離領域をも兼ねる埋め込み酸化膜層
２０が形成されており、その上にシリコン層３が島状に
存在している。2. Description of the Related Art FIG. 12 is a cross-sectional view of a MOS semiconductor memory device having an SOI structure element manufactured by a conventional method. A buried oxide film layer 20 which also serves as an element isolation region is formed, and the silicon layer 3 is present thereon in an island shape.
【０００３】メモリセル領域Ｉでは、集積度を上げるた
め、できるだけ小さなゲート寸法を用いることが好まし
く、そのような構造をとることが普通である。一方、周
辺回路領域ＩＩでは、メモリセル部のトランジスタに比
べ、ゲート寸法は大きくすることが可能である。In the memory cell region I, it is preferable to use as small a gate size as possible in order to increase the degree of integration, and such a structure is usually adopted. On the other hand, in the peripheral circuit region II, the gate size can be made larger than that of the transistor in the memory cell section.
【０００４】ところで、ＳＯＩトランジスタは、ゲート
寸法が小さくなると、ゲートの支配力の及ばないシリコ
ン層の下層の部分でパンチスルーを起こしやすいという
問題がある。この問題は、埋め込み酸化膜を薄膜化する
ことで解決される。このため、例えば埋め込み酸化膜厚
を実効ゲート長以下にする必要があるというような報告
がなされている。（大村泰久ら「高速ＣＭＯＳ／ＳＩＭ
ＯＸデバイス技術」（電子情報通信学会技術研究報告
（１９９１年）ｐ１７２）参照）。Incidentally, the SOI transistor has a problem that when the gate size is reduced, punch-through is likely to occur in the lower layer portion of the silicon layer, which is not controlled by the gate. This problem is solved by thinning the buried oxide film. Therefore, for example, it is reported that the buried oxide film thickness needs to be equal to or less than the effective gate length. (Yasuhisa Omura et al. "High-speed CMOS / SIM
OX device technology "(see Technical Report of the Institute of Electronics, Information and Communication Engineers (1991) p172)).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、埋め込
み酸化膜を薄膜化すると、寄生容量が増大して回路の高
速化を妨げるという問題点がある。バルク素子と比較し
てＳＯＩ素子が高速であるのは、寄生容量の少なさによ
るとことろが大きい。埋め込み酸化膜を薄膜化すること
により接合容量や配線容量などが増大してしまっては、
高速化可能という利点を発揮できないということにな
り、バルクに対する優位性が小さくなってしまう。However, when the buried oxide film is thinned, there is a problem that the parasitic capacitance increases and the speedup of the circuit is hindered. The high speed of the SOI device compared with the bulk device is largely due to the small parasitic capacitance. If the junction capacitance, wiring capacitance, etc. are increased by thinning the embedded oxide film,
This means that the advantage of being able to speed up cannot be exhibited, and the advantage over bulk is diminished.
【０００６】本発明は、このような従来の問題点に着目
して創案されたものであって、ＳＯＩ素子を有するＭＯ
Ｓ型半導体記憶装置において、高集積化と高速化を同時
に実現できるＭＯＳ型半導体記憶装置及びその製造方法
を提供することを目的とする。The present invention was devised by focusing on such a conventional problem, and an MO having an SOI element was proposed.
It is an object of the present invention to provide a MOS type semiconductor memory device and a method of manufacturing the same which can realize high integration and high speed in an S type semiconductor memory device at the same time.
【０００７】[0007]
【目的を達成するための手段】上記課題は、本発明によ
れば、ＳＯＩ構造の素子を有するＭＯＳ型半導体記憶装
置において、メモリセルの埋め込み酸化膜の膜厚を周辺
回路のそれよりも薄くすることによって解決される。即
ち、上記目的は、以下の各発明によって達成される。According to the present invention, in the MOS type semiconductor memory device having an SOI structure element, the buried oxide film of the memory cell is made thinner than that of the peripheral circuit. Will be solved by That is, the above object is achieved by the following inventions.
【０００８】本出願の請求項１の発明は、ＳＯＩ構造を
備えるＭＯＳ型半導体記憶装置において、メモリセルの
埋め込み絶縁膜の膜厚を周辺回路の絶縁膜よりも薄くす
ることを特徴とするＭＯＳ型半導体記憶装置であって、
これにより上記目的を達成するものである。According to the invention of claim 1 of the present application, in a MOS type semiconductor memory device having an SOI structure, the embedded insulating film of the memory cell is made thinner than the insulating film of the peripheral circuit. A semiconductor memory device,
This achieves the above object.
【０００９】本出願の請求項２の発明は、メモリセルの
埋め込み絶縁膜の膜厚は、メモリセルを構成するＭＯＳ
型半導体装置の実効ゲート長よりも小さいものとするこ
とを特徴とする請求項１に記載のＭＯＳ型半導体記憶装
置であって、これにより上記目的を達成するものであ
る。According to the invention of claim 2 of the present application, the film thickness of the embedded insulating film of the memory cell is the same as that of the MOS constituting the memory cell.
The MOS type semiconductor memory device according to claim 1, wherein the effective gate length is smaller than the effective gate length of the type semiconductor device.
【００１０】本出願の請求項３の発明は、ＳＯＩ構造を
備えるＭＯＳ型半導体記憶装置の製造方法であって、半
導体基板上にＳＯＩ半導体層となる凸部を形成し、更に
素子分離領域となる埋め込み絶縁膜を形成し、該絶縁膜
の内メモリセルの埋め込み絶縁膜となる部分を薄膜化
し、その後はり合わせの台となる基板をはり合わせては
り合わせ研磨法によりＳＯＩ構造を形成することによっ
て、メモリセルの埋め込み絶縁膜の膜厚を周辺回路の絶
縁膜の膜厚よりも薄く形成することを特徴とするＭＯＳ
型半導体記憶装置の製造方法であって、これにより上記
目的を達成するものである。A third aspect of the present invention is a method of manufacturing a MOS type semiconductor memory device having an SOI structure, which comprises forming a convex portion to be an SOI semiconductor layer on a semiconductor substrate and further forming an element isolation region. By forming a buried insulating film, thinning a portion of the insulating film to be a buried insulating film of a memory cell, and then laminating substrates to be a base for laminating and forming an SOI structure by a lapping polishing method, A MOS characterized in that the film thickness of the buried insulating film of the memory cell is formed thinner than the film thickness of the insulating film of the peripheral circuit.
A method for manufacturing a semiconductor memory device, which achieves the above object.
【００１１】本出願の請求項４の発明は、ＳＯＩ構造を
備えるＭＯＳ型半導体記憶装置の製造方法であって、半
導体基板の内部にイオン注入により絶縁膜を形成し、更
に該絶縁膜の内周辺回路領域の埋め込み絶縁膜となる部
分に更にイオン注入を行って絶縁部を厚膜化することに
よって、メモリセルの埋め込み絶縁膜の膜厚を周辺回路
の絶縁膜の膜厚よりも薄く形成することを特徴とするＭ
ＯＳ型半導体記憶装置の製造方法であって、これにより
上記目的を達成するものである。According to a fourth aspect of the present invention, there is provided a method for manufacturing a MOS type semiconductor memory device having an SOI structure, wherein an insulating film is formed inside a semiconductor substrate by ion implantation, and the inner periphery of the insulating film is further formed. To form the embedded insulating film of the memory cell to be thinner than the insulating film of the peripheral circuit by further ion-implanting a portion of the circuit region to be the embedded insulating film to thicken the insulating portion. M characterized by
A method of manufacturing an OS type semiconductor memory device, which achieves the above object.
【００１２】[0012]
【作用】本発明によれば、ＳＯＩ素子を有するＭＯＳ型
半導体記憶装置において、メモリセルのアレイの埋め込
み絶縁膜の膜厚を周辺回路のそれよりも薄くすることに
より、メモリセル内では素子の微細化が可能であり、一
方、周辺回路の素子の寄生容量を増加させることがない
ため、高集積化と高速化を同時に実現できる。According to the present invention, in a MOS type semiconductor memory device having an SOI element, the thickness of the buried insulating film of the array of memory cells is made smaller than that of the peripheral circuit, so that the elements in the memory cell can be made finer. On the other hand, since the parasitic capacitance of the elements of the peripheral circuit is not increased, high integration and high speed can be realized at the same time.
【００１３】[0013]
【実施例】以下本発明の実施例について、図面を参照し
て説明する。但し当然のことではあるが、本発明は図示
の実施例により限定を受けるものではない。Embodiments of the present invention will be described below with reference to the drawings. However, it should be understood that the present invention is not limited to the illustrated embodiments.
【００１４】実施例１ この実施例は、本発明を、はり合わせ法を用いてＳＯＩ
基板を形成し、これによりＳＯＩ構造を備えるＭＯＳ型
半導体記憶装置を得る場合に適用したものである。Example 1 This example illustrates the present invention using the bonding method to SOI.
This is applied when a substrate is formed to obtain a MOS type semiconductor memory device having an SOI structure.
【００１５】図１に、本実施例のＭＯＳ型半導体記憶装
置の断面図を示す。図１に示すように、本実施例は、Ｓ
ＯＩ構造を備えるＭＯＳ型半導体記憶装置において、メ
モリセルの埋め込み絶縁膜２１の膜厚Ｔ1 を周辺回路の
絶縁膜２２の膜厚Ｔ2 よりも薄くした構造をとっている
（図１中、符号Ｉでメモリセル領域を示し、符号ＩＩで
周辺回路領域を示す）。FIG. 1 shows a sectional view of a MOS type semiconductor memory device of this embodiment. As shown in FIG. 1, in this embodiment, S
In the MOS type semiconductor memory device having the OI structure, the film thickness T 1 of the embedded insulating film 21 of the memory cell is smaller than the film thickness T 2 of the insulating film 22 of the peripheral circuit (in FIG. 1, reference numeral). I indicates a memory cell area, and reference numeral II indicates a peripheral circuit area).
【００１６】更に詳しくは、本実施例のＭＯＳ型半導体
記憶装置は、埋め込み絶縁膜２（ここでは酸化膜層）の
上に島状に半導体層（シリコン層）３が形成されてお
り、素子は、メモリセル領域Ｉと周辺回路ＩＩとではサ
イズが異なっており、メモリセル領域Ｉの方がサイズが
小さくなっている。また、メモリセル領域Ｉと周辺回路
領域ＩＩとでは埋め込み絶縁膜２（酸化膜）の膜厚が異
なっており、メモリセル領域Ｉにおける膜厚Ｔ1 は、周
辺回路領域ＩＩにおける膜厚Ｔ2 より小さくなってい
る。More specifically, in the MOS semiconductor memory device of this embodiment, the semiconductor layer (silicon layer) 3 is formed in an island shape on the buried insulating film 2 (here, an oxide film layer), and the element is The memory cell region I and the peripheral circuit II have different sizes, and the memory cell region I has a smaller size. Further, the film thickness of the embedded insulating film 2 (oxide film) is different between the memory cell region I and the peripheral circuit region II, and the film thickness T 1 in the memory cell region I is larger than the film thickness T 2 in the peripheral circuit region II. It is getting smaller.
【００１７】本実施例ではこのようにメモリセルの埋め
込み絶縁膜２１の膜厚Ｔ1 を周辺回路の絶縁膜２２の膜
厚よりも薄くすることにより、メモリセルの短チャネル
効果を防ぎ、さらに周辺回路の寄生容量を増やすことが
なく、高集積化と高速化を同時に実現できた。In this embodiment, the thickness T 1 of the embedded insulating film 21 of the memory cell is made smaller than the thickness of the insulating film 22 of the peripheral circuit in this way, so that the short channel effect of the memory cell is prevented and the peripheral portion is further prevented. High integration and high speed could be realized at the same time without increasing the parasitic capacitance of the circuit.
【００１８】以下、この実施例のＭＯＳ型半導体記憶装
置の製造方法の詳細を、図２ないし図７に基づいて説明
する。この実施例においては、基板はり合わせ法を用い
てＳＯＩ基板を形成して、ＭＯＳ型半導体記憶装置を得
る。The details of the method of manufacturing the MOS type semiconductor memory device of this embodiment will be described below with reference to FIGS. In this embodiment, an SOI substrate is formed by using the substrate bonding method to obtain a MOS type semiconductor memory device.
【００１９】即ち本実施例では、半導体基板１上にＳＯ
Ｉ半導体層となる凸部１１ａを形成し（図２）、更に素
子分離領域となる埋め込み絶縁膜２を形成し（図３）、
該絶縁膜２の内メモリセルの埋め込み絶縁膜となる部分
を薄膜化し（図４）、その後はり合わせの台となる基板
をはり合わせてはり合わせ研磨法によりＳＯＩ構造を形
成することによって（図５〜図７）、メモリセルの埋め
込み絶縁膜の膜厚を周辺回路の絶縁膜の膜厚よりも薄く
形成する。That is, in this embodiment, SO is deposited on the semiconductor substrate 1.
The convex portion 11a to be the I semiconductor layer is formed (FIG. 2), and the buried insulating film 2 to be the element isolation region is further formed (FIG. 3).
By thinning a portion of the insulating film 2 to be a buried insulating film of a memory cell (FIG. 4), and then laminating substrates to be a base for laminating, an SOI structure is formed by a lapping method (FIG. 5). 7 to 7), the film thickness of the embedded insulating film of the memory cell is formed thinner than the film thickness of the insulating film of the peripheral circuit.
【００２０】更に詳しくは、本実施例ではまず、図２に
示すように、半導体（ここではシリコン）基板１をエッ
チングして該シリコン基板１に段差を形成する。段差の
凸部１１ａが後に島状の半導体層（シリコン層）となっ
て拡散層となり、凹部１２ａが素子分離領域となる。More specifically, in this embodiment, first, as shown in FIG. 2, a semiconductor (here, silicon) substrate 1 is etched to form a step in the silicon substrate 1. The convex portion 11a of the step later becomes an island-shaped semiconductor layer (silicon layer) to become a diffusion layer, and the concave portion 12a becomes an element isolation region.
【００２１】次に、図３に示すように、シリコン基板１
に、必要があれば、２０〜１００ｎｍ程度表面酸化を施
したのち、ＣＶＤ等により絶縁膜２をなす酸化膜を堆積
する。この酸化膜２は後に埋め込み絶縁膜（酸化膜）と
なるものであり、膜厚は周辺回路のトランジスタのゲー
ト長から設定されなければならない。Next, as shown in FIG. 3, the silicon substrate 1
Then, if necessary, after performing surface oxidation of about 20 to 100 nm, an oxide film forming the insulating film 2 is deposited by CVD or the like. This oxide film 2 will later become a buried insulating film (oxide film), and the film thickness must be set from the gate length of the transistor of the peripheral circuit.
【００２２】続いて、図４に示すように、レジストをパ
ターニングしてこのレジストパターン６をマスクとして
メモリセル領域Ｉの酸化膜２のみをエッチングする。模
式的に符号ＩＩＩでエッチングを示し、また、破線でエ
ッチング前の絶縁膜（酸化膜）２を示す。ここで、残さ
れる酸化膜２（２１）の膜厚Ｔ1 は、メモリセルのトラ
ンジスタの実効ゲート長よりも小さくなるように設定さ
れなければならない。例えば実施例では、実効ゲート長
は０．４ｎｍ以下の微細構造としたので、酸化膜２１の
膜厚Ｔ1 は、該実効ゲート長未満とした。Then, as shown in FIG. 4, a resist is patterned and only the oxide film 2 in the memory cell region I is etched using the resist pattern 6 as a mask. The etching is schematically indicated by reference numeral III, and the insulating film (oxide film) 2 before etching is indicated by the broken line. Here, the film thickness T 1 of the remaining oxide film 2 (21) must be set to be smaller than the effective gate length of the transistor of the memory cell. For example, in the embodiment, since the effective gate length is 0.4 nm or less, the film thickness T 1 of the oxide film 21 is less than the effective gate length.
【００２３】その後は、図５に示すように、はり合わせ
のバッファとなる膜、たとえば、ポリシリコン膜４など
を厚く（例えば〜５μｍ）堆積して、それを平坦化研磨
することにより、高度に平滑なはり合わせ面とする。図
５中、符号ＩＶで模式的に平坦化研磨を示す。Thereafter, as shown in FIG. 5, a film serving as a laminating buffer, for example, a polysilicon film 4 or the like is deposited thickly (for example, to 5 μm), and is flattened and polished to obtain a high degree. Use a smooth bonded surface. In FIG. 5, reference numeral IV schematically indicates flattening polishing.
【００２４】次に、図６に示すように、もう１枚のシリ
コン基板５（はり合わせの台となる基板）とはり合わ
せ、ひっくり返す。符号Ｖではり合わせを模式的に示
す。Next, as shown in FIG. 6, another silicon substrate 5 (a substrate that serves as a laminating base) is laminated and turned over. Reference numeral V schematically shows the bonding.
【００２５】ひっくり返して図５と図６で上下を逆にし
たのは、面取りや研削のため、上下を逆にして基板１を
上側にしたためである。5 and 6 are turned upside down so that the substrate 1 is turned upside down so that the substrate 1 is turned upside down for chamfering or grinding.
【００２６】もとのシリコン基板１を裏側（図６の上
側）から研削・研磨し、更に絶縁膜（酸化膜）２をスト
ッパーとして選択研磨を行い、島状に半導体層（シリコ
ン）３を残す。これにより図７の構造を得る。符号ＶＩ
で、研削・選択研磨を模式的に示す。The original silicon substrate 1 is ground and polished from the back side (upper side in FIG. 6), and further, selective polishing is performed using the insulating film (oxide film) 2 as a stopper to leave the semiconductor layer (silicon) 3 in an island shape. . As a result, the structure shown in FIG. 7 is obtained. Code VI
Here, the grinding and selective polishing are schematically shown.
【００２７】その後、ゲート酸化膜７１、ゲート電極７
などを形成してトランジスタを形成し、図１のＭＯＳ型
半導体記憶装置を得る。After that, the gate oxide film 71 and the gate electrode 7 are formed.
Are formed to form a transistor, and the MOS type semiconductor memory device of FIG. 1 is obtained.
【００２８】以上に説明したように、本実施例のＳＯＩ
構造を備えるＭＯＳ型半導体記憶装置にあっては、メモ
リセルの埋め込み酸化膜の膜厚を周辺回路のそれよりも
薄くすることにより、メモリセル内では素子の微細化が
可能であり、一方、周辺回路の素子の駆動能力を低下さ
せることがないため、高集積化と高速化を同時に実現で
きた。As described above, the SOI of this embodiment
In the MOS type semiconductor memory device having the structure, by making the film thickness of the buried oxide film of the memory cell thinner than that of the peripheral circuit, it is possible to miniaturize the elements in the memory cell, while Since the driving ability of the elements of the circuit is not deteriorated, high integration and high speed can be realized at the same time.
【００２９】実施例２ 図８ないし図１０に、本発明の第２の実施例を示す。こ
の実施例は、いわゆるＳＩＭＯＸ法を用いてＳＯＩ構造
を形成して、ＭＯＳ型半導体記憶装置を得る例である。Embodiment 2 FIGS. 8 to 10 show a second embodiment of the present invention. This embodiment is an example of obtaining a MOS type semiconductor memory device by forming an SOI structure by using the so-called SIMOX method.
【００３０】即ち、本実施例では、半導体基板の内部に
イオン注入（ここではＳｉ基板１内部へのＯ2 のイオン
注入）により絶縁膜１１を形成し（図８）、更に該絶縁
膜１１の内周辺回路領域ＩＩの埋め込み絶縁膜となる部
分に等にイオン注入を行って絶縁部を膜厚化する（図１
０）ことによって、メモリセルの埋め込み絶縁膜の膜厚
を周辺回路の絶縁膜の膜厚よりも薄く形成する。That is, in this embodiment, the insulating film 11 is formed inside the semiconductor substrate by ion implantation (here, the ion implantation of O 2 into the Si substrate 1) (FIG. 8), and the insulating film 11 is further formed. Ion implantation is performed to the portion to be the buried insulating film in the inner peripheral circuit region II to thin the insulating portion (FIG. 1).
As a result, the film thickness of the embedded insulating film of the memory cell is formed thinner than the film thickness of the insulating film of the peripheral circuit.
【００３１】更に詳しくは、本実施例においては、ま
ず、図８に示すように、絶縁部を与えるイオン注入、こ
こでは代表的な酸素イオンのイオン注入及び熱処理を行
うことにより、通常のＳＩＭＯＸ基板８を形成する。こ
れによって、基板１の内部に絶縁膜１１が形成され、そ
の上部が半導体層１２となっているＳＩＭＯＸ基板８を
得て、次工程に入る。More specifically, in the present embodiment, first, as shown in FIG. 8, an ordinary SIMOX substrate is prepared by performing ion implantation for providing an insulating portion, here representative ion implantation of oxygen ions and heat treatment. 8 is formed. As a result, the SIMOX substrate 8 in which the insulating film 11 is formed inside the substrate 1 and the upper portion thereof is the semiconductor layer 12 is obtained, and the next step is performed.
【００３２】次に、図９に示すようにメモリセル領域Ｉ
のみをレジストマスク９によりマスキングする。Next, as shown in FIG. 9, the memory cell region I
Only the resist mask 9 is masked.
【００３３】更に高エネルギーで酸素をイオン注入す
る。これにより図１０に示すように、新たにイオン注入
層１０を形成する。Oxygen is ion-implanted with higher energy. Thereby, as shown in FIG. 10, a new ion implantation layer 10 is formed.
【００３４】更に熱処理を加え、メモリセル部と周辺回
路部とで埋め込み酸化膜１１の膜厚の異なるＳＯＩ基板
を作製する（図１１）。Further, heat treatment is performed to manufacture an SOI substrate in which the thickness of the buried oxide film 11 is different between the memory cell portion and the peripheral circuit portion (FIG. 11).
【００３５】その後は、ＬＯＣＯＳ法などを用いて素子
分離し、ゲート酸化膜、ゲート電極を形成し、トランジ
スタを形成する。After that, element isolation is performed by using the LOCOS method or the like, a gate oxide film and a gate electrode are formed, and a transistor is formed.
【００３６】本実施例によって得られたＭＯＳ型半導体
記憶装置も、実施例１の装置と同様の効果を有する。The MOS type semiconductor memory device obtained in this embodiment also has the same effect as the device of the first embodiment.
【００３７】[0037]
【発明の効果】本発明によれば、ＳＯＩ構造を有するＭ
ＯＳ型半導体記憶装置であって、高集積化と高速化とを
ともに同時に実現できるＭＯＳ型半導体記憶装置を提供
でき、また、そのようなＭＯＳ型半導体記憶装置の製造
方法を提供することができた。According to the present invention, M having an SOI structure
It was possible to provide an OS type semiconductor memory device that is capable of achieving both high integration and high speed at the same time, and a method of manufacturing such a MOS type semiconductor memory device. .
【図１】実施例１のＭＯＳ型半導体記憶装置の断面図で
ある。FIG. 1 is a cross-sectional view of a MOS semiconductor memory device according to a first embodiment.
【図２】実施例１の工程を順に断面図で示すものである
（１）。2A to 2C are sectional views showing steps of Example 1 in order (1).
【図３】実施例１の工程を順に断面図で示すものである
（２）。3A to 3C are sectional views showing the steps of Example 1 in order (2).
【図４】実施例１の工程を順に断面図で示すものである
（３）。4A to 4C are sectional views showing the steps of Example 1 in order (3).
【図５】実施例１の工程を順に断面図で示すものである
（４）。5A to 5C are sectional views showing steps of Example 1 in order (4).
【図６】実施例１の工程を順に断面図で示すものである
（５）。FIG. 6 is a sectional view showing the steps of Example 1 in order (5).
【図７】実施例１の工程を順に断面図で示すものである
（６）。FIG. 7 is a sectional view showing the steps of Example 1 in order (6).
【図８】実施例２の工程を順に断面図で示すものである
（１）。FIG. 8 is a sectional view showing the steps of Example 2 in order (1).
【図９】実施例２の工程を順に断面図で示すものである
（２）。9A to 9C are sectional views showing the steps of Example 2 in order (2).
【図１０】実施例２の工程を順に断面図で示すものであ
る（３）。FIG. 10 is a sectional view showing the steps of Example 2 in order (3).
【図１１】実施例２の工程を順に断面図で示すものであ
る（４）。FIG. 11 is a sectional view showing the steps of Example 2 in order (4).
【図１２】従来のＭＯＳ半導体記憶装置の断面図であ
る。FIG. 12 is a cross-sectional view of a conventional MOS semiconductor memory device.
１ 半導体基板（シリコン基板） ２ 埋め込み酸化膜 ２１ メモリセルの埋め込み絶縁膜 ２２ 周辺回路の埋め込み絶縁膜 ３ 半導体層（ＳＯＩ層） ４ はり合わせのためのバッファ層（ポリシリコン） ５ はり合わせの台となるシリコン基板 ６ レジスト ７ ゲート電極 ８ ＳＩＭＯＸ基板 ９ レジスト １０ （酸素）イオン注入層 １１ 埋め込み絶縁膜（酸化膜）層 １２ 半導体層（ＳＯＩ層） 1 Semiconductor Substrate (Silicon Substrate) 2 Buried Oxide Film 21 Buried Insulation Film of Memory Cell 22 Buried Insulation Film of Peripheral Circuit 3 Semiconductor Layer (SOI Layer) 4 Buffer Layer (Polysilicon) 5 for Laminating 5 Silicon substrate 6 resist 7 gate electrode 8 SIMOX substrate 9 resist 10 (oxygen) ion implantation layer 11 buried insulating film (oxide film) layer 12 semiconductor layer (SOI layer)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/08 ３３１ Ｅ 27/12 Ｅ 29/786 9056−4Ｍ Ｈ０１Ｌ 29/78 ３１１ Ｃ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H01L 27/08 331 E 27/12 E 29/786 9056-4M H01L 29/78 311 C
Claims (4)
置において、 メモリセルの埋め込み絶縁膜の膜厚を周辺回路の絶縁膜
よりも薄くすることを特徴とするＭＯＳ型半導体記憶装
置。1. A MOS type semiconductor memory device having an SOI structure, wherein a film thickness of a buried insulating film of a memory cell is thinner than that of an insulating film of a peripheral circuit.
モリセルを構成するＭＯＳ型半導体装置の実効ゲート長
よりも小さいものとすることを特徴とする請求項１に記
載のＭＯＳ型半導体記憶装置。2. The MOS type semiconductor memory according to claim 1, wherein the thickness of the buried insulating film of the memory cell is smaller than the effective gate length of the MOS type semiconductor device forming the memory cell. apparatus.
置の製造方法であって、 半導体基板上にＳＯＩ半導体層となる凸部を形成し、 更に素子分離領域となる埋め込み絶縁膜を形成し、 該絶縁膜の内メモリセルの埋め込み絶縁膜となる部分を
薄膜化し、 その後はり合わせの台となる基板をはり合わせてはり合
わせ研磨法によりＳＯＩ構造を形成することによって、 メモリセルの埋め込み絶縁膜の膜厚を周辺回路の絶縁膜
の膜厚よりも薄く形成することを特徴とするＭＯＳ型半
導体記憶装置の製造方法。3. A method of manufacturing a MOS type semiconductor memory device having an SOI structure, comprising forming a convex portion to be an SOI semiconductor layer on a semiconductor substrate and further forming a buried insulating film to be an element isolation region, The portion of the insulating film that becomes the embedded insulating film of the memory cell is thinned, and then the substrates that become the base for laminating are laminated together to form the SOI structure by the lapping and polishing method. A method of manufacturing a MOS type semiconductor memory device, characterized in that the thickness is formed thinner than that of an insulating film of a peripheral circuit.
置の製造方法であって、 半導体基板の内部にイオン注入により絶縁膜を形成し、 更に該絶縁膜の内周辺回路領域の埋め込み絶縁膜となる
部分に更にイオン注入を行って絶縁部を厚膜化すること
によって、 メモリセルの埋め込み絶縁膜の膜厚を周辺回路の絶縁膜
の膜厚よりも薄く形成することを特徴とするＭＯＳ型半
導体記憶装置の製造方法。4. A method for manufacturing a MOS type semiconductor memory device having an SOI structure, comprising forming an insulating film by ion implantation inside a semiconductor substrate, and further forming a buried insulating film in an inner peripheral circuit region of the insulating film. MOS type semiconductor memory characterized in that the film thickness of the buried insulating film of the memory cell is formed thinner than the film thickness of the insulating film of the peripheral circuit by further ion-implanting the part to thicken the insulating part. Device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05548594A JP3254889B2 (en) | 1994-03-25 | 1994-03-25 | MOS type semiconductor memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05548594A JP3254889B2 (en) | 1994-03-25 | 1994-03-25 | MOS type semiconductor memory device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07263575A true JPH07263575A (en) | 1995-10-13 |
| JP3254889B2 JP3254889B2 (en) | 2002-02-12 |
Family
ID=12999932
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05548594A Expired - Fee Related JP3254889B2 (en) | 1994-03-25 | 1994-03-25 | MOS type semiconductor memory device and method of manufacturing the same |
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005522034A (en) * | 2002-03-28 | 2005-07-21 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Semiconductor device formed on buried oxide film having a plurality of thicknesses and manufacturing method thereof |
| JP2007524981A (en) * | 2003-12-16 | 2007-08-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Silicon-on-insulator wafer contoured insulator layer and manufacturing process |
| US7638840B2 (en) | 2003-06-30 | 2009-12-29 | Kabushiki Kaisha Toshiba | Semiconductor storage device and semiconductor integrated circuit |
-
1994
- 1994-03-25 JP JP05548594A patent/JP3254889B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005522034A (en) * | 2002-03-28 | 2005-07-21 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Semiconductor device formed on buried oxide film having a plurality of thicknesses and manufacturing method thereof |
| US7638840B2 (en) | 2003-06-30 | 2009-12-29 | Kabushiki Kaisha Toshiba | Semiconductor storage device and semiconductor integrated circuit |
| JP2007524981A (en) * | 2003-12-16 | 2007-08-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Silicon-on-insulator wafer contoured insulator layer and manufacturing process |
| US7935613B2 (en) | 2003-12-16 | 2011-05-03 | International Business Machines Corporation | Three-dimensional silicon on oxide device isolation |
| JP4701085B2 (en) * | 2003-12-16 | 2011-06-15 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method for manufacturing a silicon-on-insulator wafer |
| US8405150B2 (en) | 2003-12-16 | 2013-03-26 | International Business Machines Corporation | Contoured insulator layer of silicon-on-insulator wafers and process of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3254889B2 (en) | 2002-02-12 |
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