JPH0722248B2 - Limiter circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a limiter circuit for limiting the output amplitude of a transistor.

[0002]

2. Description of the Related Art Conventionally, a microwave limiter circuit composed of active elements such as field effect transistors (hereinafter referred to as FETs), capacitors, inductors, etc., keeps an output signal at a constant level in response to fluctuations in the input signal level. It has a suppressing function and is an important component in radar communication systems and the like.

FIG. 4 shows the structure of a conventional FET limiter circuit used in microwave communication.

In FIG. 4, 11 is a source grounded F
ET and 12 are microwave signal input terminals, 13 is a signal output terminal, 14 is an input matching circuit, and 15 is an output matching circuit. The drain voltage of the FET 11 is the bias supply terminal 16
Is supplied via the drain resistor 17. The gate bias voltage is supplied from the bias supply terminal 18 via the gate resistor 19.

In the FET 11, as shown in the FET static characteristic diagram of FIG. 5, the bias point P is set so as to be in the vicinity of pinch-off and the drain-source voltage V _{DS in the} vicinity of the knee voltage. Here, when the microwave signal is applied to the signal input terminal 12, the bias point P moves cyclically on the AC load line A, and the drain current changes as shown in FIG. 6 as the input signal level increases. As shown, it changes in a form close to a squared half-wave rectified wave.

Therefore, the direct current component I of the drain current I
_DC2, if the change in the drain current is assumed to be square half-wave rectification wave, and _{I DC2 = I 0/4 ...} (1). I0 is the maximum value of the current amplitude shown in FIG.
At this time, since the bias point P of the FET 11 is in the vicinity of pinch off, I _DC2 > I _DC0 (2) _IDCO is a bias current when there is no signal.

On the other hand, since the drain bias voltage of the FET 11 is supplied through the drain resistor 17, the drain-source voltage V _DS becomes smaller by the increase of the direct current component of the drain current. Therefore, the saturated output signal level of the FET 11 is suppressed and the input signal level is limited. That is, the limiting characteristic of the FET limiter circuit depends on the increase amount of the direct current component of the drain current.

However, in the conventional FET limiter circuit having the above structure, the microwave monolithic circuit (MMI) is used.
In the case of C), the bias point P of the FET is pinched.
Since it is set near OFF, the element sensitivity to the FET parameter of the circuit is high, and the matching state of the FET 11 is M.
It varies from lot to lot of MIC. This variation causes variation in the increase of the direct current component of the drain current, and the limiting input signal level also
For example, as shown in FIG. 7, variations are generated in lots 1, 2, and 3. Therefore, it is necessary to inspect whether or not the variation is within the allowable range, which causes a reduction in yield in MMIC manufacturing.

Further, in a FET limiter circuit composed of a hybrid IC (HIC), differences in FET lots and variations in assembly cause variations in the matching state of the FETs, so that it is necessary to adjust the limiting characteristics. This has been the cause of the yield reduction in HIC manufacturing.

The above is true not only when using a FET but also when using a normal transistor.

[0011]

As described above, in the conventional limiter circuit, since the bias point of the transistor element is set near the pinch-off, the element sensitivity to the circuit parameter is high, and the MMIC has lot-to-lot correspondence. To
In the HIC, the matching state of the input and output of the transistor element is different due to the influence of variations in the assembly, which causes the variations in the limiting characteristics.

The present invention has been made in order to solve the above-mentioned problems, and the bias point of a transistor element is set near pinch-off so that even if the matching state of the input and output of the transistor element varies, the limit An object of the present invention is to provide a limiter circuit capable of suppressing variations in the charging characteristics.

[0013]

In order to achieve the above object, the present invention controls a transistor by grounding a first controlled electrode of a transistor and applying a bias voltage to the second controlled electrode via a resistor. A limiter circuit that limits a bias current with an increase in an input signal supplied to an electrode to limit the output amplitude of a second controlled electrode, and is connected to the second controlled electrode to control the electrode. It is configured by including a filter circuit that makes a short-circuit state at an integer multiple frequency excluding the fundamental frequency with respect to the electrode input frequency.

[0014]

In the limiter circuit having the above structure, the second controlled electrode is short-circuited at a frequency that is an integral multiple of the control electrode input frequency, excluding the fundamental frequency, and the increase amount of the DC component of the second controlled electrode is increased. Even if the bias point of the transistor element is set near the pinch-off and the input / output matching state of the transistor element varies,
Suppress variations in limiting characteristics.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. However, in FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals, and different parts will be mainly described here.

FIG. 1 shows the structure, which is composed of an MMIC. A filter circuit 18 is connected between the drain electrode of the FET 11 and the signal output terminal 13. The filter circuit 20 has a function of making the drain electrode short-circuit at a frequency that is an integral multiple of the source input signal frequency of the FET 11 excluding the fundamental frequency f. In reality, if the filter is formed in consideration of the second and third harmonics 2f and 3f, it is sufficient to realize the short-circuit state with respect to the harmonics. Therefore, in the embodiment shown in FIG. This is realized by using the open end stubs a and b so that the drain electrode is short-circuited with respect to the three harmonics 2f and 3f. a is a stub for shorting the second harmonic, and b is a stub for shorting the third harmonic.

Incidentally, FIG. 1 shows a case where the input matching circuit 14 and the output matching circuit 15 are constructed by using stubs c, d, e and f, respectively.

The operation of the above structure will be described below with reference to FIGS.

When a microwave signal is supplied to the input signal input terminal 12, the bias point P shown in FIG. 5 periodically moves on the AC load line A. As the input signal level increases, the drain current of the FET 11 changes in a form close to a rectangular wave as shown in FIG. 2 because a short-circuit current of a harmonic component of the input signal frequency f flows through the filter circuit 20.

Therefore, assuming that the change in the drain current has a rectangular wave shape, the direct current component I of the drain current I
_DC1 is I _DC1 = I ₀ / π (3), and the relationship of I _DC1 > I _DC2 (4) is obtained.

Therefore, in the FET limiter circuit having the above structure, even if the matching state of the FET 11 is different for each lot of MMICs, the DC component of the drain current is large, so that, for example, as shown in FIG. It is possible to suppress the variation of the input signal level which is subject to the limiting for each of 1, 2, and 3. As a result, the yield in MMIC manufacturing can be improved by about 10% or more.

In the above embodiment, the change in drain current is assumed to have a rectangular wave shape, but this is only an odd-order harmonic component. Actually, a direct-current component due to an even-order harmonic component is present. Therefore, the increase of the direct current component of the drain current becomes large. This makes it possible to further suppress variations in limiting characteristics.

Further, although the case where the FET is used has been described above, the present invention can be applied to the case where a normal transistor is used and the same result can be obtained. It goes without saying that the present invention is also applicable to the case where the HIC is used.

[0024]

As described above, according to the present invention, the bias point of the transistor element is set in the vicinity of pinch-off, and even if the matching state of the input / output of the transistor element varies, the variation of the limiting characteristic is caused. It is possible to provide a limiter circuit capable of suppressing the above.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration when an FET is used as an example of a limiter circuit according to the present invention.

FIG. 2 is a waveform diagram showing a drain current waveform of the same example.

FIG. 3 is a characteristic diagram showing a limiting characteristic for each lot when the FET limiter circuit of the embodiment is composed of MMIC.

FIG. 4 is a circuit diagram showing a configuration of a conventional FET limiter circuit.

FIG. 5 is a characteristic diagram showing static characteristics of an FET.

FIG. 6 is a waveform diagram showing the drain current waveform of FIG.

7 is a characteristic diagram showing limiting characteristics for each lot when the FET limiter circuit of FIG. 4 is configured by MMIC.

[Explanation of symbols]

11 ... FET, 12 ... Microwave signal input terminal, 13 ...
Signal output terminal, 14 ... Input matching circuit, 15 ... Output matching circuit, 16 ... Drain bias supply terminal, 17 ... Drain resistance, 18 ... Gate bias supply terminal, 19 ... Gate resistance, 20 ... Filter circuit, a, b ... Open Edge stub.

Claims (5)

[Claims] 1. A first controlled electrode of a transistor is grounded, a bias voltage is applied to a second controlled electrode via a resistor, and a bias current is increased as an input signal supplied to the control electrode increases. In a limiter circuit that limits and limits the output amplitude of the second controlled electrode, the limiter circuit is connected to the second controlled electrode, and the electrode is at an integral multiple frequency excluding the fundamental frequency with respect to the control electrode input frequency. A limiter circuit having a filter circuit for making a short circuit. 2. The limiter circuit according to claim 1, wherein the limiter circuit is a microwave monolithic circuit. 3. The limiter circuit according to claim 2, wherein the filter circuit is formed by an open end stub. 4. The limiter circuit according to claim 1, wherein the limiter circuit is a microwave hybrid circuit. 5. The limiter circuit according to claim 4, wherein the filter circuit is formed by an open end stub.