JPH07203386A - Television signal processor - Google Patents

Abstract

PURPOSE:To improve the picture quality of successive scanning output signals by executing successive scanning conversion in a band to which a compensation signal is not transmitted by means of a letter box type decoder based upon signals corresponding to respective frames as units and executing successive scanning conversion by using twice the information quantity of a signal obtained by intra-field interpolation. CONSTITUTION:A main screen part signal in a signal arriving by a letter box system and jump scanning is synthesized with a frame by a frame synthesizing circuit 302 and separated into a high band component and a low band component by a V-HPF 303 and a subtractor 304. In the case of a still image, a switch 306 is turned on, the high band component is added by an adder 305 and conversion into successive scanning is executed by a double speed conversion and a selector, and in the case of a dynamic image, a vertical high band component is shifted to a low band by a V shifting circuit 307 and conversion processing into successive scanning is executed by the shifted component and the low band component from an adder 304.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal processing device.

[0002]

2. Description of the Related Art When a horizontally long screen having an aspect ratio of 16: 9 is photographed by a camera and displayed on a display having an aspect ratio of 4: 3, the circularity cannot be maintained and a circular object becomes a vertically long ellipse. That is, the compatibility between the landscape broadcast and the current receiver cannot be obtained as it is. In order to avoid this problem, a horizontally long image is compressed by 3/4 in the vertical direction on the sending side, and there is a non-image part at the top and bottom of the display (there are black bars at the top and bottom of the screen. The image is displayed in), and the letterbox format is proposed.

In the letterbox format, a signal having an aspect ratio of 16: 9 and N scanning lines (N is an integer) is subjected to compression processing on M lines (M is an integer), and an upper and lower non-image area is provided at the center of the screen. , The compressed additional signals are multiplexed and transmitted to (N−M) lines for reproducing a higher definition image on the receiving side.

FIG. 9 shows a scan line 480 in the letterbox format.
FIG. 10 is a block diagram for encoding a signal having a frame frequency of 1/60 [sec], and FIG. 10 shows a decoding process of an input signal to sequentially scan 480 scanning lines and a frame frequency of 1/60 [sec]. It is a block diagram for obtaining a signal.

In FIG. 9, input terminals 101, 102, 1
The R, G, and B signals respectively input to 03 are matrix-converted by the matrix circuit 104, converted into Y, I, and Q signals and output. The control signal generator 129 generates a timing signal required by the system based on H (horizontal synchronizing signal) and V (vertical synchronizing signal).

The I signal is a vertical low pass filter (V-LP).
F) The band is limited by 117, and the interlaced scanning converter 119
Then, the sequential scanning signal having the frame frequency of 1/60 [sec] is converted into the interlaced scanning signal having the frame frequency of 1/30 [sec]. I signal converted to interlaced scanning is 4
The 3-converter 121 vertically compresses the signal 3/4 times, and converts the signal of 480 [line / frame] effective scanning lines into a signal of 360 [line / frame] effective scanning lines. 4 →
The output of the 3 converter 121 is a horizontal low pass filter (HL).
It is input to the PF) 123 and band-limited in the horizontal direction, and then input to the multiplier 125. In the multiplier 125, the carrier (cos2πf) output from the control signal generator 129 is output.
Sct) is modulated with the I signal.

The Q signal is a V-LPF 118, an interlaced scanning converter 120, a 4 → 3 converter 122, and an H-LPF 124.
Then, the same processing as that of the I signal is performed to form an interlaced scanning signal having an effective scanning line number of 360 [lines / frame] and a frame frequency of 1/30 [sec], and is input to the multiplier 126. The multiplier 126 modulates the carrier wave (sin2πfsct) output from the control signal generator 129 with the Q signal.

The modulated I and Q signals are added to the adder 12
7 is added and is input to the adder 115 as a C signal.

On the other hand, the Y signal output from the matrix circuit 104 is the motion detection circuit 141, V-LPF 105, V-
It is input to the HPF 131. Y in the motion detection circuit 141
The motion of the image is detected from the signal and a motion detection signal is output. This motion detection signal is compressed 3/4 times in the vertical direction by the 4 → 3 converter 142, is converted from a sequential scanning signal to an interlaced scanning signal by the interlaced converter 143, and the effective scanning line number is 360 [lines / frame], Frame frequency 1/30 [s
ec].

The V-HPF 131 extracts the vertical high frequency component (VH signal) of the Y signal. The extracted VH signal is vertically reduced by the vertical shift circuit 132, vertically compressed 3/4 times by the 4 → 3 converter 133, and the effective scanning line number is 360 [lines / frame] and the frame frequency is 1 /. 60
It is converted into a progressive scanning signal of [sec]. The 4 → 3 converted signal is inverted by the frame inverting circuit 134 every other frame. The frame-inverted signal is converted by the interlace converter 135 from a sequential scanning signal into an interlaced scanning signal, and becomes a signal having an effective scanning line number of 360 [lines / frame] and a frame frequency of 1/30 [sec]. The signal converted into the interlaced scan is band-limited in the horizontal direction by the H-LPF 136.

The V-LPF 105 band-limits the Y signal in the vertical direction. The band-limited signal is a 4 → 3 converter 10
The number of effective scanning lines is 48 when compressed vertically by 3/4
0 [book / frame], frame frequency 1/60 [se
The progressive scanning signal of c] is converted into a progressive scanning signal having an effective scanning line number of 360 [lines / frame] and a frame frequency of 1/60 [sec]. The output of the 4 → 3 converter 106 is V−
It is input to the LPF 107 and the V-HPF 108.

In the V-LPF 107, the 4 → 3 converter 106
Output is subjected to band limitation in the vertical direction, and the band-limited Y signal is converted from a sequential scanning signal into an interlaced scanning signal by the interlaced scanning converter 109. The output of the interlaced scan converter 109 is input to the adder 115.

In the V-HPF 108, the 4 → 3 converter 106
The vertical high frequency component of the output of is extracted, and the extracted Y signal is converted by the interlaced scan converter 110 from the sequential scanning signal to the interlaced scanning signal. The output of the interlaced scanning converter 110 is band-limited in the horizontal direction by the H-LPF 111 and input to the adder 137.

The VH signal band-limited by the H-LPF 136 is input to the switch 144. The switch 144 conducts only when it is determined to be a still image based on the motion detection signal detected by the motion detection circuit 141. The VH signal that has passed through the switch 144 is added to the Y signal in the vertical high range by the adder 137, and the addition result is subjected to horizontal time compression processing by the time compression / reordering circuit 112, and the time compressed signal is 1
20 [books / frames] Rearrangement is performed so as to fit in the upper and lower non-image portions.

The adder 115 adds the Y signal converted into the interlaced scanning and the modulated color signal C, and 4:
It becomes the main screen part of 3 screens. The output of the adder 115 and the output of the time compression / sorting circuit 112 are switched and output by the switch 116 according to the timing signal output from the control signal generation unit 129. The output of the switch 116 becomes the encode output signal.

The operation of the conventional decoder will be described with reference to FIG.

The input terminal 201 has an analog digital (A /
D) The converted encoded signal is input. The input signal is input to the Y / C separation circuit 202 and the multiple signal processing circuit 221. The multiple signal processing circuit 221 demodulates the signals multiplexed in the upper and lower non-image parts, rearranges them to make 120 signals into 360 signals, and expands the time-compressed signals in time. Multiplex signal processing circuit 221
Is separated into a VH signal and an LD signal by an LD / VH separation circuit 238.

The VH signal output from the LD / VH separation circuit 238 is converted from the interlaced scanning signal to the progressive scanning signal by the progressive scanning converter 239, and the 360 lines / 2: 1 signal to the 360 lines / 1: 1 signal. become. The signal converted into the progressive scan is input to the 3 → 4 converter 236, and the signal is converted into 4 in the vertical direction.
It is expanded by ⅓ and is converted from a signal having 360 effective scanning lines [lines / frame] to a signal having 480 effective scanning lines [lines / frame]. The line-inverted circuit 237 line-inverts the scan-line converted signal, and frequency-shifts the signal from the vertical low band to the vertical high band. The line-inverted VH signal is input to the adder 214.

The LD signal output from the LD / VH separation circuit 238 is level 0 every other line in the 0 insertion circuit 233.
Signal is inserted and the interlaced scanning signal of 180 [lines / field] is converted into a progressive scanning signal of 360 [lines / frame]. The 0-inserted signal is input to the V-LPF 234, the 0-level signal is interpolated, and the interpolated signal is input to the adder 235.

The signal input to the Y / C separation circuit 202 is separated into a luminance signal Y and a color signal C. The color signal C is sent to the color demodulation circuit 241, and the luminance signal Y is the motion detection circuit 203, HL.
It is input to the PF 204 and the subtractor 207. The color demodulation circuit 241 performs color demodulation processing and outputs an I signal and a Q signal. The I and Q signals are band-limited in the horizontal direction by the H-LPF 242, vertically expanded by 4/3 times by the 3 → 4 converter 243, and 480 [lines / line] from the interlaced scanning signal of 360 [lines / frame]. [Frame] interlaced scanning signal. The scanning line converted I and Q signals are converted at double speed by the double speed conversion circuit 244 and converted from the interlaced scanning signal of 480 [lines / frame] to the sequential scanning signal of 480 [lines / frame]. The double-speed converted I and Q signals are input to the matrix circuit 245.

The motion detection circuit 203 detects the motion of the image from the input Y signal and outputs a motion detection signal.

The Y signal input to the H-LPF 204 is band-limited in the horizontal direction, and its output is input to the 0 insertion circuit 205 and the subtractor 207. The subtractor 207 subtracts the Y signal whose band is limited by the H-LPF 204 from the original Y signal to extract a high frequency component in the horizontal direction. The extracted horizontal high frequency Y signal is input to the progressive scan converter 208.

The progressive scan converter 20 will now be described with reference to FIG.
The operation of No. 8 will be described.

The signal input to the progressive scan conversion unit 208 is added to the input terminal 301 and input to the buffer memory 501, the field memory 502, and the interpolation filter 503. The interpolation filter 503 creates an interpolation component from the upper and lower scanning lines. This signal becomes an interpolation component for a moving image. The field memory 502 outputs a signal obtained by delaying the input signal by one field. This signal becomes an interpolation component at the time of still image. Field memory 502 and interpolation filter 5
The output of 03 is input to the selector 504, and selectively switched and output according to the motion detection signal from the motion detection circuit 203. The output of the selector 504 is the buffer memory 50.
The signal is input to the double speed conversion circuit 505 together with the signal whose delay has been adjusted in 1 and is converted to a double speed here, converted into a sequential scanning signal of the effective scanning line 360 [lines / frame], and output. The output of the double speed conversion circuit 505 is output via the output end 315 and input to the adder 212 (FIG. 10).

On the other hand, in the signal input to the 0 insertion circuit 205, the signal of level 0 is inserted every other line and the number of effective scanning lines is 360 [lines / frame] from the interlaced scanning signal of the effective scanning line number 180 [lines / field]. ] It is converted into a progressive scanning signal. The inserted signal is 0 by V-LPF206.
The level signal is interpolated and input to the adder 235. In the adder 235, the LD signal is added and the components up to 360 LPH are reproduced in horizontal reduction.

The output of the adder 235 is added by the adder 212 with the sequentially converted horizontal high-frequency components, and the 3 → 4 converter 213 vertically expands by 4/3 times to obtain 360 [lines / line]. The signal of [frame] is converted to the signal of 480 [lines / frame]. The scanning line converted signal is added to the VH signal by the adder 214 to reproduce the components up to 480 LPH. The output of the adder 214 is input to the matrix circuit 245.

In the matrix circuit 245, the input Y,
The I and Q signals are matrix-converted into R, G and B signals and output.

11 and 12 are block diagrams of another conventional encoder and decoder. In the letterbox type television signal, the multiple signals are superimposed on the upper and lower non-picture parts, but this multiple signal causes visual interference in the current receiver. Therefore, in order to reduce the visual interference, the encoder performs a process of subtracting the vertical high frequency component of the Y signal one field before from the signal component that becomes the multiplex signal. The decoder performs signal processing that is the reverse of that performed by the encoder. The operation of the encoder in the second conventional example will be described below with reference to FIG.

In FIG. 11, input terminals 101, 102,
The R, G and B signals respectively inputted to 103 are matrix-converted by the matrix circuit 104 and converted into Y, I and Q signals and outputted. The control signal generator 129 generates a timing signal required by the system based on the H and V signals.

The I signal is band-limited by the V-LPF 117, and the interlaced scanning converter 119 makes the frame frequency 1/6.
Frame frequency 1/3 from 0 [sec] progressive scan signal
It is converted into an interlaced scanning signal of 0 [sec]. The interlaced scan-converted I signal is vertically compressed 3/4 times by the 4 → 3 converter 121, and the number of effective scanning lines is 480 [line / line
The signal of [frame] is converted into a signal of 360 [line / frame] of effective scanning lines. The output of the 4 → 3 converter 121 is input to the H-LPF 123, band-limited in the horizontal direction, and input to the multiplier 125. In the multiplier 125, the carrier (cos2πf) output from the control signal generator 129 is output.
Sct) is modulated with the I signal.

The Q signal is V-LPF 118, interlaced scan converter 120, 4 → 3 converter 122, H-LPF 124.
Then, the same processing as that of the I signal is performed to form an interlaced scanning signal having an effective scanning line number of 360 [lines / frame] and a frame frequency of 1/30 [sec], and is input to the multiplier 126. The multiplier 126 modulates the carrier wave (sin2πfsct) output from the control signal generator 129 with the Q signal.

The modulated I and Q signals are added by an adder 127.
And added as a C signal to the adder 115.

On the other hand, the Y signal output from the matrix circuit 104 is the motion detection circuit 141, V-LPF 105, V-
It is input to the HPF 131. Y in the motion detection circuit 141
The motion of the image is detected from the signal and a motion detection signal is output. This motion detection signal is compressed 3/4 times in the vertical direction by the 4 → 3 converter 142, is converted from a sequential scanning signal to an interlaced scanning signal by the interlaced scanning converter 143, and the number of effective scanning lines is 360 [lines / frame]. , Frame frequency 1/30
It is converted into a signal of [sec].

The V-HPF 131 extracts the vertical high frequency component (VH signal) of the Y signal. The extracted VH signal is vertically reduced by the vertical shift circuit 132, vertically compressed 3/4 times by the 4 → 3 converter 133, and the effective scanning line number is 360 [lines / frame] and the frame frequency is 1 /. 60
It is converted into a progressive scanning signal of [sec]. The 4 → 3 converted signal is inverted by the frame inverting circuit 134 every other frame. The frame-inverted signal is converted from a sequential scanning signal into an interlaced scanning signal by the interlaced scanning converter 135, and becomes a signal having an effective scanning line number of 360 [lines / frame] and a frame frequency of 1/30 [sec]. The interlaced converted signal is band-limited in the horizontal direction by the H-LPF 136.

The V-LPF 105 band-limits the Y signal in the vertical direction. The band-limited signal is a 4 → 3 converter 10
The number of effective scanning lines is 48 when compressed vertically by 3/4
0 [book / frame], frame frequency 1/60 [se
The progressive scanning signal of c] is converted into a progressive scanning signal having an effective scanning line number of 360 [lines / frame] and a frame frequency of 1/60 [sec]. The output of the 4 → 3 converter 106 is V−
It is input to the LPF 107 and the V-HPF 108.

In the V-LPF 107, the 4 → 3 converter 106
Output is subjected to band limitation in the vertical direction, and the band limited Y signal is converted by the interlaced converter 109 from a sequential scanning signal to an interlaced scanning signal. The output of the interlace converter 109 is input to the adder 115 and the V-HPF 141.

In the V-HPF 141, the vertical high frequency component of the Y signal converted into the interlaced scanning signal by the interlaced scanning converter 109 is extracted. The output of V-HPF141 is H-LP
The band is horizontally limited in F142, delayed by one field in the field delay circuit 143, and input to the subtractor 145.

In the V-HPF 108, the 4 → 3 converter 106
The vertical high frequency component of the output of is extracted, and the extracted Y signal is converted by the interlaced converter 110 from a sequential scanning signal to an interlaced scanning signal. The output of the interlaced scan converter 110 is H
-The band is horizontally limited by the LPF 111, and the adder 13
Input to 7.

The VH signal band-limited by the H-LPF 136 is input to the switch 144. The switch 144 conducts only when it is determined that the image is a still image based on the motion detection signal output from the motion detection circuit. The VH signal passed through the switch 144 is added to the output signal of the H-LPF 111 by the adder 137. The output of the adder 137 is the field delay circuit 14 for reducing the visual interference in the above-mentioned current receiver.
The output of No. 3 is subtracted, and the subtraction result is subjected to horizontal time compression processing by the time compression / rearrangement circuit 112, and the time-compressed signals are arranged so as to fit in the upper and lower non-image parts of 120 [lines / frame]. Replacement is done.

The adder 115 adds the interlaced-converted Y signal and the modulated color signal C to form a 4: 3 screen main screen section. The output of the adder 115 and the output of the time compression / sorting circuit 112 are switched and output by the switch 116 according to the timing signal output from the control signal generation unit 129. The output of the switch 116 becomes the encode output signal.

Next, the operation of the decoder in the second conventional example will be described with reference to FIG. A at the input end 201
The / D-converted encoded signal is input. The input signal is input to the Y / C separation circuit 202 and the multiple signal processing circuit 221. The multiple signal processing circuit 221 demodulates the signals multiplexed in the upper and lower non-image parts, rearranges them to 1
The number of signals that had been 20 has been changed to 360, and the time-compressed signal has been expanded in time. The output of the multiple signal processing circuit 221 is input to the adder 222.

The signal input to the Y / C separation circuit 202 is separated into a luminance signal Y and a color signal C. The color signal C is sent to the color demodulation circuit 241, and the luminance signal Y is sent to the motion detection circuit 203, HL.
PF204, subtractor 207, field delay circuit 231
Entered in. The color demodulation circuit 241 performs color demodulation processing and outputs an I signal and a Q signal. I and Q signals are HL
Each band is horizontally limited by the PF 242, and 3 → 4.
The converter 243 vertically expands by 4/3 times to 360
480 [book / frame] from the interlaced scanning signal of [book / frame]
[Frame] interlaced scanning signal. The scanning line converted I and Q signals are converted at the double speed by the double speed conversion circuit 244 to 48 from the interlaced scanning signal of 480 [lines / frame].
It is converted into a progressive scanning signal of 0 [lines / frame]. The double-speed converted I and Q signals are input to the matrix circuit 245.

The motion detection circuit 203 detects motion from the input Y signal and outputs a motion detection signal.

The signal input to the field delay circuit 231 is delayed by one field, band-limited in the horizontal direction by the H-LPF 232, and vertical high frequency components are extracted by the V-HPF 223. The output of the V-HPF 223 is input to the adder 222. The adder 222 adds the output of the multiplex signal processing circuit 221 and the output of the V-HPF 223 to obtain L
It is input to the D / VH separation circuit 238.

The LD / VH separation circuit 238 separates the VH signal and the LD signal. LD / VH separation circuit 238
The VH signal output from the interlaced scanning converter 239 converts the interlaced scanning signal into a progressive scanning signal, which is 360 lines /
A signal of 2: 1 is changed to a signal of 360 lines / 1: 1. The signal converted into the progressive scan is input to the 3 → 4 converter 236, expanded in the vertical direction by 4/3 times, and the number of effective scan lines is 36.
A signal of 0 [lines / frame] is converted to a signal of 480 [lines / frame] of effective scanning lines. The scan line converted signal is line-inverted by the line inversion circuit 237 and frequency-shifted from the vertical reduction to the vertical high band. The line-inverted VH signal is input to the adder 214.

The LD signal output from the LD / VH separation circuit 238 is level 0 every other line in the 0 insertion circuit 233.
Signal is inserted and the interlaced scanning signal of 180 [lines / field] is converted into a progressive scanning signal of 360 [lines / frame]. The 0-inserted signal is input to the V-HPF 234, the 0-level signal is interpolated, and the interpolated signal is input to the adder 235.

The Y signal input to the H-LPF 204 is band-limited in the horizontal direction, and its output is input to the 0 insertion circuit 205 and the subtractor 207. The subtractor 207 subtracts the Y signal band-limited by the H-LPF 204 from the original Y signal to extract a horizontal high frequency component. The extracted horizontal high frequency Y signal is input to the progressive scan converter 208 (the operation of the progressive scan converter is the same as the operation of the decoder described above, and therefore, will be omitted here). The output of the progressive scan converter 208 is input to the adder 212.

The signal input to the 0 insertion circuit 205 has a level 0 signal inserted every other line and the number of effective scanning lines is 18
The interlaced scanning signal of 0 [lines / field] is converted into a progressive scanning signal of 360 [lines / frame] of effective scanning lines. The 0-inserted signal is input to the adder 235 by interpolating the signal of 0 level in the V-LPF 206. The LD signal is added by the adder 235, and components up to 360 LPH are reproduced in horizontal reduction.

The output of the adder 235 is added to the horizontal high frequency components sequentially converted by the adder 212, and the 3 → 4 converter 2 is added.
It is extended to 4/3 times in the vertical direction at 13, and 360 [books /
The signal of [frame] is converted to the signal of 480 [lines / frame]. The scan line converted signal is added to V by the adder 214.
The components up to 480 LPH are reproduced by adding the H signal. The output of the adder 214 is input to the matrix circuit 245.

In the matrix circuit 245, the input Y,
The I and Q signals are matrix-converted into R, G and B signals and output.

As described above, the encoder multiplexes and transmits the additional signals in the non-image parts at the top and bottom of the screen, and the decoder reproduces a high-definition image by using the multiplexed additional signals. Since the additional signal is band-limited to the horizontal low band due to the limitation of the band transmitted at this time, since the horizontal high band signal component is subjected to the progressive scan conversion by the intra-field interpolation, the image quality cannot be improved. .

[0052]

As described above, a broadcast in which an encoder multiplexes and transmits an additional signal to the non-picture part at the top and bottom of the screen, and a decoder reproduces a high-definition image using the multiplexed additional signal. In the system, it is possible to reproduce a high-definition image by using an additional signal for the horizontal low frequency component. However, since the horizontal high-frequency component is progressive scanning conversion by intra-field interpolation, the resolution in the vertical direction cannot be improved. Further, there is a problem that the image quality is deteriorated because the aliasing component is generated by the intra-field interpolation. Furthermore, when an interlaced scanning signal such as a signal of the current NTSC system is input, since inter-field interpolation is applied to a moving image regardless of the horizontal band, it is a still image in which progressive scanning conversion is performed by inter-field interpolation. However, there is a problem in that the image quality difference is large and gives a feeling of strangeness.

Therefore, the present invention is a television which can obtain a higher definition image than the image quality obtained by the conventional method by changing to a method of progressive scanning conversion using a signal in units of frames regardless of whether it is a still image or a moving image. It is an object of the present invention to provide a John reception processing device. In addition, by changing the characteristics of the hardware such as the filter according to the identification signal, the second generation ED can be used without adding new hardware.
An object of the present invention is to provide a television reception processing device having a hardware configuration capable of processing signals other than TV.

[0054]

SUMMARY OF THE INVENTION According to the present invention, a signal input in a decoder is used as a frame-based signal, and a vertical high-frequency component of the signal is subjected to motion adaptation, and the vertical high-frequency component or the time-axis direction It is treated as a high frequency component, and the interlaced scanning signal is converted into a progressive scanning signal. In addition, by sharing the existing memory, it is possible to provide a higher-definition image than before by adding a minimum amount of hardware. Further, the hardware configuration is such that a change in hardware characteristics can be obtained by the identification signal and signals other than the second-generation EDTV can be processed without adding new hardware.

[0055]

By the above means, the input interlaced scanning signal is treated as a signal in units of frames, so that it is possible to obtain a higher-definition progressive scanning image than before.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) Since the present invention relates to the receiving apparatus, the encoder performs the same operation as the conventional example.

FIG. 1 is an overall block diagram of a decoder in an embodiment according to the present invention. FIG. 2A is a block diagram of the progressive scan conversion unit 501 of the system shown in FIG. FIG. 2B shows a scanning line structure when the interlaced scanning signals are frame-combined.

In FIG. 1, portions other than the progressive scan conversion unit 501 perform the same operation as that of the first conventional example described above, and therefore the operation will not be described here. Here, the operation of the progressive scan conversion unit 501 of FIG. 1 will be described with reference to FIG.

In FIG. 2A, the interlaced scanning signal input to the input terminal 301 is frame-synthesized by the frame synthesizing circuit 302 and has the same frame frequency as the input signal (frame frequency = 1/30 [sec]). It becomes a sequential scanning signal. Figure 2 shows the scanning line structure when frames are combined.
It is shown in (B). The signal of the nth field and (n +
1) When the field signals are combined, the scanning lines of the fields are alternately present as shown in FIG. 2B. The frame-combined signal is input to the vertical high-pass filter (V-HPF) 303 and the subtractor 304. The V-HPF 303 extracts the vertical high frequency component of the input signal. The output of the V-HPF 303 is the subtractor 304,
Switch 306 and vertical shift (V shift) circuit 30
Input to 7.

The subtractor 304 subtracts the output of the V-HPF 303 from the frame-combined signal to extract a vertical low frequency component. This signal is input to the adder 305.

In the switch 306, based on the motion detection signal output from the motion detection circuit 203 shown in FIG.
It conducts only when the motion detection signal indicates a still image. The signal passing through the switch 306 is added by the adder 305 to the signal in the vertical low frequency range. The output of the adder 305 is input to the adder 309 and the subtractor 310.

In the V shift circuit 307, the input vertical high band signal is shifted to the vertical low band and supplied to the switch 308. The switch 308 is controlled based on the motion detection signal output from the motion detection circuit 203, and is turned on only when the motion detection signal indicates a moving image. Switch 30
The output of 8 is input to the adder 309 and the subtractor 310.

The adder 309 outputs a signal obtained by adding the output of the adder 305 and the output of the switch 308, and the subtractor 310 outputs a signal obtained by subtracting the signal of the subtractor 310 from the output of the adder 305.

The output of the adder 309 and the output of the subtractor 310 are input to the double speed converters 311 and 312, respectively, and from the progressive scan signal of the frame frequency 1/30 [sec] to the progressive scan of the frame frequency 1/60 [sec]. Converted to a signal. The output of the double speed converter 311 is the selector 3
14, the output of the double speed converter 312 is the delay adjustment circuit 313.
1/60 [sec] is delayed by the selector 314
Entered in.

The selector 314 outputs the input signal to 1 /
The signal is switched and output every 60 [sec], and this signal becomes the output of the progressive scan conversion unit 501 via the output terminal 315.

(Second Embodiment) The present invention is not limited to the above-mentioned first embodiment. In the first embodiment, an example has been described in which the input interlaced scanning signals are frame-combined and sequentially scanned and converted as a frame unit signal. FIG. 3 shows a second embodiment as a method of handling the interlaced scanning signal as a frame unit signal and converting it into a sequential scanning.

Similar to FIG. 2, FIG. 3 shows a block diagram of the progressive scan conversion unit 501 of the system shown in FIG. The second embodiment will be described below with reference to the drawings.

FIG. 2A has two signal processing paths in order to reduce the amount of memory used in the frame synthesizing circuit shown in the first embodiment, and is similar to the previous embodiment. It is a circuit block diagram for obtaining the effect of, and shows the progressive scan conversion part. 3 (B) and FIG. 3 (C) are similar to FIG.
It is a figure for explaining the operation of the V-HPF surrounded by the broken line in (A), and the white circles in the figure show the scanning lines, respectively. FIG. 4 is a supplementary diagram for easier understanding that the embodiment shown in FIG. 3 can obtain the same result as the embodiment shown in FIG.

If an interlaced scanning signal of (n + 1) fields is input to the input terminal 301, the signal delayed by one field by the field delay circuit 401 and output is an interlaced scanning signal of n fields.
The n-field interlaced scan signal and the (n + 1) -field interlaced scan signal are input to the portion constituting the V-HPF 400 surrounded by the broken line in FIG. The operation of this portion will be described with reference to FIGS. The V-HPF will be described taking a 3-tap filter as an example for the sake of simplicity.

When the frame-combined signal is passed through a 3-tap filter as shown in the example, as shown in FIG. 3C, the combinations of scanning lines with coefficient taps are Δ2, Δ3, Proceed in the order of combinations such as…. In order to perform the same filter processing without performing frame synthesis, it is possible to have two systems of filter processing circuits. As shown in FIG.
A circuit for processing a combination of 1, Δ3, ... And Δ2, Δ
A circuit for processing the combination of 4, ...

Now, returning to FIG. 3A, the operation of the vertical filter will be described. The n-field signal output from the field delay circuit 401 is input to the line memory 402 and the coefficient multiplier 406 for obtaining 1H delay. The scanning line b in FIG. 3B is input to the coefficient unit 406, and the line memory 40
From 2, the signal of the scanning line a 1H before the scanning line b is input to the coefficient unit 405. The coefficient unit 404 has an input end 301
The signal of the scanning line d obtained by delaying the signal of the (n + 1) field added by 1H by the line memory 403 is input. The signals input to the coefficient multipliers 404, 405, and 406 are respectively multiplied by the coefficients, added by the adder 407, and output as a filtered signal. These are combinations of Δ1 in FIG. 3B (scan line a,
b, d) is the filtered output.

Similarly, the n-field signal output from the field delay circuit 401 is input to the coefficient multiplier 408. This signal corresponds to the scanning line b in FIG. The (n + 1) field signal input to the input terminal 301 is input to the coefficient unit 410 and the line memory 403. The coefficient line 410 receives the signal of the scanning line e in FIG. 3B, and the line memory 403 inputs the signal of the scanning line d 1H before the scanning line e to the coefficient unit 409. The signals input to the coefficient multipliers 408, 409, and 410 are multiplied by the coefficients, added by the adder 411, and output as a filtered signal. These are shown in Figure 2.
Combination of Δ2 in (b) (scanning lines b, d, e)
Is the filtered output.

The output of the adder 407 is input to the subtractor 412 and the switches 414 and 415. The subtractor 412 subtracts the vertical high-frequency component from the original signal, outputs a signal whose band is limited in the vertical direction, and supplies the signal to the adder 413. The switch 414 conducts a signal based on the motion detection signal only when a still image. In the adder 413, the vertical low band signal and the vertical high band signal are added and output. The switch 415 conducts a signal only in the case of a moving image based on the motion detection signal,
The signal is inverted by the inversion circuit 416. The output of the adder 413 and the output of the inverting circuit 416 are both input to the adder 417 and the subtractor 418. The adder 417 is the adder 41
3 and the output of the inversion circuit 416 are added, and the addition result is supplied to the double speed conversion circuit 425. The subtractor 418 subtracts the output of the inversion circuit 416 from the output of the adder 413 and supplies the subtraction result to the double speed conversion circuit 426.

The output of the adder 411 is input to the subtractor 419 and the switches 421 and 422. The subtractor 419 subtracts the vertical high-frequency component from the original signal, and inputs the vertical low-frequency component to the adder 420. The switch 421 conducts a signal based on the motion detection signal only when a still image. In the adder 420, the vertical low frequency signal and the vertical high frequency signal are added and output. The switch 422 is based on the motion detection signal,
The signal is conducted only when it is a moving image. The output of the adder 420 and the output of the switch 422 are both input to the adder 423 and the subtractor 424. The adder 423 adds the output of the adder 420 and the output of the switch 422, and supplies the addition result to the double speed conversion circuit 425. The subtractor 424 is the adder 420
Is subtracted from the output of the switch 422, and the subtraction result is supplied to the double speed converter 426.

Now, the outputs of the circuits of the first embodiment (FIG. 2) and the second embodiment (FIG. 3) will be compared with each other with reference to FIGS. 4 and 5. In the figure, vertical lines mean fields or frames, circles af mean scanning lines, and h, l
The symbol with means the output of the vertical high-pass filter and the output of the vertical low-pass filter. The black circles mean inverted scan lines.

FIG. 4A shows an interlaced scanning signal input to the input terminal 301 of the first and second embodiments. Figure 4
(2) is the output of the frame synthesis circuit 302 of FIG.
FIG. 4C shows the output of the frame synthesis circuit 302 as V-HP.
The vertical high frequency components obtained by inputting to F are shown in FIG.
(4) indicates a vertical low-frequency component. FIG. 4 (5) shows an output obtained by V-shifting the vertical high frequency component, which corresponds to the output of the V shift circuit 307 in FIG. FIG. 4 (6) shows the result of adding the component obtained by V-shifting the vertical low-frequency component and the vertical high-frequency component, which corresponds to the output of the adder 309 in FIG. FIG. 4 (7) shows the result of subtracting the component obtained by V-shifting the vertical high-frequency component from the vertical low-frequency component, and the subtracter 31 of FIG.
This corresponds to an output of 0.

FIG. 5 (11) corresponds to the output of the adder 407 for obtaining the output of the V-HPF 400 in FIG. 3, and FIG.
Corresponds to the output of the subtractor 412 that obtains the vertical low-frequency component in FIG. Further, FIG. 5 (13) corresponds to the output of the adder 411 that obtains the vertical HPF output in FIG. 3, and FIG. 5 (14) corresponds to the output of the subtractor 419 that obtains the vertical low-frequency component.

V-shifting the output of the V-HPF 303 in the first embodiment means inverting the polarity every other line. Therefore, in order to obtain a similar result in the second embodiment, This is possible by inverting the polarity of the vertical high frequency component shown in FIG. 5 (11).
The output of FIG. 5 (15) is obtained.

In order to obtain the same result as in FIG. 5 (6) with the embodiment of FIG. 3, the output of the adder 413 and the polarity inverting circuit 41 are used.
The result obtained by adding the outputs of 6 (FIG. 5 (16)),
This is possible by using the result (FIG. 5 (18)) obtained by adding the output of the adder 420 and the output of the switch 422. In order to obtain the same result as in FIG. 4 (7) in the embodiment of FIG. 3, the result obtained by subtracting the output of the adder 413 and the output of the polarity inverting circuit 416 (see FIG. 5 (1
7)) and the result obtained by subtracting the output of the adder 420 and the output of the switch 422 (FIG. 5 (19)).

Returning to FIG. 3 again, the subsequent operation will be described.

The double speed converter 425 converts the input signal into a progressive scanning signal having a frame frequency of 1/60 [sec], and inputs the signal to the selector 314. The double speed converter 426 converts the input signal into a frame frequency of 1/60 [se
c] to the progressive scanning signal, and the delay circuit 313 converts it to 1/6.
It is delayed by 0 [sec] and input to the selector 314. The selector 314 outputs 1/6 of the two input signals.
The output is switched every 0 [sec] and is output from the progressive scan conversion unit 501 via the output terminal 315.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings.

The second embodiment described above has two processing systems in order to reduce the memory used for frame composition. The signal input to the progressive scan conversion unit 501 was subjected to signal processing by simultaneously using a signal delayed by one field using a field memory and a signal applied to the input end.

Now, looking at the decoder shown in FIG. 1, the field delay circuit 231 is used for the visual interference reduction measures in the above-mentioned current receiver, and the field-delayed signal is H-LPF 232. Bandwidth limited horizontally. The band limitation in the horizontal direction is H-LPF204.
Equal to the bandwidth limit by. Therefore, the field delay (field delay circuit 40) required in the second embodiment of FIG.
This field delay circuit 231 can be utilized instead of 1).

The operation will be described with reference to FIG. Input end 20
An A / D-converted encode signal is input to 1.
The input signal is input to the Y / C separation circuit 202 and the multiple signal processing circuit 221. Multiplex signal processing circuit 221
Then, the signals multiplexed in the upper and lower non-image parts are demodulated and rearranged into 120 signals, and the time-compressed signals are expanded in time. The output of the multiple signal processing circuit 221 is input to the adder 222.

The signal input to the Y / C separation circuit 202 is separated into a luminance signal Y and a color signal C. The color signal C is sent to the color demodulation circuit 241, and the luminance signal Y is sent to the motion detection circuit 203, HL.
PF204, subtractor 207, field delay circuit 231
Entered in. The color demodulation circuit 241 performs color demodulation processing and outputs an I signal and a Q signal. I and Q signals are HL
Each band is horizontally limited by the PF 242, and 3 → 4.
The conversion circuit 243 vertically expands by 4/3 times,
The interlaced scanning signal of 0 [lines / frame] is converted into the interlaced scanning signal of 480 [lines / frame]. The scanning line converted I and Q signals are converted at the double speed by the double speed conversion circuit 244 to 4 from the interlaced scanning signal of 480 [lines / frame].
It is converted into a progressive scanning signal of 80 [lines / frame]. The double-speed converted I and Q signals are input to the matrix circuit 245.

The motion detection circuit 203 detects motion from the input Y signal and outputs a motion detection signal.

The signal input to the field delay circuit 231 is delayed by one field and input to the H-LPF 232 and the subtractor 224. The H-LPF 232 performs horizontal band limitation, and its output signal is V-HPF2.
23 and the subtractor 224. V-HPF22
In 3, vertical high frequency components are extracted. V-HPF223
Is output to the adder 222. The adder 222 adds the output of the multiplex signal processing circuit 221 and the output of the V-HPF 223 and inputs them to the LD / VH separation circuit 238.

The LD / VH separation circuit 238 separates the VH signal and the LD signal. LD / VH separation circuit 238
The VH signal output from the interlaced scanning signal is converted from the interlaced scanning signal to the progressive scanning signal by the sequential conversion circuit 239, and 360 lines /
A signal of 2: 1 is changed to a signal of 360 lines / 1: 1. The sequentially converted signals are input to the 3 → 4 conversion circuit 236, vertically expanded by 4/3 times, and the number of effective scanning lines is 360 [lines / frame] to 480 [lines / frame]. Is converted to a signal. The line-inverted circuit 237 line-inverts the scan-line converted signal and frequency-shifts it from the vertical low band to the vertical high band. Line-inverted VH
The signal is input to the adder 214.

The LD signal output from the LD / VH separation circuit 238 is level 0 every other line in the 0 insertion circuit 233.
Signal is inserted and the interlaced scanning signal of 180 [lines / field] is converted into a progressive scanning signal of 360 [lines / frame]. The 0-inserted signal is input to the V-HPF 234, the 0-level signal is interpolated, and the interpolated signal is input to the adder 235.

The Y signal input to the H-LPF 204 is band-limited in the horizontal direction, and its output is input to the 0 insertion circuit 205 and the subtractor 207.

The level 0 signal is inserted every other line in the signal input to the 0 insertion circuit 205, and the number of effective scanning lines is 18
The interlaced scanning signal of 0 [lines / field] is converted into a progressive scanning signal of 360 [lines / frame] of effective scanning lines. The 0-inserted signal is interpolated by the V-LPF 206 at the 0 level and input to the adder 235. The LD signal is added by the adder 235, and the components up to 360 LPH are reproduced in the horizontal low range.

The subtractor 207 outputs HL from the original Y signal.
The band-limited Y signal is subtracted by the PF 204 to extract a horizontal high frequency component. The extracted horizontal high frequency Y signal is sequentially input to the scan conversion unit 501. Subtractor 224
Then, from the output of the field delay circuit 231, the H-LP
A horizontal high frequency component obtained by subtracting the output of F232 is extracted and input to the progressive scan conversion unit 501.

Now, the operation of the progressive scan conversion unit 501 will be described with reference to FIG.

In the progressive scan conversion unit 501, the subtracter 2
The output of 07 is input to the input terminal 301 of FIG.
The output of 24 is input to the input end 301a. Input end 30
The signal input to 1a corresponds to the output of the field delay circuit 401 in the second embodiment. Since the following operation is the same as the operation in FIG. 3 showing the second embodiment, it will be omitted. The output of the progressive scan conversion unit 501 is input to the adder 212 (FIG. 6).

Returning to FIG. 6, the output of the adder 235 is added to the horizontal high-frequency components sequentially converted by the adder 212, and the result is 3
The 4 conversion circuit 213 vertically expands by 4/3 to convert the 360 [lines / frame] signal to a 480 [lines / frame] signal. The scanning line converted signal is added to the VH signal by the adder 214 to reproduce the components up to 480 LPH. The output of the adder 214 is input to the matrix circuit 245. In the matrix circuit 245, the input Y, I, Q signals are converted into a matrix, and R, G,
B signal is converted and output.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to the drawings.

A device that receives a letterbox format signal is required to be able to process signals other than the letterbox format (for example, current NTSC signals, VTR output signals, game machine outputs, etc.). Therefore, the present invention provides a decoder that can process signals such as the current NTSC signal without changing the parameters of the circuit and requiring additional hardware. The operation will be described below with reference to FIG. In the part different from the conventional one, the function of the H-LPF (denoted by 251) between the Y / C separation circuit 202 and the 0 insertion circuit 205 is changed, and the function is switched by the system identification signal. Further, the function of the scanning line conversion circuit between the adder 212 and the adder 214 is changed, and the function is also switched by the identification signal. Further, a switch 253 is provided between the adders 234 and 212, and a switch 254 is also provided between the line inverting circuit 237 and the adder 214.

In FIG. 8, an input terminal 201 has an A / D converted letterbox format signal or a current NTSC signal.
A signal or the like is input. The input signal is input to the Y / C separation circuit 202 and the multiple signal processing circuit 221. Further, the identification signal detection circuit detects whether the input signal is a letterbox EDTV signal or another signal, and outputs an identification signal. H-LPF251
Is an H-LPF when the identification signal is an EDTV signal.
It operates as a (horizontal low pass filter) and the identification signal is N
In the case of a TSC signal or the like, a signal with a filter coefficient of 0 is output. The identification signal of the 3 → 4 converter 252 is EDTV.
, It operates as a vertical scanning line conversion circuit,
When the identification signal is an NTSC signal or the like, it operates as a horizontal compression circuit or a delay adjustment circuit. Switch 25
3, 254 conducts when the identification signal is an EDTV signal and does not pass a signal when the identification signal is an NTSC signal or the like.

First, when the identification signal indicates the EDTV signal, the operation of the decoder shown in FIG. 8 is the same as that of the first embodiment, and therefore its explanation is omitted here.

Next, the operation when the identification signal indicates an NTSC signal or the like will be described.

The signal input to the input terminal 201 is input to the Y / C separation circuit 201 and the multiple signal processing circuit 221.
The signal output from the multiplex signal processing circuit 221 is cut off by the switches 253 and 254, so the operation will not be described here.

The signal input to the Y / C separation circuit 202 is separated into a luminance signal Y and a color signal C, the color signal C is sent to the color demodulation circuit 241, and the luminance signal Y is sent to the motion detection circuit 203, HL.
It is input to the PF 251 and the subtractor 207. The color demodulation circuit 241 performs color demodulation processing and outputs an I signal and a Q signal. The I and Q signals are band-limited in the horizontal direction by the H-LPF 242, vertically expanded by 4/3 times in the 3 → 4 conversion circuit 243, and 480 [lines / frame] from the interlaced scanning signal of 360 [lines / frame]. [Frame] interlaced scanning signal. The scanning line converted I and Q signals are converted at a double speed by the double speed conversion circuit 244 and converted from the interlaced scanning signal of 480 [lines / frame] to the sequential scanning signal of 480 [lines / frame]. The double-speed converted I and Q signals are input to the matrix circuit 245.

The motion detection circuit 203 detects motion from the input Y signal and outputs a motion detection signal.

Since the Y signal input to the H-LPF 251 is multiplied by the coefficient 0, 0 is output. Its output is 0
It is input to the insertion circuit 205 and the subtractor 207. Since the signal input to the 0 insertion circuit 205 is cut off by the switch 253, the operation will not be described here. The subtractor 207 subtracts the band-limited Y signal from the original Y signal by the H-LPF 251.
Since the output of 1 is 0, the original Y signal is output. The Y signal output from the subtractor 207 is the progressive scan conversion circuit 5
08 is input.

The output of the progressive scan conversion circuit 508 is the adder 2
It is input to the 3 → 4 conversion circuit 252 via 12. 3 → 4
Since the conversion circuit 252 operates as a horizontal 4 → 3 converter according to the identification signal, the input signal is compressed to 3/4 in the horizontal direction. The compressed signal is input to the matrix circuit 245 via the adder 214.

In the matrix circuit 245, the input Y,
The I and Q signals are matrix-converted into R, G and B signals and output.

As another method, it is conceivable to use the 3 → 4 conversion circuit 252 as a delay adjustment circuit and not perform horizontal compression. In this case, since the circularity cannot be maintained if the image is output as it is, the deflection angle of the CRT is adjusted and displayed.

Although the present embodiment has been described with reference to the embodiment in which the progressive scanning output is obtained, switching the circuit operation by the identification signal to perform the signal processing can also be applied to the decoder system which outputs the interlaced scanning signal. .

The above-described decoder system can improve the image quality of the progressive scan conversion output signal in the band in which the compensation signal is not transmitted. Also, by sharing the existing field delay circuit, the amount of memory used can be reduced. Also, even if a signal other than the letterbox format is input, without significantly changing the circuit,
It can be processed by a circuit for processing a letterbox format signal.

[0112]

As described above, in the decoder of the letter box system which multiplexes and transmits the additional signal to the upper and lower non-image parts by the encoder and reproduces a high-definition image by using the additional signal multiplexed by the decoder, Since the progressive scan conversion of the band in which the compensation signal is not transmitted is performed using the signal in which the frame is a unit, the progressive scan conversion is performed using the information amount twice as much as the signal obtained by the intra-field interpolation.
The image quality of the progressive scan output signal can be improved. Further, by using the output of the delay circuit used for other purposes together, it is possible to reduce the amount of memory used for the progressive scan conversion circuit. Further, even when a signal other than the letterbox format is input, the signal processing can be performed without significantly changing the circuit.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an embodiment according to the present invention.

FIG. 2 is a diagram for explaining a first embodiment of a progressive scan conversion circuit according to the present invention and its operation.

FIG. 3 is a diagram for explaining a second embodiment of the progressive scan conversion circuit according to the present invention and its operation.

FIG. 4 is a diagram for supplementarily explaining the operation of the circuit of FIG.

FIG. 5 is a diagram for supplementarily explaining the operation of the circuit of FIG.

FIG. 6 is an overall block diagram of a decoder showing a third embodiment according to the present invention.

7 is a detailed block diagram of a progressive scan conversion unit 501 in FIG.

FIG. 8 is an overall block diagram of a decoder showing a fourth embodiment according to the present invention.

FIG. 9 is a diagram showing a conventional encoder.

FIG. 10 is a diagram showing a conventional decoder.

FIG. 11 is a diagram showing a conventional encoder.

FIG. 12 is a diagram showing a conventional decoder.

FIG. 13 is a diagram showing an example of a conventional progressive scan converter.

[Explanation of symbols]

202 ... Y / C separation circuit, 203 ... Motion detection circuit, 20
4 ... Horizontal low-pass filter (H-LPF), 205 ... 0
Insertion circuit, 206 ... Vertical low-pass filter (V-LP
F), 207 ... Subtractor, 212 ... Adder, 213 ... 3 →
4 converter, 214 ... Adder, 221 ... Multiplex signal processing circuit, 222 ... Adder, 223 ... Vertical low-pass filter (V-LPF), 231 ... Field delay circuit, 232
... Horizontal low-pass filter, 233 ... 0 insertion circuit, 234
Vertical vertical high pass filter (V-HPF), 235 ... Adder, 236 ... 3 → 4 converter, 237 ... Line inversion circuit,
238 ... LD / VH separation circuit, 239 ... Progressive scan converter, 241 ... Demodulation circuit, 242 ... Horizontal low-pass filter, 243 ... 3 → 4 converter, 244 ... Double speed converter, 24
5 ... Matrix circuit, 501 ... Progressive scan conversion unit, 30
2 ... Frame synthesizing circuit, 303 ... Vertical high-pass filter, 304 ... Subtractor, 305 ... Adder, 306 ... Switch, 307 ... Vertical shift circuit, 308 ... Switch, 30
9 ... Adder, 310 ... Subtractor, 311, 312 ... Double speed converter, 313 ... Delay adjusting circuit, 314 ... Selector, 40
0 ... Vertical high-pass filter (V-HPF), 401 ... Field delay circuit, 402, 403 ... Line memory, 4
04 406, 408-410 ... Coefficient unit, 407, 41
1 ... Adder, 412 ... Subtractor, 413 ... Adder, 41
4, 415 ... Switch, 416 ... Inversion circuit, 417 ... Adder, 418, 419 ... Subtractor, 420 ... Adder, 42
1, 422 ... Switch, 423 ... Adder, 424 ... Subtractor, 415, 426 ... Double speed converter, 224 ... Subtractor.

Claims (6)

[Claims] 1. A first television signal having N scanning lines (N is an integer) is compressed to M scanning lines (M is an integer, N> M), and the compressed signal is reinforced. Of the signal of the number M of scanning lines one field before the multiplex signal of 1 field is encoded after being band-limited, and the attenuated multiplexed signal has the remaining number of scanning lines (N-
M) a device to which the respective television signals of the second television signal multiplexed into the book and the third television signal of the number of scanning lines N (N is an integer) are input, Discriminating means for discriminating between the television signal and the third television signal, and operating on the basis of the discriminating signal from the discriminating means, and when the second television signal is inputted, the number of scanning lines is M. Means for separating the signal in the horizontal direction into a signal in the same band as the compensation signal in the horizontal direction and a signal in a higher band than that, and a motion for detecting a motion of an image from the input signal to obtain a motion detection signal. A detecting unit; and a frame synthesizing unit for converting the n-field (n is an integer) of the high-band signal and the signal obtained by delaying the (n-1) -field signal by one field into a frame-based signal. , Said Separating means for further separating the signal obtained from the synthesizing means into a vertical high-frequency signal and a vertical low-frequency signal, and the vertical high-frequency signal or the vertical high-frequency signal to the vertical low-frequency signal according to the motion detection signal. Arithmetic means for arithmetically operating the shifted signal and the vertical low-frequency signal, means for speed-converting the arithmetic result by the arithmetic means to convert interlaced scanning signals to progressive scanning signals, and band limiting the input signals. Extracted signal,
A television signal processing apparatus comprising: means for calculating this signal and the compensation signal obtained by decoding the attenuated multiplexed signal, and converting the calculation result into a scanning signal in order. 2. An apparatus for converting interlaced scanning signals into progressive scanning signals, wherein n fields (n is an integer) and (n-
1) A signal obtained by delaying a field signal by one field is passed through a vertical high-pass filter, and an output of the vertical high-pass filter and an input signal are calculated to obtain a vertical high-pass signal and a vertical low-pass signal. Signal separation means, motion detection means for detecting an image motion from the input signal to obtain a motion detection signal, and n fields (n is an integer) and (n-
1) A frame synthesizing unit for converting a field signal into a signal in which a frame is united with a signal delayed by one field; and a signal for determining the vertical high frequency signal or the vertical high frequency signal according to the motion detection signal. And a signal processing unit for calculating the vertical low-frequency signal, and a unit for converting the calculation result of the calculation unit into a scanning signal from an interlaced scanning signal by performing speed conversion. apparatus. 3. A signal obtained by delaying the signal of the (n-1) field by one field is a multiplexed signal which is transmitted by subtracting a vertical high frequency component of a signal of M scanning lines before one field. 3. The television signal processing device according to claim 2, wherein the delay signal is added to the vertical high frequency components of the signal of the number M of scanning lines one field before to obtain a compensation signal. . 4. The number N of scanning lines (N is an integer) of a first television signal is compressed into the number M of scanning lines (M is an integer, N> M), and the number of scanning lines M one field before is obtained. A second television signal in which the compensation signal by the vertical high-frequency component of the book signal is band-limited and then encoded into a multiplexed signal, and the attenuated multiplexed signal is multiplexed into the remaining number of scanning lines (NM). And a third television signal of N scanning lines (N is an integer), which are input to the respective television signals, the second television signal and the third television signal being distinguished from each other. And a conversion unit that operates based on the identification signal from the identification unit and that converts into a progressive scanning signal without separating in the horizontal direction when the third television signal is input. Television communications characterized by Processing apparatus. 5. A first television signal having N scanning lines (N is an integer) is compressed to M scanning lines (M is an integer, N> M), and the scanning line number M one field before is obtained. A second television signal in which the compensation signal by the vertical high-frequency component of the book signal is band-limited and then encoded into a multiplexed signal, and the attenuated multiplexed signal is multiplexed into the remaining number of scanning lines (NM). And a third television signal of a scanning line number N (N is an integer), respectively, in a device to which the second television signal and the third television signal are input. And a conversion unit that operates based on the identification signal from the identification unit and that converts the signal of M scanning lines to N / M times when the third television signal is input. Switching to switch to compression means for horizontally compressing means Television signal processing apparatus characterized by having means. 6. A first television signal having N scanning lines (N is an integer) is compressed into M scanning lines (M is an integer, N> M), and the scanning line number M one field before is obtained. A second television signal in which the compensation signal by the vertical high-frequency component of the book signal is band-limited and then encoded into a multiplexed signal, and the attenuated multiplexed signal is multiplexed into the remaining number of scanning lines (NM). And a third television signal of a scanning line number N (N is an integer), respectively, in a device to which the second television signal and the third television signal are input. And a conversion unit that operates based on the identification signal from the identification unit and that converts the signal of M scanning lines to N / M times when the third television signal is input. Switching means for switching the means to delay means for delay adjustment Television signal processing apparatus characterized by having.