JPH07161843A - Sram device - Google Patents

Abstract

PURPOSE:To provide an SRAM device which can reduce a memory cell and which is manufactured easily in the SRAM device having an additive capacitance which is used to enhance a soft error-resistance property. CONSTITUTION:A capacitance C between storage nodes for every memory cell for an SRAM is constituted of an impurity-diffused layer 25 formed on the surface of a semiconductor substrate 30, of first conductive layer 24 and of a gate insulating film 32 which is formed between the impurity-diffused layer 25 and the first conductive layer 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM (Static Random Access Memory) device having improved soft error resistance.

[0002]

2. Description of the Related Art In SRAM devices, α has become
The problem of soft error caused by lines is a problem. For example, when the SRAM is highly integrated, the current per unit memory cell becomes smaller, while natural uranium (U) contained in a trace amount in the ceramic package material and the lid material for sealing the semiconductor memory element is released. When α rays enter the semiconductor memory element, a large number of electron-hole pairs are generated in the substrate and the generated electrons move in the substrate to destroy the information (charge) stored in the memory cell. The phenomenon that the memory malfunctions occurs.

Therefore, an SRAM using a TFT as a load transistor has been developed. By using the TFT as the load transistor, excellent memory retention characteristics, high soft error resistance, and low standby current can be achieved. However, such a TFT type S
Even in RAM, it is difficult to obtain sufficient soft error resistance, and further improvement in soft error resistance has been studied.

As a measure for further improving the soft error resistance, a structure is adopted in which charges can be accumulated between the storage nodes of the memory cells. Soft error rate (SE
It is necessary to accumulate a charge of about 8 fC in the storage node so that (R) becomes 200 FIT or less (at the power supply voltage of 2 V).

From this point of view, in the 0.5 μm rule (4 Mb SRAM), in addition to the parasitic capacitance, 0.5 fF
It is necessary to add the capacity of. This capacity is traditionally
For example, as shown in FIG. 7, it is generally formed between the third conductive layer 2 which becomes the gate electrode of the TFT and the fourth conductive layer 4 in which the channel region of the TFT is formed.
In this case, the electrode area of the capacitor is
It was 0.43 μm. The area of the memory cell is 1
Since it is 8 μm ² , the effect of increasing the cell area due to the addition of capacitance is relatively small.

FIG. 7 shows a cross section of a memory cell for a TFT load type SRAM device.
The element isolation region 8 and the gate insulating film 10 are formed, and the first conductive layer 1 having, for example, a polycide structure is formed thereon.
2 is formed. The first conductive layer 12 becomes the gate electrodes of the drive transistor and the selection transistor. The second conductive layer 1 is formed on the first conductive layer 12 via an interlayer insulating film.
4, the third conductive layer 2 and the third conductive layer 4 are sequentially stacked. The second conductive layer 14, the third conductive layer 2 and the third conductive layer 4 are composed of, for example, a polysilicon film. Second
A reference power supply line V _ss is formed on the conductive layer 14, for example. A metal wiring layer 16 is deposited on the fourth conductive layer 4 via an interlayer insulating film. The metal wiring layer 16 is used as a bit line.

In the 0.4 μm rule SRAM device,
Similar to the 0.5 μm rule SRAM device, the additional capacitance for reducing the soft error rate is added to the third conductive layer 2.
And the fourth conductive layer 4 are formed. However,
In the 0.4 μm rule SRAM device, as compared with the 0.5 μm rule SRAM device, the memory cells are further miniaturized and the parasitic capacitance is reduced. Therefore, it is necessary to increase the additional capacitance for reducing the soft error rate. is there. Therefore, the calculated electrode area is 0.79 μm ² .
However, the cell area was 9.98 μm ² , and the ratio of the electrode area to the cell area was still low.

[0008]

In the SRAM device of the 0.25 μm rule, as in the SRAM device of the 0.4 μm rule, the additional capacitance for reducing the soft error rate is the third conductive layer 2 and the fourth conductive layer. It is formed between the layers 4. However, in the 0.25 μm rule SRAM device, as compared with the 0.45 μm rule SRAM device,
Since the memory cell is further miniaturized and the parasitic capacitance is reduced, it is necessary to increase the additional capacitance for reducing the soft error rate. Therefore, in calculation, the required additional capacitance is 2 fF, and the electrode area is 1.7 μm ² . Since the cell area is 3.3 μm ² (when no additional capacitance is provided), the ratio of the electrode area to the cell area is large. Therefore, in the actual cell pattern having the additional capacity, it is necessary to make the cell area twice as large as that of the cell pattern having no additional capacity.

As described above, in the conventional SRAM device in which the additional capacitance for reducing the soft error rate is formed between the third conductive layer and the fourth conductive layer, as the memory cell becomes finer, the additional capacitance is increased. Therefore, the electrode area for forming the memory cell must be increased, and there is a problem that the memory cell area cannot be reduced as compared with the SRAM device having no additional capacitance.

Although it is conceivable to make the interlayer insulating film between the third conductive layer and the fourth conductive layer thin in order to reduce the electrode area of the additional capacitance, the interlayer withstand voltage and insulation reliability should be improved. It cannot be too thin to secure.
In addition, the literature (IEDM91, 17.4, Nos. 477 to 48)
As shown in page 0), a method of forming a necessary additional capacitance by further increasing the number of conductive layers such as a polysilicon layer has also been proposed. However, this method has a problem that the manufacturing process becomes long because the conductive layer is further added.

The present invention has been made in view of the above circumstances, and provides an SRAM device having an additional capacity for improving soft error resistance, in which memory cells can be downsized and which is easy to manufacture. The purpose is to do.

[0012]

In order to achieve the above object, the SRAM device according to the present invention has a capacitance between the storage nodes of each SRAM memory cell that is different from that of an impurity diffusion layer formed on the surface of a semiconductor substrate. , A first conductive layer and an insulating film formed between the impurity diffusion layer and the first conductive layer.

The word line serving as the gate electrode of the select transistor is preferably divided into two for each memory cell.

[0014]

In the SRAM device according to the present invention, the capacitance between the storage nodes of the SRAM memory cells is controlled by the impurity diffusion layer formed on the surface of the semiconductor substrate, the first conductive layer, the impurity diffusion layer, and the first diffusion layer. And an insulating film formed between the conductive layers. The insulating film formed on the surface of the semiconductor substrate is
For example, it is formed by a thermal oxidation method and used as a gate insulating film. This insulating film is a good quality insulating film as compared with an interlayer insulating film formed between conductive layers, and can be thinned to about 8 nm.

By using this insulating film as a capacitive insulating film for improving soft error resistance, the size of the capacitive electrode can be reduced. If the size of the capacitor electrode can be reduced, it contributes to the size reduction of the memory cell. For example, assuming a 0.25 μm rule SRAM device, an 8 nm gate insulating film formed on the surface of a semiconductor substrate is
If it is used as a capacitance insulating film, in order to obtain a capacitance of 2fF (in the case of the capacitance between storage nodes, the capacitance is doubled in consideration of the mirror effect), 0.46 μm ²
Electrode area is required. The increase in cell area in the case of adding capacitance largely depends on whether or not the electrode pattern matches the cell pattern well. If the layout could be done most efficiently, the increase in cell area is about 3 times larger than the layout of a cell without capacitance.
The increase is 0%. By the way, in the SRAM device in which the additional capacitance is formed between the third conductive layer and the fourth conductive layer, the increase of the cell area is about twice or more, and in comparison with that, the area of the memory cell of the SRAM device of the present invention is increased. The rate of increase is small,
The cell area can be reduced.

A word line serving as a gate electrode of the selection transistor is divided into two for each memory cell.
In a so-called divided word line type SRAM device, a layout is easily formed by partially changing the layout pattern of the gate electrode of the drive transistor. That is, by only partially changing the layout pattern of the memory cells of the divided word line type SRAM device, it is possible to form a capacitor for improving the soft error resistance between the first conductive layer and the semiconductor substrate.

Further, in the SRAM device of the present invention, the soft error resistance can be improved without increasing the number of conductive layers. Therefore, the manufacturing process does not become complicated.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An SRAM device according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. 1 is a plan view of a main part of a memory cell for an SRAM device according to an embodiment of the present invention,
2 to 4 are main-portion plan views showing patterns of conductive layers sequentially stacked on the memory cell shown in FIG. 1, and FIG. 5 shows manufacturing steps of the main portion of the memory cell shown in FIG. Show V-V
FIG. 6 is a sectional view taken along the line, and FIG. 6 is an equivalent circuit diagram of the memory cell shown in FIGS.

An SRAM device according to an embodiment of the present invention is
This is a TFT load type SRAM device, and a large number of memory cells MC having a laminated pattern shown in FIGS. 1 to 4 are formed on a semiconductor substrate. The memory cell MC of the SRAM device of this embodiment is
It has an equivalent circuit of the configuration shown in FIG.

As shown in FIG. 6, an SRAM memory cell using a TFT as a load transistor has a pair of driving transistors Q1 and Q1 which form a flip-flop circuit.
Q2 and a selection transistor Q3 for selecting a memory cell
, Q4 and load transistor Q5 composed of TFT
, Q6. Selection transistors Q3, Q4
Responds to the gate voltage generated on the word line W (W1, W2) to turn on the transistor and store the information stored in the flip-flop circuit composed of the driving transistors Q1 and Q2 in the bit line b and the inverted bit. It is adapted to transmit on line b '. Drive transistors DQ1, D
The Q2 and the selection transistors SQ3 and SQ4 are N-channel MOS formed on the semiconductor substrate, as described later.
Load transistors LQ5 and L
Q6 is composed of a P-channel TFT composed of a thin film formed on them.

In this embodiment, as shown in FIG. 6, a capacitance C for improving the soft error resistance is formed between both storage nodes n ₁ and n ₂ of the memory cell MC. The capacitance C is formed between the first conductive layer and the semiconductor substrate, as will be described later. As shown in FIG. 1, the SRAM of this embodiment
In the one memory cell MC of the device, the gate electrodes 20a, 20b, 22a, 2 having the pattern shown in FIG.
With 2b. These gate electrodes are obtained by patterning the first conductive layer. The first conductive layer is formed of, for example, a polysilicon layer or a polycide layer (a laminated film of a polysilicon layer and a silicide layer).

The gate electrodes 20a and 20b also serve as the divided word lines W1 and W2, and cross the upper and lower sides of the memory cell MC substantially in parallel to form select transistors SQ3 and SQ4. The gate electrodes 22a and 22b are divided word lines W1,
Formed between W2 and driving transistors DQ1 and DQ, respectively
Configure Q2.

In this embodiment, the upper capacitance electrode 24 is formed of the same first conductive layer as the gate electrode 22a of the drive transistor DQ1. These gate electrodes 20
The first conductive layer on which a, 20b, 22a, 22b and the upper capacitance electrode 24 are formed is formed on the element isolation region (LOCOS) 26 and the N-type impurity diffusion layer 28 formed on the surface of the P-type well. It The N-type impurity diffusion layer 28 is
Each memory cell MC is formed in the pattern shown in FIG.
It serves as the N-type source / drain regions of the drive transistors DQ1 and DQ2 and the select transistors SQ3 and SQ4, and also functions as the lower capacitance electrode 25 (the portion indicated by the dotted line in FIG. 1) below the upper capacitance electrode 24.

As shown in FIG. 5B, gate insulation is provided between the semiconductor substrate 30 and the first conductive layer forming the gate electrodes 20a, 20b, 22a, 22b and the upper capacitor electrode 24 shown in FIG. A film 32 is formed. The gate insulating film 32 is formed, for example, by thermally oxidizing the surface of the semiconductor substrate 30, and is made of a silicon oxide film or the like.

The N-type impurity diffusion layer 28 serving as the source / drain regions shown in FIG. 1 and FIG.
It is formed by ion-implanting N-type impurities from above 0a, 20b, 22a, and 22b. This N-type impurity diffusion layer 28
The manufacturing method described later is adopted to configure the lower capacitor electrode 25 formed on the surface of the semiconductor substrate 30 so as to be connected with the N-type impurity diffusion layer. 1 and 5
The lower capacitor electrode 25, the gate insulating film 32, and the upper capacitor electrode 24 shown in (B) form the capacitor C shown in FIG.

The gate electrodes 20a, 20b, 2 shown in FIG.
2a, 22b and the first conductive layer forming the upper capacitance electrode 24 and the impurity diffusion layer 2 serving as the source / drain regions
Reference numeral 8 is connected to the second, third, fourth conductive layers and metal wiring layers shown in FIGS. 2 to 4 through contact holes in order to configure the circuit of memory cell MC shown in FIG.

The second conductive layer laminated on the first conductive layer via the interlayer insulating layer has the contact position changing layers 40 and 44 and the reference power supply line Vss having the pattern shown in FIG.
As the interlayer insulating layer, a silicon oxide layer, a silicon nitride layer, a PSG layer, a BPSG layer, or the like is used. The second conductive layer is made of, for example, a polysilicon film. The contact position changing layer 40 shown in FIG.
Through the source / drain region diffusion layer 28 of the select transistor SQ3 shown in FIG.
It is a layer for shifting to the position of 8.

The reference power supply line Vss shown in FIG. 2 is connected to the source / drain region diffusion layers of the drive transistors DQ1 and DQ2 shown in FIG. 1 through the contact holes 50 and 52, respectively. Contact position changing layer 44 shown in FIG.
Is connected through the contact hole 54 to the source / drain region diffusion layer 28 of the select transistor SQ4 shown in FIG. 1 located on the lower layer side and shifts the extraction position of the bit line b ′ to the position of the contact hole 56. It is a layer.

In FIG. 1, the contact hole 5
Reference numerals 8 and 60 denote the source / drain region diffusion layers 2 of the drive transistors DQ1 and DQ2, which form the gate electrodes 22a and 22b of the drive transistors DQ1 and DQ2, respectively.
8 for cross coupling.

These contact position changing layers 40, 44
And on the second conductive layer on which the reference power supply line Vss42 is formed, the TF having the pattern shown in FIG.
A third conductive layer forming the T gate electrodes 62 and 64 is laminated. The third conductive layer is composed of, for example, a polysilicon layer. These gate electrodes 62 and 64 become the gate electrodes of the load transistors LQ5 and LQ6, and through the contact holes 58 and 60, the drive transistor D shown in FIG.
It is connected to the gate electrodes 22a and 22b of Q1 and DQ2.

On the third conductive layer on which the gate electrode is formed, a fourth conductive layer forming the channel forming layers 66 and 68 having the pattern shown in FIG. 3 is laminated via an interlayer insulating layer. The fourth conductive layer is composed of, for example, a polysilicon layer. The fourth conductive layers forming the channel forming layers 66 and 68 are connected to the other gate electrodes 62 and 64 forming a pair through the contact holes 70 and 72, respectively, and form the channels of the TFTs forming the load transistors LQ5 and LQ6. Together, they constitute the power supply line Vdd.

As shown in FIG. 4, the word lines W1 and W2 (see FIG. 1) are formed on the fourth conductive layer forming the channel forming layers 66 and 68 through the interlayer insulating layer in the memory cell MC. ) And two patterns of parallel first metal wiring layers 74 and 76 arranged in a direction substantially perpendicular to the above are stacked. The first metal wiring layers 74 and 76 are made of, for example, aluminum or aluminum alloy. The first metal wiring layers 74 and 76 are
The contact position changing layers 40 and 44 of the second conductive layer shown in FIG. 2 are connected through the contact holes 60 and 56 to form the bit lines b and b '.

Next, a method of manufacturing the SRAM device according to this embodiment will be described. First, as shown in FIG. 5A, L (not shown) is formed on the surface of the semiconductor substrate 30 by a selective oxidation method using a silicon nitride film as an oxidation prevention mask.
Semiconductor substrate 3 forming OCOS and surrounded by LOCOS
An insulating film 31 for pad having a film thickness of about 10 nm is formed on the surface of No. 0 by the thermal oxidation method. Next, before depositing the first conductive layer and before forming the impurity diffusion layer 28 to be the source / drain regions, a resist film 34 is formed, and the resist film 3 is formed.
4, an opening 36 is formed in a pattern slightly larger than the lower capacitance electrode 25, and an N-type impurity is ion-implanted into the surface of the semiconductor substrate 30 through the opening 36 to form the lower electrode 25.

The specific conditions for the ion implantation are not particularly limited. For example, arsenic As or phosphorus Phos is used as the ion implantation source, and if it is As, 30 KeV, Ph
If it is os, the ion implantation energy of 20 KeV is 1
The condition is a dose amount of × 10 ¹³ to 1 × 10 ¹⁴ . The dose amount necessary to sufficiently convert the diffusion layer to be the lower capacitance electrode 25 into N is necessary, but if it is too large, there is a possibility that the film thickness of the gate insulating film increases, the breakdown voltage deteriorates, and the LOCOS film deteriorates. Therefore, the above range is preferable.

Next, the resist film 34 shown in FIG. 5A is removed and an annealing treatment (for example, 800 ° C. and 30 ° C.) is performed.
Is performed to recover the film quality of the LOCOS film in the ion-implanted portion, and the pad insulating film 31 is removed by dilute hydrofluoric acid treatment. As shown in FIG. The film 32 is formed by a thermal oxidation method or the like, and a first conductive layer having, for example, a polycide structure (a laminated film structure of a polysilicon film and a silicide film) is deposited on the film 32, and patterns 20a, 20b, 22a shown in FIG. , 22b.

After that, as shown in FIG. 5B, ion implantation for forming a low concentration N-type impurity layer is performed in order to make the impurity diffusion layers to be the source / drain regions have an LDD structure, and then the insulation is performed. Conductive sidewall 38 is formed on a side portion of the first conductive layer having a predetermined pattern, and the source / source
Ion implantation is performed to form the N-type impurity diffusion layer 28 to be the drain region.

The subsequent process is the usual TFT type SR.
This is similar to the manufacturing process of the AM device. SR of this embodiment
In the AM device, as shown in FIG. 5, the capacitance C between the storage nodes of the SRAM memory cell is set to the lower capacitance electrode 25 formed of the impurity diffusion layer formed on the surface of the semiconductor substrate 30.
And an upper capacitance electrode 24 formed of the first conductive layer, and a gate insulating film 32 formed between the lower capacitance electrode 25 and the upper capacitance electrode 24. Semiconductor substrate 30
The gate insulating film 32 formed on the surface of is formed by, for example, a thermal oxidation method. The gate insulating film 32 is a good quality insulating film as compared with an interlayer insulating film formed between conductive layers, and can be thinned to about 8 nm.

By using the gate insulating film 32 as a capacitive insulating film for enhancing soft error resistance, the size of the capacitive electrode can be reduced. If the size of the capacitor electrode can be reduced, it contributes to the size reduction of the memory cell. For example, assuming that a 0.25 μm rule SRAM device is used and an 8 nm gate insulating film formed on the surface of a semiconductor substrate is used as a capacitive insulating film, it is 2 fF.
In order to obtain the capacity (in the case of the capacity between the storage nodes, the effect of the capacity is doubled in consideration of the mirror effect),
An electrode area of 0.46 μm ² is required. By patterning this electrode area in the dotted hatching portion shown in FIG. 1, the dimensions of the memory cell MC are 3.35 μm in the vertical direction and 1.35 in the horizontal direction.
Next to 45 μm, the cell area is 4.86 μm ² . Compared with the cell area when there is no load capacity for soft error measures, the cell area increases by about 50%, which is a conventional example in which the load capacity is formed between the third conductive layer and the fourth conductive layer. In comparison, the cell area can be reduced. By the way, in the SRAM device in which the additional capacitance is formed between the third conductive layer and the fourth conductive layer, the increase of the cell area is about twice or more, and in comparison with this, the memory cell of the SRAM device of this embodiment is The area increase rate is small and the cell area can be reduced.

In this embodiment, the selection transistor S
The word lines W1 and W2 to be the gate electrodes 20a and 20b of Q3 and SQ4 are divided into two lines for each memory cell, that is, a so-called divided word line type, and the gate electrodes of the conventional drive transistors DQ1 and DQ2 are The capacitance electrode C can be formed by only partially changing the layout pattern. That is, the conventional divided word line SRA
The capacitance C for improving the soft error resistance can be formed between the first conductive layer and the semiconductor substrate by only partially changing the layout pattern of the memory cell of the M device.

Further, in the SRAM device of this embodiment, the soft error resistance can be improved without increasing the number of conductive layers. Therefore, the manufacturing process does not become complicated. The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways within the scope of the present invention.

For example, the insulating film of the capacitor C is formed on the semiconductor substrate 3
Any insulating film other than the gate insulating film may be used as long as it is an insulating film formed to 0.

[0042]

As described above, according to the present invention, by using the insulating film formed on the surface of the semiconductor substrate as the capacitive insulating film for enhancing the soft error resistance, the size of the capacitive electrode can be increased. Can be made smaller. If the size of the capacitor electrode can be reduced, it contributes to the size reduction of the memory cell.

In a so-called divided word line type SRAM device in which a word line serving as a gate electrode of a select transistor is divided into two for each memory cell, a layout pattern of a gate electrode of a drive transistor is partially used. By making changes, the layout makes it easy to form the capacitor electrodes. That is, by only partially changing the layout pattern of the memory cells of the divided word line type SRAM device, it is possible to form a capacitor for improving the soft error resistance between the first conductive layer and the semiconductor substrate.

Further, in the SRAM device of the present invention, the soft error resistance can be improved without increasing the number of conductive layers. Therefore, the manufacturing process does not become complicated.

[Brief description of drawings]

FIG. 1 is a plan view of an essential part of a memory cell for an SRAM device according to an embodiment of the present invention.

FIG. 2 is a plan view of a principal part showing a pattern of a conductive layer laminated on the memory cell shown in FIG.

FIG. 3 is a plan view of relevant parts showing a pattern of a conductive layer stacked on the memory cell shown in FIG.

FIG. 4 is a plan view of a principal portion showing a pattern of a conductive layer laminated on the memory cell shown in FIG.

5A and 5B are cross-sectional views taken along the line VV shown in FIG. 1, showing a manufacturing process of a main part of the memory cell shown in FIG.

FIG. 6 is an equivalent circuit diagram of the memory cell shown in FIGS.

FIG. 7 is a cross-sectional view of a main part of an SRAM device according to a conventional example.

[Explanation of symbols]

 20a, 20b, 22a, 22b ... Gate electrode 24 ... Upper capacitance electrode 25 ... Lower capacitance electrode 28 ... Impurity diffusion layer 30 ... Semiconductor substrate 32 ... Gate insulating film n1, n2 ... Storage node b, b '... Bit line DQ1, DQ2 ... Driving transistor SQ3, SQ4 ... Selection transistor LQ5, LQ6 ... Load transistor (TFT) C ... Coupling capacitance MC ... Memory cell

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78

Claims (2)

[Claims] 1. A SRAM device in which a first conductive layer formed on a semiconductor substrate serves as gate electrodes of a drive transistor and a selection transistor, and a capacitance between storage nodes of each SRAM memory cell is equal to that of the semiconductor substrate. An SRAM device comprising an impurity diffusion layer formed on a surface, the first conductive layer, and an insulating film formed between the impurity diffusion layer and the first conductive layer. 2. The SRAM device according to claim 1, wherein a word line serving as a gate electrode of the select transistor is divided into two for each memory cell.