JPH07160757A - Fpga timing automatic adjustment system - Google Patents

Abstract

PURPOSE:To automatically adjust the timing of setup or hold violation at the time of dividing and mapping an FPGA circuit. CONSTITUTION:A delay data file 12 is generated by timing analysis means 7 to 11, and the number of delay elements is calculated in accordance with the violation margin in a step 14, and a signal line to which a delay element will be inserted is deleted in a step 15, and the delay element is inserted together with a new signal line in a step 16. The first delay data file is used as a delay master file 13 and is converted to information of the difference from the next generated delay data file 12 to obtain a difference data file, thus managing the generation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic timing adjustment system for an FPGA (Field Programmable Gate Array), and more particularly, within an FPGA, between FPGAs and FPG
The present invention relates to an automatic FPGA timing adjustment system for eliminating a timing deviation between boards on which A is arranged.

[0002]

2. Description of the Related Art In a conventional FPGA timing adjustment system, the following method is used.

The first method is a method of manually correcting the placement and wiring results of the gate array, and its flowchart is shown in FIG. First, layout pattern layout 26
And the wiring 27 is automatically designed, and the simulation 28 is performed on the result of the design, and if the timing deviation tolerance standard is not satisfied, the layout is manually changed 29,
Alternatively, the circuit change 30 is performed, and the arrangement 26 and the rewiring 27 are performed again.

The second method is a method of adjusting the timing for each single integrated circuit, and its flowchart is shown in FIG. First, the inter-element connection information is changed 31 and the layout pattern is automatically placed and routed 32. Then, the delay time is calculated 33 in the layout pattern, and the delay elements for each delay element are corrected so as to correct the timing deviation of each part. The replacement pattern determination 34 and the pattern replacement 35 of each delay element are performed.

[0005]

Among the above-mentioned conventional methods, the former method of manually changing the layout or the circuit has a drawback that the design period and the design cost increase.

Further, in the second method for automatically adjusting the timing for each single integrated circuit, since the violation margin generated between the integrated circuits is not taken into consideration, after the layout in each integrated circuit is designed, In many cases, it is necessary to change the circuit and layout of the integrated circuit again, which has the drawback of increasing the design period and the design cost. Furthermore, in a logic circuit composed of a plurality of FPGAs, layout pattern information needs to be divided and stored for each FPGA unit, and when performing delay correction only on a signal line in which setup and hold violation has occurred, a delay element in the system is used. If the connection information of the signal line whose circuit is changed by inserting or deleting is extracted and the difference data is not generation-managed, all the layout information divided into each FPGA unit must be re-divided when delay-corrected. I have to. Even when the delay pattern is partially adjusted, even if the layout pattern does not fit in the FPGA, it is necessary to divide the layout pattern into all FPGAs again.

An object of the present invention is to solve the above-mentioned problems and automatically eliminate setup or hold violation that occurs in FPGAs, between FPGAs, and between boards on which FPGAs are arranged. It is in.

[0008]

SUMMARY OF THE INVENTION The automatic timing adjustment system of the present invention is arranged in and between each FPGA in a logic circuit composed of a plurality of boards on which a plurality of field programmable gate arrays (FPGAs) are arranged. Performs static timing analysis based on the wired layout pattern information, and outputs delay timing analysis means that outputs data for setup or hold violation margin and path name of the signal line, and information on the violation margin and path name. The FP
File generation means for extracting only layout pattern information in which a violation has occurred in and between GAs and generating a delay data file in which the instance name and pin name of the element and the violation margin are described from the extracted pattern information Then, the number of delay elements to be inserted or released from the signal line extracted from the violation margin is calculated, the original signal line to be inserted or released from the delay element is released, and the layout pattern in the FPGA is set. When a violation occurs, the delay element is inserted or released together with a new signal name, and the F
When a layout pattern between PGAs violates, a delay timing adjusting means for inserting or releasing a delay element together with a new signal name is provided.

[0009]

The present invention will be described below with reference to the drawings.

2A and 2B are circuit diagrams illustrating a logic circuit in which a delay element is added to a signal line connected in the middle of a sequential circuit composed of flip-flops 1 and 2. When setup or hold violation occurs between the flip-flops 1 and 2 in FIG.
As shown in FIG. 7B, the timing adjustment is performed by adding the NAND 5 for the delay element and the new connection information of this NAND 5 after deleting the original net name (netA) in FIG. Indicates the operation to be performed.

FIG. 1 is a flow chart showing an embodiment of the present invention, in which timing adjustment is automatically performed using the operations of FIGS. 2 (a) and 2 (b). Each FPGA based on the layout pattern of each FPGA and the connection information 7 between FPGAs
Arrangement and wiring 8 are performed for each, and timing analysis 9 is performed. As a result, when the timing shift due to the delay time does not satisfy the allowable standard, the report file 10 in which the violation margin shortage and the path name are described is output. From the report file 10 and the layout pattern information 7 in and between each FPGA, the layout pattern information 7 in and between FPGAs with a violation margin is extracted 11 to create a delay data file 1
1 is performed and the delay data file 12 in which the instance name and pin name of the violation margin element are described is output, and the information of the delay data file 12 is appended as the delay master file 13. Also, the number of stages of delay elements is calculated 14 from the violation margin of the delay data file 12, the signal line for adding or deleting the delay elements is deleted 15, and the delay elements for the number of stages of the delay elements calculated with the new signal name are inserted. Alternatively, it is deleted 16. When inserting or deleting the delay element, the delay element inserted or deleted between the FPGAs is woven or deleted in the FPGA on the input side.

FIGS. 3A and 3B are flow charts illustrating the difference data extraction method in this embodiment. First, the difference between the old delay data and the new delay data file 17 from the timing analysis process is extracted 18 and the delay insertion time, the delay data difference information 19 describing the element instance and the pin name are output, and this information is used. Based on the netlist database 20, the differential information of the delay data is format-converted 21. The differential data file 22 after the format conversion 21 includes a net name to be deleted, an instance name and a pin name of an element, and a net name to be added by the circuit change, and an instance name of a delay element due to a circuit change due to delay insertion or deletion And the pin name are described.
This difference file 22 is appended as the delay master file 13 and generation-managed. Further, the information of the difference file 22 is incorporated into the netlist database 20 by incorporating the circuit-changed information, so that the information of the netlist database 20 is changed every time the timing is automatically adjusted when the violation occurs due to the timing analysis. Further, the layout pattern in each FPGA is rearranged / wired 8 for the changed information.

FIGS. 4A to 4C are shown in FIGS. 3A and 3B.
6 is a format diagram showing a format of a difference file 22 in FIG. First, FIG. 9A describes the connection information changed before and after the timing analysis. For example, the first line is connection information before delay adjustment, and describes the signal line to be deleted. In this format,
The first column describes the signal name, and the second column describes the connection between the elements by which the signal line is connected by the instance name and pin name of the element. Further, the third column distinguishes whether the signal line is added or deleted by the identification data (DEL = delete, ADD = add).

FIG. 4 (b) describes the instance name and the primitive name of the added delay element, and also uses identification data to indicate whether these delay elements are added or deleted. The first column is the instance name, the second column is the primitive name, and the third column is the identification data for addition or deletion.

FIG. 4C describes the library name of the delay element (second column) added in the first column. Therefore, this table enables correspondence between each library and each primitive.

[0016]

As described above, according to the present invention, in the layout design of the integrated circuit which requires the variation of the propagation delay time of the signal to be less than a certain limit, the division of the netlist into the FPGA and From the report file of the static timing analysis tool at the time of placement and routing, extract the netlist inside the FPGA with the violation margin from the netlist of each FPGA, calculate the number of delay elements and delay from this violation margin. By deleting the signal line for adding the element and adding the function of adding the delay element together with the new signal line, the design period can be shortened and the cost can be reduced as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a flowchart of an embodiment of the present invention.

2A and 2B are circuit diagrams illustrating an operation of adding a delay element according to an embodiment of the present invention.

3A and 3B are flowcharts showing a method of extracting difference data according to an embodiment of the present invention.

4A to 4C are format diagrams illustrating a generation management method of the differential data in FIGS. 3A and 3B.

FIG. 5 is a flowchart of a first example of the related art.

FIG. 6 is a flowchart of a second example of the related art.

[Explanation of symbols]

 1 Flip-flop 2,6 Pin name 3,4 Net name 5 Delay element

Claims (2)

[Claims] 1. A static timing analysis based on layout pattern information arranged and wired in and between each FPGA in a logic circuit composed of a plurality of boards on which a plurality of field programmable gate arrays (FPGAs) are arranged. The delay timing analysis means for outputting the setup line and hold violation margin of the signal line and the path name, and the FPG from the information of the violation margin and the path name.
File generation means for extracting only layout pattern information in which violation has occurred in and between A and generating a delay data file in which the instance name and pin name of the element and the violation margin are described from the extracted pattern information. Then, the number of delay elements to be inserted or released from the signal line extracted from the violation margin is calculated, the original signal line to be inserted or released from the delay element is released, and the layout pattern in the FPGA is set. When a violation occurs, the delay element is inserted or released with a new signal name, and the FP
An automatic timing adjustment system for an FPGA, comprising: a delay timing adjusting means for inserting or releasing a delay element together with a new signal name when a violation occurs in a layout pattern between GAs. 2. When the delay data file is repeatedly updated and generated, a difference in contents between the delay data file at each time and the delay data file immediately before that time is extracted, and the delay master file is hair-pended each time. 2. The FPGA automatic timing adjustment system according to claim 1, further comprising management means for history management.