JPH07105783B2 - Staff synchronizer - Google Patents

Description

The present invention relates to a stuff synchronizer that detects a phase shift between two data and synchronizes them.

[Prior Art] FIG. 9 is a block connection diagram showing a conventional stuff synchronizer, in which 1 is a first-in first-out (hereinafter referred to as FIFO), which is sent from a terminal through a line 5. The incoming data is the input signal, and the output signal is
Is supplied to the latches 3a and 3b. Further, the output signal 11 from the control circuit 2 and the inverted terminal clock 6b are
Input to FO1. 12 is a phase comparator, which uses the terminal clock 6a and the first transmission line clock 4a as input signals,
These phases are compared, a delayed pulse 7a or an overtaking pulse 7b is output and input to the control circuit 2. The clock of the first transmission line is also input to the control circuit 2. Reference numeral 9 is an output signal of “insert” or “delete”, which is output from the control circuit 2. Output signals 10a and 10b from the control circuit 2 are input to the clock terminals of the latches 3a and 3b, respectively. The output signal from the latch 3a is sent to the first transmission line 21, and the output signal from the latch 3b and the "insert" and "delete" output signals 9 form the data to the second transmission line 22.

Next, the operation will be described. First, the data sent from the terminal via the line 5 is taken into the FIFO 1 at the timing of the clock 6b. The phase comparator 12 compares the phase of the terminal clock 6a with the phase of the first transmission path clock 4a. If the deviation is within 360 °, no signal is sent to the control circuit 2, but the first When the delay of the phase of the clock of the transmission line is 360 °, the delay pulse 7a is sent to the control circuit 2 and the advance pulse 7b is sent to the control circuit 2.
The control circuit 2 sends the clock 4a of the first transmission path to the FIFO 1 while no signal is sent from the phase comparator 12, so that the output signal 8 is output at this timing and the latch 3a
The output signal 10a to the first transmission line 21 is immediately turned on, and the data is output to the first transmission line 21. At this time, since the output signal 10b is turned off, no data is output to the second transmission line 22. When the delayed pulse 7a comes, the control circuit 2 puts the information of "insertion" on the output signal 9, and the clock 4b of the second transmission line.
Output signal 11b, turn on output signal 11 and immediately output signal 10b
Is turned on, the output signal 8 from the FIFO1 is taken into the latch 3b, and the data is output. At this time, the output signal 10a is off, and no data is output to the first transmission line 21. From the data output from the latch 3b and the "insertion" signal of the output signal 9, data to the second transmission line 22 is created. As a result, one bit, which could not be sent because the first transmission path clock 4b was slower than the terminal clock 6a, was sent using the second transmission path. On the contrary, when the overtaking pulse 7b arrives at the control circuit 2, the output signal 9
Send'Delete 'information to. The clock 4b of the first transmission line is faster than the clock 6a of the terminal and one bit more is sent, so when the clock 4b of the second transmission line comes, the clock of the first transmission line that comes after that. Output signal 4a only once 11
Do not put the data on the FIFO, and do not take the data from the FIFO1 at this time.

[Problems to be Solved by the Invention] Since the conventional stuff synchronizer is configured as described above, when one phase is overtaken by 360 °, one bit is added and a delay of 360 ° occurs. It is necessary to delete one bit, and the phase comparator 1
When I tried to investigate in 2, there were problems such as lack of stability and complicated circuit when the phase lead changed drastically.

The present invention has been made in order to solve the above-mentioned problems, and changes of the clock of the terminal and the clock of the transmission line are
It is an object to obtain a stuff synchronizer that can be examined using a simple circuit.

[Means for Solving the Problems]

The stuff synchronizer according to the present invention inputs the data on the terminal side into the FIFO via the first latch and transfers it to the first transmission line via the second latch according to the speed of the first transmission line. If the input enable signal of the FIFO is prohibited by the phase detection circuit at the timing of the clock on the terminal side, it is assumed that a delay has occurred once and the information of'insertion 'and the data from the FIFO are output. Output to the second transmission line, and at the timing of the clock of the first transmission line, the FI
If the output permission signal of FO is prohibited, it is assumed that overtaking has occurred once, and the information of “delete” is sent to the second transmission line, and once the data is transmitted at the timing of the first transmission line. Is not taken out from the FIFO.

[Action]

The phase detection circuit according to the present invention, when the input permission signal of the FIFO is prohibited, determines that the delay has occurred once and outputs the information of “insertion” and the data from the FIFO to the second transmission line. However, if the output permission signal of the FIFO is disabled,
When it is determined that the overtaking has occurred once, the information of “deletion” is output to the second transmission path, and the data is not taken out from the FIFO at the timing of the first transmission path thereafter.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, reference numeral 3c is a latch as a first latch, which uses data sent from the terminal via the line 5 as an input signal, and an output signal is sent to the FIFO1 via the input line 13. FIF
The output signal from O1 is input to the latch 3a which is the second latch and the phase detection circuit 15 through the output line 14, and the output signal from the latch 3a is output to the first transmission line 21. The input permission signal 16 and the output permission signal 17 are also output from the FIFO 1, and these are input to the phase detection circuit 15. Terminal clock 6a,
The clock 4a of the first transmission line and the clock 4b of the second transmission line are also supplied to the phase detection circuit 15. From the phase detection circuit 15, the input latch clock 18, the input FIFO clock 19, the output
FIFO clock 20 and output latch clock 10a are output,
Control data is output to the second transmission path 22.

FIG. 3 is an operation explanatory diagram when the phase shift is within an allowable range, FIG. 4 is an operation explanatory diagram when a delay occurs, and FIG. 5 is an operation explanatory diagram when an overtaking occurs.

Next, the operation will be described.

First, when the phase shift is within the allowable range,
When the input enable signal 16 is enabled at the trailing edge of the second terminal clock 6a, the phase detection circuit 15 sends an inverted clock of the terminal clock 6a as the input latch clock 18 and the input FIFO clock 19. When the input enable signal 16 is enabled, it means that the FIFO1 has an empty space.The data previously latched by the latch 3c is input to the FIFO1, new data is latched by the latch 3c, and the input line to the FIFO1 is input. Output to 13. When the input enable signal 16 is enabled, at the point A on the terminal clock 6a, the terminal data 31'e 'is latched by the latch 3c, and the previously latched data'd' is input to the FIFO1. It The state at this time is shown in the data state 33 immediately after the point A. Next, the first transmission line 21
When the clock 4a comes in, the phase detection circuit 15 outputs the first output FIFO clock 20 and the first output latch clock 10a as long as the output enable signal 17 is enabled as in the data status 34 immediately after the point B.
Since the clock 4a of the transmission line 21 is sent, the data is output from the FIFO1 and, at the same time, the data is output to the first transmission line 21 as indicated by the data 32 of the first transmission line 21. Next, as indicated by point C of the terminal clock 6a, when the terminal clock 6a arrives, the phase detection circuit 15 sends the input latch clock 18 and the input FIFO clock 19, so the previous data'e 'is stored in the FIFO1. The data status 35 immediately after the point C is input.

Next, regarding the operation when the phase shift occurs, first, the case where the delay occurs will be described. The phase detection circuit 15 checks the state of the input permission signal 16 every time when the terminal clock 6a arrives. As shown in the data situation 37 immediately after the point A in FIG. 3, all the data is stored in the FIFO1. When the terminal clock 6a arrives at the point C in the jammed state, the input detection signal 16 is prohibited, so that the phase detection circuit 15 determines that a delay has occurred and performs the following processing.

When the clock 4b of the second transmission line comes before the point B of the clock 4a of the first transmission line, the information of "insertion" is given to the second point.
To the transmission line 22, and then the output FIFO clock 20 is sent once to extract one data from the FIFO1. The state at this time is shown in the data state 38 immediately after the point C. According to this, since the data'b 'was sent using the second transmission line 22,
There is no'b 'on the data 32 of the first transmission line.
Then, the input latch clock 18 and the input FIFO clock 19 are sent once to input the data'g 'which could not be captured at the point C.

The state at this time is shown in the data state 39 immediately after the point C.
When the point B of the clock 4a of the first transmission line comes faster than the clock 4b of the second transmission line, the data in the FIFO1 is output and the input permission signal 16 is permitted. Therefore, the input latch clock 18 and the input FIFO clock 19 are sent to input the data that could not be captured at the point C. Then, when the clock 4b of the second transmission line comes, "insert"
Information from the FIFO1 to the second transmission line 22 and the output line 14 from the FIFO1.
The above data is fetched and sent to the second transmission line 22. Then, the output FIFO clock 20 is sent once, and the data on the output line 14 from the FIFO1 has already been sent.
Output from FIFO1.

Next, the operation when overtaking occurs will be described. The phase detection circuit 15 checks the state of the output permission signal 17 every time the clock 4a of the first transmission line arrives, but as shown in the data status 40 immediately after point A in FIG. When the number of data of 1 is 1, B, D of the clock 4a of the first transmission line
If two clocks 4a of the first transmission line come like the point, when the point D comes, the FIFO1 is already empty as shown in the data situation 41 immediately after the point B. The output permission signal 17 is prohibited. The phase detection circuit 15 has a first
If the output enable signal 17 is disabled when the clock 4a of the transmission line of 4 comes, it is assumed that overtaking has occurred, and first, the clock is sent only to the output latch clock 10a, and the data on the output line 14 from the FIFO 1 is sent. Is output to the first transmission line 21, and the state at this time is shown in the data state 42 immediately after the point D. Then, the following processing is performed.

Next to the point E, which is the clock 4a of the first transmission line,
When the clock 4b of the transmission line of 1 comes earlier, only the information of'deletion 'is sent to the second transmission line 22. As shown in'c 'of the data 32 of the first transmission line, the data sent at the point E is the same data as before, but since the information of'delete' is sent, this data is sent by the other station. Be thrown away.

When the next transmission line clock 4a, point E, has not arrived yet and the second transmission line clock 4b has not yet arrived, the data status 43 immediately after point C is obtained. So
The clock is sent to the output FIFO clock 20 once, and the data status 44 immediately after the point E is set, and then the clock is sent to the output FIFO clock 20 and the output latch clock 10a to output burst data. And the clock 4b of the second transmission line
When it comes to, it sends the information of "delete" and stops sending the output FIFO clock 20 and the output clock 10a only once.

FIG. 5 shows another embodiment of the present invention. In the figure, the latch 3c receives the data sent from a terminal (not shown) via the line 5, and the output signal is sent to the FIFO 1 via the input line 13. The output signal from the FIFO1 is supplied to the latch 3a and the phase detection circuit 15 via the output line 14,
The output signal from 3a is output to the first transmission line 21. FI
An input permission signal 16 and an output permission signal 17 are also output from FO1, and these are supplied to the phase detection circuit 15. The inverted terminal clock 6b is connected to the latch 3c and the input clock terminal of the FIFO1. The clock 4a of the first transmission line and the clock 4b of the second transmission line are input to the phase detection circuit 15, the output FIFO clock 20 and the output latch clock 10a are output from the phase detection circuit 15, and the second Control data is output to the transmission path 22.

FIG. 6 is an operation explanatory diagram when the phase shift is within the allowable range, FIG. 7 is an operation explanatory diagram when a delay occurs, and FIG. 8 is an operation explanatory diagram when an overtaking occurs.

Next, the operation will be described.

First, when the phase shift is within the allowable range,
The phase detection circuit 15 checks the input permission signal 16 and the output permission signal 17, and considers that the phase shift is within the allowable range unless it is prohibited for a certain time or longer. This fixed time is
This is the time during which the input enable signal 16 is disabled while data is being input to the FIFO1, and the time during which the output enable signal 17 is disabled while data is being output from the FIFO1. Then, while it is within the allowable range, the clock 4a of the first transmission line is sent to the output FIFO clock 20 and the output latch clock 10a. Since the inverted terminal clock 6b is input to the latch 3c and the input clock terminal of the FIFO1, the terminal data 31 is latched by the latch 3c at the falling edge of the terminal clock 6a, and is input to the input line 13 to the FIFO1. Data is input to FIFO1. When the data status 45 immediately after point A, B of clock 4a of the first transmission line
Even if the point comes, as shown in the data status 46 immediately after the point B, since the data still remains in the FIFO1, the output enable signal 17 is immediately enabled. Further, at this time, even if the point C of the terminal clock 6a comes, as shown in the data status 47 immediately after the point C, there is still empty space in the FIFO1, so the input enable signal 16 is immediately enabled. .

Next, regarding the operation when the phase shift occurs, first, the case where the delay occurs will be described. The phase detection circuit 15 assumes that a delay has occurred when the input permission signal 16 is prohibited for a certain time or longer, which is shown in FIG. When the C point of the terminal clock 6a comes in the data situation 48 immediately after the A point, the inverted terminal clock 6b is sent to the input clock terminal of the latch 3c and the FIFO1, and the data situation 49 immediately after the C point appears. However, since there is no more empty space in the FIFO1, the input permission signal 16 remains prohibited even after a certain period of time, and the phase detection circuit 15 performs the next process. When the clock 4b of the second transmission line arrives, the information of "insertion" is sent to the second transmission line 22, and the data on the output line 14 from the FIFO1 is taken in and sent to the second transmission line 22. Then, the output FIFO clock 20 is sent once, and since the data on the output line 14 from the FIFO1 has already been sent, the next data is output from the FIFO1.

Next, a case where overtaking occurs will be described. The phase detection circuit 15 assumes that overtaking has occurred when the output permission signal 17 is prohibited for a certain period of time or more, which is shown in FIG. When the clock 4a of the first transmission line arrives in the data status 50 immediately after the point A, the data status 52 immediately after the point D is obtained. Since the FIFO 1 no longer contains data, the output enable signal 17 remains disabled even after a certain period of time, and the phase detection circuit 15 performs the next process. Clock of the second transmission line
When 4b comes, send the information of "Delete" to the second transmission line 22,
The output FIFO clock 20 and the output latch clock 10a are not sent once when the clock 4a of the first transmission line comes after that. The same data as before is sent to the first transmission line 21, but since the information of'deletion 'is sent, this data is discarded by the partner station. In this case,
A 180 ° delay and a 180 ° overtaking were detected, but 360 ° ・ n + 1
To detect a delay of 80 °, output starts from the state of 1 + n empty after reset, and to detect overtaking of 360 ° n + 180 °, after 2 + n data is accumulated after resetting, Let the output start.

The present invention is also applicable to the case where the clock 4a and the data 32 of the first transmission line are a plurality of continuous burst clocks and burst data of different speeds. In this case, the FIFO1 As for the data, the size of the data must be larger than the data sent in bursts, and after reset, the data must be stored in excess of the number of data sent in bursts before output. In this case, assuming that n is the number of data sent in bursts, the allowable range is -360 ° ・ n to 360 ° ・ n and -360 ° ・ (n + m) to 360 ° ・ ( n + m)
In this case, the FIFO1 in which n + m pieces of data are stored is used.

Further, in relation to the other embodiment described above, when the clock 4a and the data of the first transmission line are the burst clock and the bust data, respectively, n is 360 ° .n as the number of data transmitted in burst. Delay and 360 ° ・ n overtaking can be detected, but to detect 360 ° ・ (n + m) delay, output is started from the state of 1 + m empty after reset and 360 ° ・ (n + m) To detect the overtaking, output may be started after 1 + n + m pieces of data are accumulated after reset.

〔The invention's effect〕

As described above, according to the present invention, the data on the terminal side is
Input to the FIFO via the latch, and output to the first transmission line via the second latch according to the speed of the first transmission line, and the timing of the clock on the terminal side by the phase detection circuit If the input enable signal of the FIFO is prohibited at the time, the information of'insertion 'and the data from the FIFO is output to the second transmission line, assuming that the delay has occurred once.
If the output permission signal of the FIFO is prohibited at the timing of the clock of the first transmission line, it is determined that overtaking has occurred once, and the information of “delete” is sent to the second transmission line, and then Since the data is not taken out from the FIFO once at the timing of the first transmission line of, the phase shift of the two data can be easily detected by checking the input permission signal and the output permission signal of the FIFO. Moreover, there is an effect that a circuit for simplifying the detection can be obtained.

[Brief description of drawings]

FIG. 1 is a block connection diagram showing a stuff synchronizer according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram showing an operation when a phase shift in the present invention is within an allowable range, and FIG. FIG. 4 is an operation explanatory view showing an operation when a delay occurs in the present invention, FIG. 4 is an operation explanatory view showing an operation when an overtaking occurs in the present invention, and FIG. 5 is a staff according to another embodiment of the present invention. FIG. 7 is a block connection diagram showing the synchronizer, and FIG. 6 is an operation explanatory diagram showing an operation when the phase shift in the embodiment of FIG.
FIG. 8 is an operation explanatory view showing an operation when a delay occurs in the embodiment of FIG. 5, FIG. 8 is an operation explanatory view showing an operation when an overtaking occurs in the embodiment of FIG. 5, and FIG. FIG. 4 is a block connection diagram showing a conventional stuff synchronization device. 1 is a first-in first-out (FIFO), 3c is a first latch, 3a is a second latch, and 15 is a phase detection circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first transmission line and a second transmission line for transmitting asynchronous data given from a terminal side, wherein the data rate on the terminal side is higher than the data rate on the first transmission line. In the case of transmitting excess information and transmitting excess information through the second transmission line, if the data rate on the terminal side is slower than the data rate of the first transmission line, excess data will be transmitted. In a stuff synchronizer for transmitting information to be transmitted through a second transmission line, a first latch for latching the data on the terminal side and data from the first latch are input and the first latch is input. According to the data rate of the transmission line, the first-in first-out which outputs to the first transmission line via the second latch and the first-in first-out at the timing of the clock of the terminal. When the force permission signal is in the prohibition,
Assuming that a delay has occurred once, the information of'insertion 'and one data from the first-in first-out are added to the above second.
If the output permission signal of the first-in first-out is prohibited at the timing of the clock of the first transmission line, the information of'delete 'is assumed to be one overtaking. Is sent to the second transmission line,
A stuff synchronizer, comprising: a phase detection circuit for preventing data from being taken out from the first-in first-out once at the subsequent timing of the first transmission path.