JPH0685778A - Jitter suppression system in smoothing circuit - Google Patents

Abstract

PURPOSE:To suppress low frequency jitter regardless of a frequency of occurrence of pointer action in the smoothing circuit. CONSTITUTION:A stuff control detecting section 1 detects a pointer action from an asynchronous data signal, a write clock generating section 2 generates a byte stuffing clock from a clock of the asynchronous data signal. Then valid data in the asynchronous data signal are written in a buffer memory 3, and a PLL circuit 5 smoothes the clock. A missing accumulation distribution section 4 distributes the accumulated byte stuff values in the unit of bits nonlinearly to generate a bit stuffing clock, and a PLL circuit 11 smoothes the clock. A changeover section 17 selects an output clock of either of both the PLL circuits in response to the quantity of the accumulated value in the missing accumulation distribution section 4 and an output of the section 17 reads data in the buffer memory 3 as a read clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for smoothing a stuffed signal, and more particularly to SDH, SONET.
The present invention relates to a jitter suppression method in a smoothing circuit that can effectively suppress low-frequency jitter when performing a pointer action in units of 1 byte in a new synchronous transmission network such as.

For example, in the case of SONET, the STS-1 frame has an address indicating the start position of data as a pointer, but since the start position of data changes when byte-multiplexed, the pointer is also updated accordingly. There is a need to.

Further, when signals are multiplexed / demultiplexed, a stuff byte is inserted in order to match the difference in frequency of each signal, but the insertion of the stuff byte changes the data start position, which has occurred. Data gaps are covered by pointer actions.

It is desired that the jitter suppressing method in the smoothing circuit at the time of such a pointer action can effectively suppress the low frequency jitter.

[0005]

2. Description of the Related Art The stuffing technique is used as a method for establishing a synchronous network, but SDH based on CCITT recommendation and SO standardized in North America.
With the standardization of new synchronous interfaces such as NET, there is a tendency to shift from the conventional bit multiplex system to the byte multiplex system.

The problem of the jitter suppression technique in the byte multiplexing system is that the stuffing frequency is much smaller than that in the bit multiplexing system, so that the stuffing frequency is low and the cutoff of the low-pass filter of the clock recovery circuit used in the past is low. Since the frequency is lower than the frequency, the occurrence of low frequency jitter is inevitable.

At this time, if the cutoff frequency of the low-pass filter is simply set to be low to suppress the low frequency jitter, the lock-in range of the phase locked loop (PLL) for generating a clock in the stuffing circuit. However, such a method cannot be used since

On the other hand, conventionally, the following various methods have been used. FIG. 3 shows an example of a jitter suppression method in a conventional smoothing circuit, in which the band of a low-pass filter that suppresses the stuffing frequency is
A method of controlling according to the occurrence frequency of the pointer action is shown.

In FIG. 3, reference numeral 21 denotes a separating unit which separates data and clock from an asynchronous signal and outputs the same, and detects the occurrence of a pointer action. A buffer memory 22 is used to write data by the separated clock. A phase comparator 23 compares the phases of the write clock and the read clock. Reference numeral 24 is a low-pass filter, which is a phase comparator 23.
The output of is integrated to generate a band-limited output.

A voltage-controlled oscillator 25 generates a signal having a frequency that changes according to the magnitude of the output of the low-pass filter 24. Reference numeral 26 is a frequency divider, which divides the output frequency of the voltage controlled oscillator 25 to generate a read clock, whereby the smoothed data is read from the buffer memory 22. A control unit 27 changes the band of the low-pass filter 24 according to the frequency of generation of the pointer action detection signal in the separation unit 21.

In the system shown in FIG. 3, the band of the low-pass filter is narrowed every time a pointer action is detected within a predetermined time, and when the pointer action is not detected within the predetermined time, the low-pass filter is detected. By performing the control of returning the band sequentially or all at once, it is possible to suppress the occurrence of low frequency jitter.

Specifically, in the digital phase locked loop (D-PLL) circuit constituting the circuit of FIG. 3, the output of the phase comparator for obtaining the phase difference information between the write clock and the read clock of the memory is counted. It is realized by switching control of the set value of the up / down counter stepwise or continuously.

FIG. 4 shows another example of a jitter suppressing method in a conventional smoothing circuit, which is called a bit leak method, in which a toothless clock in byte units is once accumulated and By distributing the cumulative value in a non-linear manner to generate a bit stuff signal smoothed by a moving average method within a fixed time, and applying this to a conventional PLL circuit,
It is intended to suppress the occurrence of low frequency jitter.

In FIG. 4, reference numeral 31 is a write clock generator, which is a clock in the received data and STS-1.
A write clock for synchronous transmission network data is generated from the overhead signal in the frame. A buffer memory 32 writes synchronous transmission network data in response to the write clock. An accumulation unit 33 accumulates a byte stuffing signal which is a stuffing signal in byte units.

Reference numeral 34 denotes a distributor, which non-linearly distributes the accumulated value in the accumulator 33, for example, densely at the center and sparse at the ends to generate a smoothed bit stuff signal. Reference numeral 35 denotes a bit stuffing unit, which is used to receive the clock in the received data, the overhead signal,
A read clock for the buffer memory 32 is generated from the bit stuff signal from the distributor 34.

Reference numeral 36 denotes a smoothing unit, which is composed of a PLL circuit, and temporarily stores the data read from the buffer memory 32 in the internal memory in response to the read clock from the bit stuffing unit 35, and the PLL circuit The smoothed clock of the bit stuffing unit 35 is used to read the data in the internal memory to output smoothed asynchronous transmission network data in which the occurrence of low frequency jitter is suppressed.

At this time, when the follow-up of the read clock is delayed due to the continuous pointer action, and the data is in the alarm area of the buffer memory, the bit stuff section 35 self-runs to generate the read clock. Try to follow.

[0018]

In the conventional method shown in FIG. 3, since the cutoff frequency of the low pass filter is controlled according to the frequency of occurrence of the pointer action,
Even if the frequency of occurrence of the pointer action is low, the occurrence of low frequency jitter can be suppressed.

However, the control of the cut-off frequency of the low-pass filter is limited, and when the frequency of occurrence of the pointer action is extremely low, the control of the cut-off frequency of the low-pass filter cannot follow this. However, there is a problem that the occurrence of low frequency jitter cannot be avoided.

Further, in the conventional method shown in FIG. 4, the toothless clocks in byte units at the time of pointer action are temporarily accumulated, and the accumulated value is non-linearly distributed to generate a smoothed bit stuff signal, which is generated by the PLL. By applying it to the circuit, the occurrence of low frequency jitter is suppressed.

Therefore, it is effective when the frequency of occurrence of the pointer action is low, but when the frequency of occurrence of the pointer action is high, it takes time to create the bit stuff signal, so that the reading of the data from the buffer memory is delayed. There is a problem that the memory overflows and the memory overflows.

The present invention is intended to solve such a problem of the prior art, and it is possible to suppress the occurrence of low-frequency jitter even when the frequency of occurrence of pointer actions is low, and to suppress the occurrence of pointer actions. It is an object of the present invention to provide a jitter suppression method in a smoothing circuit in which a memory overflow does not occur even when the occurrence frequency is high and the memory only has one stage.

[0023]

FIG. 1 shows the basic configuration of the present invention. The present invention relates to a stuff control detection unit 1 that detects that stuff control is performed from a byte stuffed asynchronous data signal and generates a pointer action detection signal, and an asynchronous data signal in response to the generation of the pointer action detection signal. A write clock generator 2 for generating a byte stuffing clock from a synchronized clock, a buffer memory 3 for writing valid data in an asynchronous data signal by the byte stuffing clock, and a first PLL for generating a clock obtained by smoothing the byte stuffing clock. A circuit 5 and a toothless accumulating and distributing unit 4 for accumulating byte stuff values according to a pointer action detection signal and non-linearly distributing the cumulative values in bit units to generate a bit stuffing clock.
And a second PLL circuit 11 for generating a clock obtained by smoothing a bit stuffing clock, and a first PLL circuit 5 according to the magnitude of the cumulative value in the missing tooth cumulative distribution unit 4.
And a switching unit 17 for selecting the output clock of the second PLL circuit 11 and the output of the switching unit 17 is used as a read clock to read the data of the buffer memory 3.

[0024]

The pointer action detection signal is generated by detecting that the stuff control is performed from the byte stuffed asynchronous data signal. Then, in response to the generation of the pointer action detection signal, a byte stuffing clock is generated from the clock synchronized with the asynchronous data signal, and the valid data in the asynchronous data signal is written in the buffer memory 3 using this byte stuffing clock as a write clock.

On the other hand, the missing tooth accumulative distribution unit 4 accumulates the byte stuff value in accordance with the pointer action detection signal and distributes the accumulated value nonlinearly in bit units to generate a bit stuffing clock.

The first PLL circuit 5 generates a clock obtained by smoothing the byte stuffing clock, and the second PLL circuit 11 generates a clock obtained by smoothing the bit stuffing clock.

Then, the output clock of the first PLL circuit 5 and the output clock of the second PLL circuit 11 are selected and output according to the magnitude of the cumulative value in the missing tooth cumulative distribution unit 4, and this output is output. The data in the buffer memory 3 is read as a read clock.

Therefore, according to the present invention, it is possible to obtain, as an output, smoothed data in which low-frequency jitter is suppressed, regardless of the occurrence frequency of pointer actions.

[0029]

2 shows an embodiment of the present invention, in which a stuffing control detector 1 detects a pointer action from an asynchronous data signal separated from a synchronous frame. 2 is a write clock generator,
A toothless clock in bytes is created corresponding to a pointer action from a clock synchronized with an asynchronous data signal. A buffer memory 3 writes valid data in the asynchronous data signal. A missing tooth cumulative distribution unit 4 creates missing tooth clocks distributed in bit units based on detection of pointer actions.

Reference numeral 5 denotes a first PLL circuit, which is a frequency divider (1 / N) for dividing the clock on the write side by N, and a frequency divider (1 / N) for dividing the clock on the read side by N. ) 7, a frequency comparator 6 for comparing the output phases of the frequency dividers 6, 7, a low-pass filter 9 for band-limiting the output of the phase comparator 8, and a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the low-pass filter 9 ( VCO) 10.

Reference numeral 11 is a second PLL circuit, which is a divider (1 / N) 12 for dividing the clock on the write side by N, and a divider (1 for dividing the clock on the read side by M × N). / (M
XN)) 13, a phase comparator 14 for comparing the output phases of the frequency dividers 12, 13, a low-pass filter 15 for band-limiting the output of the phase comparator 14, and a voltage whose oscillation frequency is controlled by the output of the low-pass filter 15. Controlled oscillator (VC
O) 16.

Reference numeral 17 denotes a switching unit, which responds to the switching control signal from the missing tooth accumulating and distributing unit 4 to VCO10 and VCO1.
The output of 6 is switched and output. 18 is the frequency division (1 /
In M), the output of the switching unit 17 is divided by M to generate a read clock for the buffer memory 3.

The stuffing control detector 1 detects that stuffing control has been performed from the asynchronous data signal, and generates a pointer action detection signal. When the pointer action detection signal is generated, the write clock generation unit 2 invalidates the clock of the invalid data portion from the clock synchronized with the asynchronous data signal, and creates the byte stuffing clock with missing teeth in byte units, The asynchronous data signal is read into the buffer memory 3 by this clock.

In the PLL circuit 5, the divider 6 divides the byte stuffing clock from the write clock generator 2 by N, and the divider 7 divides the read clock of the buffer memory 3 by N. To the phase comparator 8 for phase comparison. The output of the phase comparator 8 is band-limited through the low-pass filter 9 and applied to the VCO 10 as a control voltage, so that the VCO 10 outputs a smoothed clock having a frequency corresponding to the control voltage.

On the other hand, the missing tooth accumulative distribution unit 4 generates a bit stuffing clock by accumulating the number of pointer action detections within a predetermined time and nonlinearly distributing the accumulated value in bit units.

In the PLL circuit 11, the frequency divider 12 divides the bit stuffing clock from the missing tooth accumulator 4 by N and the divider 13 divides the clock generated by the VCO 16 by M × N. And are added to the phase comparator 14 to perform phase comparison. The output of the phase comparator 14 is band-limited through the low-pass filter 15 and is applied to the VCO 16 as a control voltage.
Outputs a smoothed clock having a frequency corresponding to the control voltage.

The missing tooth cumulative distribution unit 4 sends a switching control signal according to the cumulative value of the number of times of pointer action detection.
Output to 5. As a result, the switching unit 17 causes the VCO
10 output is selected and when this value is small, VCO16
Switch to select the output of. Frequency divider 18
Divides the output of the switching unit 17 by M and supplies it to the buffer memory 3 as a read clock, whereby the smoothed data is read from the buffer memory 3.

VCO1 in both PLL circuits 5 and 11
The oscillation frequencies of 0 and 16 are M times the read clock frequency in the buffer memory 3, and both VCOs 10 and 1
The difference in oscillation frequency of 6 is a slight difference in duty of the read clock.

In the circuit shown in FIG. 2, with this configuration, when the frequency of occurrence of the pointer action is low, low frequency jitter is obtained by the conventional jitter suppression method of the bit leak method shown in FIG. Is suppressed and the frequency of occurrence of pointer actions is high, the conventional PLL
Since the low frequency jitter is suppressed by the jitter suppression method using, the low frequency jitter can be suppressed regardless of the occurrence frequency of the pointer action.

[0040]

As described above, according to the present invention, P
Since the jitter suppression method using the LL and the jitter suppression method using the bit leak method are switched and used, low frequency jitter can be suppressed regardless of the frequency of occurrence of pointer actions.

That is, according to the present invention, in the case of the jitter suppression method using the PLL, it is possible to prevent the occurrence of low frequency jitter when the pointer action occurs less frequently, and it is possible to prevent the jitter by the bit leak method. In the case of the suppression method, it is possible to prevent memory overflow when the pointer action occurs frequently.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a jitter suppression method in a conventional smoothing circuit.

FIG. 4 is a diagram showing another example of a jitter suppression method in a conventional smoothing circuit.

[Explanation of symbols]

 1 Stuff Control Detection Section 2 Write Clock Generation Section 3 Buffer Memory 4 Tooth Missing Cumulative Distribution Section 5 PLL Circuit 11 PLL Circuit 17 Switching Section

Claims (1)

[Claims] 1. A stuff control detection unit (1) for detecting that stuff control has been performed from a byte-stuffed asynchronous data signal and generating a pointer action detection signal, and a stuff control detection unit (1) for generating the pointer action detection signal. A write clock generator (2) for generating a byte stuffing clock from a clock synchronized with the asynchronous data signal, a buffer memory (3) for writing valid data in the asynchronous data signal by the byte stuffing clock, and the byte stuffing A first PLL circuit (5) for generating a clock with a smoothed clock, and a byte stuffing clock for accumulating byte stuff values according to the pointer action detection signal and nonlinearly distributing the accumulated values in bit units. Tooth missing cumulative distribution unit 4), a second PLL circuit (11) that generates a clock obtained by smoothing the bit stuffing clock, and the first PLL circuit (11) according to the magnitude of the cumulative value in the tooth missing cumulative distribution unit (4). 5) Output clock and second
And a switching unit (17) for selecting an output clock of the PLL circuit (11), and the data of the buffer memory (3) is read as an output clock of the switching unit (17). Jitter suppression method for smoothing circuit.