JPH0685176A - Input protective circuit - Google Patents

Abstract

PURPOSE:To protect a semiconductor element from a high voltage of the outside like static electricity, by constituting the diode connection of a PMOS transistor with the power supply side when the power supply is isolated by a well, and constituting the diode connection of an NMOS transistor with the ground side when the ground system is isolated by a well. CONSTITUTION:The source and the gate of a PMOS type transistor 33 are connected with a first power supply vdd1, and the drain is connected with a second power supply vdd2, thereby constituting diode connection. In the ordinary operating state, the first power supply vdd1 and the second power supply vdd2 are kept at almost the same potential, and the PMOS type transistor 33 is cut off, so that circuit operation is not affected at all. When a high voltage is applied to an input terminal, a pulse type current flows through a transistor group 50 of an inner circuit first stage and many elements of the inner circuit via PMOS transistors 31, 33, and the increase of voltages applied to gates of the transistor group 50 is restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit in a semiconductor integrated circuit having a MOS structure.

[0002]

2. Description of the Related Art In MOS type semiconductor devices, when a high voltage is applied to the input, the gate formed by a very thin oxide film may be destroyed and may not function. Therefore, the MOS
In the case of a type semiconductor, an input / output circuit for interfacing with the outside is provided with a protection circuit for protecting the element against a high voltage from the outside.

On the other hand, in recent years, as semiconductor devices have been miniaturized, noises in power supply systems and ground systems have become a serious problem. FIG. 6 shows an example in which the noise of the output buffer changes the switching voltage (threshold value) V _th of the input buffer when the ground is one system. When the output buffer 10 drives a huge external capacitance, the external charge is instantly grounded as an Inose of the current shown in FIG.
Pour into. Therefore, the potential of the ground gnd1 instantaneously rises by the output noise ΔV, and the rise of the potential also raises the ground of the input buffer 20, so that the switching voltage (threshold value) V _{th of} the input buffer shifts and causes a malfunction. Therefore, in a high-speed element or an element designed to drive a large external load, the power supply or ground system is separated so that the noise of the output buffer does not sneak into the input buffer or the internal circuit.

FIG. 7 is a diagram showing an example of a sectional structure of a CMOS semiconductor device, and FIG. 8 is an equivalent circuit diagram of a power supply system and a ground system of a CMOS semiconductor device having the sectional structure shown in FIG. When the CMOS semiconductor circuit is formed on the P substrate as shown in FIG. 7, the power source is completely separated by the well and the ground system is gently separated via the basic resistance as shown in FIG.

FIGS. 9 and 10 show an example of an input protection circuit when the power supply and ground systems are separated as shown in FIGS. 7 and 8 ("electrostatic breakdown phenomenon of semiconductor device due to miniaturization"). Maeda S. et al. IEICE Technical Report
R90-65 CPM90-127) The input protection circuit shown in FIG. 9 and the input protection circuit shown in FIG. 10 differ only in the arrangement order of the transistor group 30 and the resistor 40 on the circuit diagram.

The internal circuit is formed by using the first power supply vdd1 and the first ground gnd1. The input protection circuit is separated from the first power supply vdd1 by, for example, a second power supply vdd2. , And the first ground gnd1 are formed using, for example, a second ground gnd2 separated by a substrate resistance. Here, the transistor group 30 of this input protection circuit is composed of a PMOS type transistor 31 and an NMOS type transistor 32, the source and gate of the PMOS transistor 31 are connected to the second power supply vdd2, and the drain of the PMOS type transistor is of NMOS type. It is connected to the drain of the transistor 32, and the source and gate of the NMOS transistor 32 are connected to the second ground gnd2. Further, these PMOS type transistor 31 and NM
The drain of the OS-type transistor 32 is connected to the input terminal directly (in the case of FIG. 9) or via the resistor 40 (in the case of FIG. 10), and directly (in the case of FIG. 10) or via the resistor 40 (in the case of FIG. 10). In the case of FIG. 9), each gate of the transistor group 50 at the first stage of the internal circuit is connected. Also P
MOS transistor 31 and NMOS transistor 3
There is a parasitic diode between each source and drain of No. 2, and this parasitic diode is also explicitly shown here.

[0007]

In order to evaluate the performance of such an input protection circuit, a test method based on the EIAJ standard as shown in FIG. 11 is adopted ("CMOS super LSI").
Design "Baifukan, supervised by Takuo Sugano, and the above-mentioned references
reference). Here, the reference pin (power supply pin or ground pin) of the device DUT under test is grounded, the capacitor is first charged with a predetermined voltage by a voltage source, and then the switch is switched to the device DUT under test with a voltage. Is applied. This test method is based on the human body model (HB
M) and machine model (MM).

FIG. 12 is a diagram showing the behavior of the circuit when the test method shown in FIG. 11 is applied to the conventional input protection circuit shown in FIG. Here, it is assumed that the ground pin is grounded as the reference pin. Power supply, vdd1, vdd
When a high voltage is applied to the input terminal when 2 is open, a pulsed current Ipul caused by this high voltage is applied.
se flows through the protection circuit in the first stage to the ground as shown in the figure, but at that time, the current flows through the NMOS transistor 32.
Since there is no place other than that, the concentration is concentrated, and the voltage increase dV due to the resistance of the NMOS transistor 32 becomes large. Then, there is a problem that the gate oxide film on the NMOS type transistor side of the transistor group 50 at the first stage of the internal circuit connected to it cannot withstand the voltage increase and is destroyed.

In view of the above problems, the present invention is an MOS type semiconductor device having a plurality of power supply or ground systems, and an input capable of protecting the semiconductor device up to a voltage higher than the conventional one against a high voltage from the outside such as static electricity. The purpose is to provide a protection circuit.

[0010]

A first input protection circuit of the present invention that achieves the above object addresses a case where a semiconductor integrated circuit having a MOS structure is formed by a process in which a power supply system is separated by wells. Is. That is, in the first input protection circuit of the present invention, each source is different from the second power supply separated by the well from the first power supply on the internal circuit side or the first ground on the internal circuit side. The drains are connected to the second ground separated by the substrate resistance, the drains are connected to each other, the drains are directly connected to the input terminal via the circuit element, and the drains are connected directly to the circuit element. In an input protection circuit including a PMOS-type transistor and an NMOS-type transistor connected to an internal circuit via one of the sources or drains, one or the other is connected to the first power supply or the second power supply, respectively. At the same time, it is characterized by including a PMOS type transistor whose gate is connected to the first power supply.

The second input protection circuit of the present invention which achieves the above object deals with a MOS integrated circuit formed by a process in which a ground system is separated by wells, and each source is It is connected to a second power source separated from the first power source on the internal circuit side by a substrate resistance, or to a first ground source separated from the first ground on the internal circuit side by a well, and each drain is mutually connected. A PM connected to the internal circuit through the drain and directly or through the circuit element to the input terminal.
In an input protection circuit including an OS transistor and an NMOS transistor, one or the other of a source and a drain is connected to the first ground or the second ground, and a gate is connected to the first ground. It is characterized by including a connected NMOS type transistor.

Here, the first input protection circuit has the features of the first input protection circuit, and
It may also have the features of the second input protection circuit. That is, in the first input protection circuit, one or the other of the source and the drain is connected to the first power supply or the second power supply, and the gate is connected to the first power supply. An NMOS transistor that includes a PMOS transistor, and has one or the other of the source and the drain connected to the first ground or the second ground and the gate connected to the first ground. You may have it.

On the contrary, the second input protection circuit may have the features of the first input protection circuit as well as the features of the second input protection circuit. That is, in the second input protection circuit, one or the other of the source and the drain is connected to the first ground or the second ground, and the gate is connected to the second ground. NMO
An NMO having an S-type transistor, wherein one or the other of the source and the drain is connected to the first ground or the second ground, and the gate is connected to the first ground.
It may include an S-type transistor.

[0014]

In the first input protection circuit of the present invention, as described above, the first power supply and the second power supply are connected in a die-auto manner by a PMOS transistor whose gate is connected to the first power supply on the internal circuit side. However, during normal operation, there is almost no potential difference between the first power supply and the second power supply, and therefore this PMOS transistor is in the cut-off state. Therefore, noise such as the output noise ΔT shown in FIG. 6 is not transmitted. On the other hand, when a high voltage is input when the ground side is grounded in the above-mentioned test method, a current flows from the second power supply to the first power supply via the diode-connected PMOS transistor, The current can flow to ground via a number of internal circuit elements connected to the first power supply, thus providing an input protection circuit that withstands higher voltages than before using the test method described above. .

In the above-mentioned test method, when the power supply side is grounded and a negative high voltage is input, the first ground and the second ground are connected to each other through the board resistance, and therefore, it is necessary to pay particular attention. Even without it, the breakdown voltage is relatively high,
As mentioned above, N connected to the diode on the ground side
When the MOS type transistor is provided, the breakdown voltage is further increased by the same action as described above.

The same applies to the second input protection circuit of the present invention. That is, in the second input protection circuit of the present invention, the first ground and the second ground are connected to the first ground on the side of the input protection circuit by the gate.
It is a diode-connected MOS transistor,
This NMOS type transistor is kept in a cut-off state in a normal operation state, and when a negative high voltage is input while the power source side is grounded in the above-mentioned test method, the second transistor on the input protection circuit side is The ground has a lower potential than the first ground on the internal circuit side, and power flows from the grounded first power supply side to the first ground side of many elements on the internal circuit side, and further the first ground side. A current flows from to the second ground side via the NMOS transistor. As described above, when the input protection circuit operates, the number of paths through which the current is separated increases, so that the voltage rise (negative voltage in this case) applied to the gate of the MOS transistor at the input stage of the internal circuit is suppressed, which is higher than in the past. It is possible to protect the gate oxide of this input stage up to the voltage. Further, in the case of the second input protection circuit of the present invention, the power supply systems are connected to each other through the base resistance, but for the same reason as in the case of the first input protection circuit described above,
A diode-connected PMOS transistor may be provided between the first power supply and the second power supply.

[0017]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of an embodiment of the input protection circuit of the present invention. Here, an embodiment corresponding to the conventional example shown in FIG. 9 is shown. Therefore, the same circuit elements as those of the conventional example shown in FIG. 9 have the same numbers and symbols as those of FIG. Numbers and symbols will be attached and only differences will be explained.

In the embodiment shown in FIG. 1, a PMOS type transistor 33 is added to the conventional example shown in FIG. This P
The source and the gate of the MOS transistor 33 are connected to the first power supply vdd1, that is, the power supply on the internal circuit side, and the drain is connected to the second power supply vdd2, that is, the power supply on the input protection circuit side. This constitutes a so-called diode connection.

FIG. 2 is a graph showing voltage-current characteristics in diode connection. When the voltage Vds is low, the current Ids is almost 0, and this transistor is in the cutoff state. As the voltage Vds is increased, the current Ids rapidly increases and becomes conductive. Although the NMOS type transistor is shown here, PM
The same applies to the OS type transistor.

In the circuit shown in FIG. 1, the first power supply vdd1 and the power supply vdd2 of I2 are maintained at substantially the same potential in the normal operation state, and therefore the PMOS transistor 33 is in the cut-off state and the circuit operation is Has no effect on. FIG. 3 is a diagram showing the behavior of the circuit when the test method shown in FIG. 11 is applied to the MOS device having the input protection circuit shown in FIG. 1, and corresponds to FIG. 12 in the conventional example. Is.

When a high voltage is applied to the input terminals when the power supplies vdd1 and vdd2 are open, a pulsed current Ipulse resulting from this high voltage flows to the internal circuit side via the PMOS transistors 31 and 33. , The internal circuit first stage transistor group 50 and many other elements forming the internal circuit. As a result, the increase in the voltage applied to the gates of the transistor group 50 is suppressed, and the transistor group 30 has a voltage higher than the conventional voltage.
The effect of protecting the gate oxide film is obtained.

FIG. 4 shows an M adopting the circuit configuration shown in FIG.
An OS device and an M that adopts the conventional circuit configuration shown in FIG.
12 is a graph showing the results of tests performed on an OS device using a machine model in which the capacitance value of the capacitance in FIG. 11 is 200 pF and the resistance value of the resistance element is 0Ω. The reference pin is the ground pin. The horizontal axis represents the applied voltage, and the vertical axis represents the number of samples that were destroyed by the applied voltage.

As shown in this graph, in the case of the circuit configuration adopted by the present invention, the withstand voltage is increased by about 100 volts as compared with the conventional one. FIG. 5 is a circuit diagram of another embodiment of the input protection circuit of the present invention. This embodiment is a particularly effective example in the case of a MOS device formed by a process in which the ground system is separated by wells.
Ground gnd1 and the second ground gnd2 on the input protection circuit side are connected via the NMOS type transistor 32, and the gate of the NMOS type transistor 34 is connected to the first ground gnd1.

The behavior of this circuit during normal operation and when a high voltage such as static electricity is applied is compared with that in the circuit shown in FIG. Since the circuit is the same as that of the circuit shown in FIG. 1 if the positive and negative signs are reversed, the description thereof is omitted here. 1 shows an example in which the PMOS type transistor 33 is arranged on the power supply side when the power supply system is separated by wells, and FIG. 5 shows the ground side on the ground side when the ground system is separated by wells. N
Although the example in which the MOS transistor 34 is arranged is shown, a PMOS transistor may be arranged in the power supply system and an NMOS transistor may be arranged in the ground system regardless of whether the well of the power supply system or the ground system is isolated. In this case, further increase in breakdown voltage is expected.

[0025]

As described above, in the input protection circuit of the present invention, when the power supplies are separated by wells, P is provided on the power supply side.
NMO is connected to the ground side when the MOS transistor is diode-connected and the ground system is separated by wells.
By connecting the S-transistor as a diode, this has no effect during normal operation, and the current pulse due to high voltage due to static electricity is bypassed or shunted, thereby keeping the effect of separating the power supply or ground. , The performance of protecting the element from high external voltage is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of an input protection circuit of the present invention.

FIG. 2 is a graph showing voltage-current characteristics in diode connection.

3 is a diagram showing the behavior of the circuit when the test method shown in FIG. 11 is applied to a MOS device including the input protection circuit shown in FIG.

FIG. 4 is a graph showing a result of a test performed on a machine model.

FIG. 5 is a circuit diagram of another embodiment of the input protection circuit of the present invention.

FIG. 6 is a diagram showing the behavior of the circuit when the number of ground systems is one.

FIG. 7 is a diagram showing an example of a cross-sectional structure of a CMOS semiconductor device.

8 is an equivalent circuit diagram of a power supply system and a ground system of a CMOS semiconductor device having the sectional structure shown in FIG.

FIG. 9 is an example of an input protection circuit when a power supply and a ground system are separated.

FIG. 10 is an example of an input protection circuit when a power supply and a ground system are separated.

FIG. 11 is a diagram showing a test method of an input protection circuit.

12 is a diagram showing the behavior of the circuit when the test method shown in FIG. 11 is applied to the conventional input protection circuit shown in FIG.

[Explanation of symbols]

 30 Transistor Group 31 PMOS Type Transistor 32 NMOS Type Transistor 33 PMOS Type Transistor 34 NMOS Type Transistor 40 Resistor 50 Internal Circuit First Stage Transistor Group

Claims (2)

[Claims] 1. Each source has a second power source separated from a first power source on the internal circuit side by a well, or a second power source isolated from a first power source on the internal circuit side by a substrate resistance. Connected to the ground, each drain is connected to each other, the drain is directly connected to the input terminal via the circuit element, and the drain is directly connected to the internal circuit via the circuit element. In the input protection circuit including the PMOS type transistor and the NMOS type transistor, one or the other of the source and the drain is connected to the first power supply or the second power supply, and the gate is the first power supply. PMO connected to power supply
An input protection circuit comprising an S-type transistor. 2. Each source has a second power supply separated from a first power supply on the internal circuit side by a substrate resistance, or a second power supply isolated from a first ground on the internal circuit side by a well. Connected to the ground, each drain is connected to each other, the drain is directly connected to the input terminal via the circuit element, and the drain is directly connected to the internal circuit via the circuit element. In the input protection circuit including the PMOS type transistor and the NMOS type transistor, one or the other of the source and the drain is connected to the first ground or the second ground, and the gate is the first ground. An input protection circuit comprising an NMOS transistor connected to the input protection circuit.