JPH0680803B2 - MIS dynamic memory cell and method of manufacturing MIS dynamic memory cell - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a method for manufacturing a current sense type MOS dynamic RAM cell.

[Prior art and its problems]

In the future, it is expected that the integration density of dynamic memory will increase more and more, but the conventional 1Tr.1 Capacitor
In the method, it is difficult to reduce the cell capacitor area due to the limitation of the leak current, and it is expected that the cell method having a current amplification function inside the memory cell has a possibility of high integration. An example of this method is K. Terada, et al “ANe
w VLSI Memory Cell Using Capacitance Coupling ", IED
M.1982. And the cross-sectional view of this memory cell structure
A diagram and an equivalent circuit are shown in FIG.

As for the structure, a CMOS structure 7-2-3-6 having a common gate is formed under the gate (8) of the switching transistor on the P-type substrate, and the p ⁺ layer (6) is used as a floating gate, and a junction (Junction) is formed under the floating gate. The FET (1-4-6) is formed. (Fig. 1) The principle is to set the word line (8) to a negative voltage and turn the PMOSFET of Q ₁ to O
Set to N and set the p ⁺ layer (6) to 0 V of the substrate potential. “0”,
Writing "1" depends on the bit line potential. p ⁺ laye
The amount of charge stored in the capacitance CNW between r and the bit line n ⁺ (Fig. 24 in Fig. 2) is changed by the bit line. When the bit line is 0V, "0" is output, and when the bit line is positive voltage, "1" is output. p ⁺ la
Written to yer (6). After the write operation, the word line voltage is returned to 0V and the p ⁺ layer is electrically floated. 0V from the positive voltage to the bit line of the cell where "1" is written
When set to, the potential of the p ⁺ layer is the capacitance CNW with the bit line.
(A negative potential is generated by 24 and the junction FET is cut off. At this time, the smaller the coupling capacitance C _G (23) between the gate (8) and the p ⁺ layer (6) is, the smaller the p ⁺ layer is. However, the junction FET cutoff is complete, but the capacitance between the gate and p ⁺ layer expands laterally during ion implantation when the p ⁺ layer is formed, and thermal annealing is performed to electrically activate the implanted impurities. Due to the thermal diffusion due to, the p ⁺ layer inevitably enters under the gate, and C _G becomes large.
In this case, even if the bit line of the cell in which "1" is written is changed from a positive voltage to 0 V, the p ⁺ layer voltage does not drop sufficiently and the junction FE
T does not cut off sufficiently, the voltage of V + (7) is transmitted to the Bit line, and "1" cannot be read sufficiently. This is a problem of the Capacitance Coupling type cell in the conventional technique.

[Object of the Invention]

The present invention was made in order to improve the cut-off characteristic of the bit line signal at the time of reading "1" of the above Capacitance Coupling type cell, and the difference between the signals at the time of reading "1" and "0" of the bit line signal. The purpose of the present invention is to provide a large capacity Couping type cell.

[Outline of Invention]

In order to increase the signal difference at the time of reading “1” and “0”, the present invention reduces the coupling capacitance C _G between the p ⁺ layer and the word line of the Capacitance Coupling type cell by using a linear shape on the sidewall of the gate electrode. Form CVD SiO ₂ and p ⁺
Ions are implanted to form a layer so that the p ⁺ layer and the gate electrode do not overlap in a self-aligned manner.

〔The invention's effect〕

According to the present invention, the coupling capacitance between the word line and the p ⁺ layer of the Capacitance Coupling type cell can be remarkably reduced, and therefore the difference between the read signals of “1” and “0” can be increased. Therefore, when the cell information is read by the sense amplifier, it is not necessary to increase the sensitivity of the sense amplifier, which enables highly sensitive detection. By enabling highly sensitive detection, the cell information detection speed can be increased, access time can be shortened, and a high-performance dynamic RAM can be realized.

Example of Invention

An embodiment of the present invention will be described below in the order of the manufacturing method step chart and FIG.

5Ω ・ cm to 10Ω ・ cm p type (100) substrate (11) with S on the entire surface
i After forming a thermal oxide film (12) for surface protection, Si ₃ N ₄ (13) is deposited on the entire surface and the area outside the element formation region is removed by etching. After this, B ⁺ for channel stop is implanted in the element isolation region. (14) (Fig. 3 (a))
Next, thermal oxidation is performed using Si ₃ N ₄ as a mask to form a thick thermal oxide film (15) in the element isolation region. After that, a part of the element formation region is covered with a resist (16), and (b) p ⁺ is implanted using this as a mask to form a Pwell (17). After that, the resist is removed by etching, and the gate electrode (18) to be the word line is formed by patterning, and CVDSiO ₂ is formed on the entire surface.
(19) is deposited. (FIG. 3 (c)) Next, CVD SiO ₂ is etched by directional ion etching, and the thick deposition of CVD SiO _{2 on} the side wall of the gate electrode is used to
The CVD SiO ₂ (19) is left only on the side wall of the gate electrode. This C
B ⁺ is implanted using VDSiO ₂ and the gate electrode as a mask to form a p ⁺ layer (20). (Fig. 3 (d)) At this time,
CVDS so that the p ⁺ layer does not overlap the gate
Adjusts the iO ₂ thickness and the acceleration energy of B ⁺ implantation.

Next, a resist (21) is patterned so as to partially cover the n well side of the gate electrode, and using this as a mask, p ⁺ is implanted to form an n ⁺ layer (22). (Fig. 3 (e)) Next, the resist (21) is removed by etching, and the entire surface is covered with CV.
N ⁺ Diffusion layer (27) that will become the bit line by depositing DSiO ₂ (26)
A hole is opened in the upper CVD SiO ₂ , Al is deposited on the entire surface, and patterned to form a metal wiring (26) of a bit line.

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional Capacitance Coupling type cell, FIG. 2 is an equivalent circuit diagram thereof, and FIG.
(F) is a process sectional view of a Capacitance Coupling type cell of the present invention.

Claims (2)

[Claims] 1. A gate having one bit line and one word line connected to one word line shares the gates of two p-channel and n-channel MISFETs, and the MI is provided.
Only the source of the SFET is made to float, and this floating source doubles as the gate of the junction FET, and uses the capacitive coupling between the bit line and the floating gate for writing "1" and "0" information. In a current read type memory cell in which electric charge is stored in a floating gate and a junction FET is turned on and off, an insulating film is provided on a sidewall of the word line, and the sidewall insulating film and the word line serve as a mask when forming a floating source. An MIS dynamic memory cell, wherein the end of the floating source and the end of the gate are formed in a self-aligned manner. 2. The MI having one bit line and one word line, and the gate connected to the one word line shares the gates of two p-channel and n-channel MISFETs.
Only the source of the SFET is made to float, and this floating source doubles as the gate of the junction FET, and uses the capacitive coupling between the bit line and the floating gate for writing "1" and "0" information. In a current-reading type memory cell in which electric charge is stored in a floating gate and a junction FET is turned on and off, a step of depositing an insulating film on the entire surface after forming a word line, and directional ion etching of the insulating film on the entire surface There is a step of leaving the insulating film in a line shape only on the side wall of the line, and a step of implanting ions of the floating source using the gate and the insulating film of the side wall as a mask to minimize the overlapping portion of the floating source and the gate. A method for manufacturing an MIS dynamic memory cell characterized by the above.