JPH065901B2 - Image quality improvement device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an image quality improving device for clarifying the contour of an image and improving the sharpness of the image (so-called image sharpness) in a television receiver, for example. .

[Technical background of the invention]

Generally, a television receiver is provided with an image quality improving device for clarifying the outline of an image and improving the sharpness of the image. Such image quality improvement is performed by increasing the gain of the high frequency component of the video signal. The frequency of this high frequency component is usually about 3 MHz. Therefore, the frequency characteristic of the gain after the image quality improving operation is as shown by the solid line in FIG. In the figure, the characteristic indicated by the broken line is the characteristic before the image quality improving operation is performed.

2 and 3 show a conventional image quality improving device. In the example shown in FIG. 2, the image quality is adjusted by changing the peaking of the image quality improving circuit 3 by the image quality adjusting volume 1 and the peaking circuit 2. In the example shown in FIG. 3, the image quality is adjusted by changing the characteristics of the image quality improvement circuit 4, for example, the CCD transversal filter, by the direct-current control voltage V _{c that} is introduced from the power supply V _cc through the image quality adjustment volume 1. Is.

[Problems of background technology]

However, in the conventional image quality improving device, when the high frequency component of the video signal is amplified to improve the image quality, the noise in the video signal is also amplified at the same time, resulting in a noisy image. It was

[Object of the Invention]

The present invention has been made to address the above situation, and when the sharpness of an image is increased, it can be reduced so as not to be affected by noise components, and this reduction operation can reduce fine pattern components. An object of the present invention is to provide an image quality improving device that is not lost.

[Outline of Invention]

According to the present invention, a video signal whose noise component is reduced by removing a pulse-shaped signal having a frequency near the frequency range of the noise component and a video signal which has not been subjected to such noise reduction operation are displayed on the time axis. Add in the matched state,
By using the added output as a video signal output, it is possible to achieve both reduction of noise components and preservation of fine picture components. In such a configuration, the sharpness of the image is controlled. The addition ratio can be controlled according to the operation of the image quality adjustment operator.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a circuit diagram showing the configuration of one embodiment. In the figure, the video signal applied to the input terminal 11 is input from the transversal filter 12. The frequency characteristic of the output of the transversal filter 12 is controlled by the DC control voltage V _c from the image quality adjusting volume 13. That is, when the control voltage V _c from the image quality adjustment volume 13 increases (approaches the voltage of the power supply V _cc), is adapted to increase the gain of the high frequency component of the video signal. The output signal of the transversal filter 12 is input to the delay element 14 having a delay time of 1H (1 horizontal time). The output signal of the delay element 14 is input to the delay element 15. The delay time of this delay element 15 is also set to 1H.

The input / output signal of the delay element 14 is input to the AND circuit 16, the input / output signal of the delay element 15 is input to the AND circuit 17, and the input signal of the delay element 14 and the output signal of the delay element 15 are connected to the AND circuit 18. Has been entered in. AND circuit 1
The output signals of 6, 17, and 18 are input to the OR circuit 19.

The output signal of the OR circuit 19 is supplied to the base of the transistor Q ₁₂ as one input of the adding circuit 20. The output signal of the transversal filter 12 is applied to the other input of the adder circuit 20. In this case, the adder circuit 2
In order to correct the time axis of both inputs of 0, the output signal of the transversal filter 12 has a delay element 2 of delay time 1H.
1 to the base of transistor Q ₁₁ .

The output signal of the OR circuit 19 is taken out from the collector of the transistor Q ₁₆ , the output signal of the delay element 21 is taken out from the collector of the transistor Q ₁₄ , and the transistors Q ₁₆ and Q _{16 are} taken.
It is added at the common connection point of the ₁₄ collectors and is led to the output terminal 23 via the inverting circuit 22.

The common connection point of the base of the transistor Q _13, Q ₁₆ is supplied with the control voltage V _c from the image quality adjustment trimmer 13, the amplification gain of the transistor _{Q 13, Q 14, Q 15} , Q 16 according to the level of the control voltage is controlled It is supposed to be done. In other words, the addition ratio of the adder circuit 20 is controlled by the control voltage V _c . It should be noted that in the adder circuit 20, R is a resistor.

The operation of the above configuration will be described.

The circuit including the delay elements 14 and 15, the logical product circuits 16, 17, and 18 and the logical sum circuit 19 is a noise having a filter characteristic for removing a pulse noise component from the video signal output from the transversal filter 12. It forms a mitigation circuit. The noise reduction operation of this noise reduction circuit will be described later.

The video signal X _A whose noise component has been reduced by this noise reduction circuit is added to the video signal X _{B which} is supplied from the delay element 21 and whose noise component has not been removed.

By the way, since the noise reduction circuit does not discriminate and remove the noise component but removes a pulsed signal having a high possibility of a noise component, a fine pattern component may also be removed. . However, both signals are averaged by adding the output video signal X _A of this noise reduction circuit and the video signal X _B that has not been subjected to the noise component reduction operation in the addition circuit 20. Therefore, the adder circuit 2
When viewed at the output terminal of 0, the pulse-like signal that is removed by the noise reduction circuit is not lost, and the level is simply reduced. Therefore, when the pulsed signal is a noise component, the reproduced image is not significantly deteriorated by the noise component, and when it is a fine pattern component, the fine pattern may be lost from the reproduced image. Absent. That is, it is possible to reduce noise components and reproduce fine patterns at the same time.

Next, the relationship with the image quality improving operation by the image quality adjusting volume 13 will be described. When the control voltage V _c from the image quality adjustment volume becomes higher, the gain of the high frequency component of the video signal output from the transversal filter 12 increases. At this time, the gain of the noise component also increases at the same time.

On the other hand, as the control voltage V _c increases, the adder circuit 20
The amplification gains of the transistors Q ₁₃ and Q ₁₆ increase, and the amplification gains of the transistors Q ₁₄ and Q ₁₅ decrease. Therefore, in the addition circuit 20, the addition ratio of the video signal X _A that has been subjected to the noise reduction operation is high, and the addition ratio of the video signal X _B that has not been subjected to the noise reduction operation is low. As a result, the output video signal X of the adder circuit 20 is strongly influenced by the video signal X _A ,
Noise components can be reduced. Therefore, even if the noise component level increases due to the image quality improving operation, it is not directly supplied to the video output circuit (not shown), so that the reproduced image is not significantly deteriorated by the noise component. . And in this case,
Since the fine pattern component is saved by the averaging process of the adding circuit 20, the fine pattern is not lost from the reproduced image.

When the control voltage V _c is low, that is, when the image is reproduced with poor sharpness, the amplification gains of the transistors Q ₁₃ and Q ₁₆ decrease and the amplification gains of the transistors Q ₁₄ and Q ₁₅ increase.
Therefore, the addition ratio of the video signal X _B becomes high and the addition ratio of the video signal X _A becomes low, and the output video signal X of the adder circuit 20 is strongly affected by the video signal X _B that has not been subjected to the noise reduction operation. , The influence of the noise component on the reproduced image becomes large. However, there is usually no problem because the image is not reproduced with the sharpness being reduced.

In the case of normal reproduction in which the sharpness of the image is not emphasized (improved image quality) or deteriorated (the image quality adjustment volume 13 is set to the central position), noise is generated by the averaging process of the adding circuit 20 as described above. The reduction of the component and the reduction of the fine pattern component are well balanced, the influence of the noise component is small, and it is possible to reproduce the image without losing the fine pattern.

In the above description, the case where the addition ratio is controlled by the control voltage V _c for adjusting the image quality has been described.
As shown in FIG.
It is also possible to provide a variable resistor R _V that works together with the variable resistor 3 and control it by changing the resistance value of the resistor R _V. In the illustrated example, by changing the gain of only the image signal X _B, shows the case of changing the addition rate. That is, transistor Q ₁₁
The video signal X _B output from the emitter of the above is passed through the variable resistor R _V to control the gain, and this is added to the video signal X _A given from the emitter side of the transistor Q _12. ing.

In addition, in FIG. 5, the case where the image quality is adjusted by the image quality amplification circuit 25 and the peaking circuit 26 is shown as a representative, but it is needless to say that it may be applied to the device shown in FIG.

Even in the case of the device shown in FIG. 5, if the output of the slider of the image quality adjusting volume 13 is regarded as a control signal, the output of the adder circuit 20 shown in FIG. The ratio may be controlled.

Here, the operation of the noise reduction circuit described above will be described.

FIG. 6 is a waveform diagram showing an example of a video signal waveform, FIG. 7 is a waveform diagram showing an example of a step signal waveform, and FIG. 8 is an operation explanatory diagram for realizing the noise reduction circuit according to the present invention.

In a television transmission / reception system, the gray level of pixels is converted into a temporally continuous electric signal by scanning the image on the image sending side, and the receiver side assembles and scans in synchronization with the resolution scanning of the image on the image sending side. By doing so, a two-dimensional image is reproduced.

FIG. 6 shows an example of a video signal converted into an electric signal.
FIG. 6 (a) shows a signal waveform in which the video signal has a low level and thus rises to a high level, and then falls from a high level to a low level again. Note that t0 on the horizontal axis
t5 shows the change over time, and is shown at regular intervals.

FIG. 6 (b) shows a signal waveform on which pulse-like noise is superimposed. Rising noise N1 occurs between times t1 and t2,
An example in which falling noise N2 occurs between times t3 and t4 is shown.

As can be seen from FIG. 6 (b), the level of pulse noise changes suddenly with respect to the original signal within a short time. Therefore, a certain time width (T1) is set and the signal within that time is set. When the level suddenly changes, it can be determined that noise has occurred.

FIG. 7 shows a change in the signal level at a certain time (T1), which is shown by dividing the signal level at equal intervals (τ). The signal (a) shows a state where the video signal rises from a low level to a high level, and the signal (b) shows a state where the video signal falls from a high level to a low level. Signals (c) and (d) respectively show the case where the rising noise N1 and the falling noise N2 occur within the time width (T1).

In such a signal, when a certain time (i) is used as a reference, the signal levels at the time (i-1) selected by (τ) and the time (i + 1) sent by (τ) are compared with each other. In the case of the original video signal, the signal level of at least one of time (i-1) and time (i + 1) and the signal level of time (i) are the same level, whereas in the case of pulse noise, (I-1) and time (i + 1)
And the signal level at time (i) are different. Therefore, before and after the time (i) (i-1, i
By comparing the signal level of +1),
It is possible to determine whether it is pulse noise.

For example, if signals at three points at respective times i-1, i, i + 1 are represented by logical values "1" and "0", the signal of FIG. 7 (a) has a low level "0" at time i-1. , Time i and i + 1 are “1”, respectively, and can be expressed as 0, 1, 1. Similarly, the signal in FIG. 7B can be expressed as 1, 0, 0. Also,
The signal of FIG. 7 (c) is 0, since the time i is high level "1" and the times i-1 and i + 1 are "0" respectively.
It can be expressed as 1,0. Similarly, the signal in FIG.
It can be expressed as 0, 1.

In this way, if the signal level at the reference intermediate time (i) and at least one of the signal levels before and after it are the same (0, 1, 1, 1, 1, 0, etc.), it is determined as the original signal. However, when the signal level before and after the signal level at the intermediate time (i) is different (0, 1, 0 or 1, 0, 1)
Can be discriminated as pulse noise.

Assuming the signal levels at these three points, signal patterns P _{1 to} P ₈ as shown in Table 1 can be considered. In Table 1, the pulse noise patterns are P ₇ and P ₈ , and if such signal patterns P ₇ and P ₈ are removed, most of the noise component can be removed without deterioration of the image.

Therefore, when P is obtained from the video signal at an appropriate time τ and the pulse signals are P ₇ and P ₈ in Table 1, the pulse signals are removed to reduce noise components without deterioration of the image. it can.

For example, when the noise signal shown in FIG. 8 (b) is additively mixed with the video signal shown in FIG. 8 (a), FIG.
The signal waveform is as shown in, and P ₇ of Table 1 of this signal,
When passed through a filter to block P _8, the output has a waveform as shown in Figure No. 8 (d), so that the noise is reduced. At this time, rising edges and falling edges P _{3 to} P ₆ of the step signal are not blocked, so that the edge portion is not blurred.

Next, a specific circuit configuration of the noise reduction circuit that blocks P ₇ and P ₈ will be described.

In order to prevent P ₇ and P ₈ , the signal level “1” at time (i) is rewritten to “0” for P ₇ , and 0, 0,
0 it is sufficient, also the signal level "0" at time (i) for the _{P 8} "1" may be rewritten as 1,1,1 to.

According to the present invention as this method, time (i-1), (i),
Each signal level of (i + 1) is set to p (i-1), p (i),
When p (i + 1), each signal level p (i-1),
By taking the majority decision of p (i) and p (i + 1), P
₇ and P ₈ are blocked.

FIG. 4 and FIG. 5 are based on the above-mentioned principle, and the noise reduction circuit composed of the delay elements 14 and 15, the logical product circuits 16, 17 and 18, and the logical sum circuit 19 has p (i-1), p
(I), by taking the majority of p (i + 1), P ₇ ,
I try to block P ₈ .

As the logical product circuits 16, 17 and 18, there is a circuit as shown in FIG. The circuit shown has two PNP transistors Q ₂₁ and Q ₂₂ having a common emitter, and the common emitter is connected to a DC power supply V _CC via a resistor R. The input A is applied to the bases of the transistors Q ₂₁ and Q _22. , B are added and the output C is taken out from the common emitter. This truth table is as shown in Table 2, and the relationship of C = A × B is established.

FIG. 10 is a circuit showing an example of the OR circuit 19,
One of the emitter of the transistor NPN transistors Q _23, Q _24, Q ₂₅ and the common, grounded the common emitter through the resistor R, is constructed by connecting the collectors to the DC power supply V _CC, transistor Q _23, Q ₂₄ , Q ₂₅ base inputs A, B,
C is added to take out the output D from the common emitter. This truth table is as shown in Table 3, where D = A
The relationship of + B + C is established.

In such a configuration, in the circuit shown in FIGS. 4 and 5, the signal p (i-1) input to the delay element 14 is input.
And when the signal p (i) output from the delay element 14 and the signal p (i + 1) output from the delay element 15 are P ₇ = {0,1,1} shown in Table 1, AND The output of the circuit 16 is “0”, the output of the AND circuit 17 is “0”,
Since the output of the logical product circuit 18 is "0", the output of the logical sum circuit 19 is "0" and the signal p (i) of the output XA of the logical sum circuit 19 is "0". Therefore, P ₇
Becomes {0, 0, 0} after passing through the circuit, and the protruding portion of the pulse signal is removed as a noise component. Also the fourth
In FIG. 5 and FIG. 5, p (i-1), p (i), p (i
+1) is P ₈ {1, 0, 1} shown in Table 1, the output of the logical product circuit 16 becomes “0”, the output of the logical product circuit 17 becomes “0”, and the logical product circuit Since the output of 18 is "1", the output of the OR circuit 19 becomes "1", and the signal p (i) of the output XA of the OR circuit 19 is "1".
Becomes Therefore, P ₈ is P ₈ {1,
1, 1}, and the protruding portion of the pulse signal is removed as a noise component. The Figure 4, the rise of the step-shaped signal in Figure 5, the _P 3 to P ₆ falling after circuit also passes p (i) becomes a same level of the _signal, P 3 to P ₆ is outputted Therefore, the edge does not blur.

The noise reduction circuit can also be configured as shown in FIG. The noise reduction circuit shown in FIG. 11 is obtained by replacing each logical product circuit of the noise reduction circuits shown in FIGS. 4 and 5 with OR circuits 27, 28 and 29.

For the circuit shown in FIG. 11, p (i-1), p
(I) and p (i + 1) are P ₇ {0, 1, shown in Table 1.
0}, the output of the OR circuit 27 is “1”, the output of the OR circuit 28 is “1”, and the output of the OR circuit 29 is “0”. Therefore, the output of the AND circuit 30 is The signal p (i) output from the AND circuit 30 becomes "0". Therefore, P ₇ is {0,0,0} after passing through the circuit.
Then, the protruding portion of the pulsed signal is removed as a noise component. Further, in FIG. 11, p (i-1), p
(I) and p (i + 1) are P ₈ = {1, 0, shown in Table 1
1}, the output of the logical sum circuit 27 is “1”, the output of the logical sum circuit 28 is “1”, and the output of the logical sum circuit 29 is “1”. Signal p
(I) becomes "1". Therefore, P ₈ becomes {0, 1, 0} = P ₂ after passing through the circuit, and the protruding portion of the pulse signal is removed as a noise component. Further, in FIG. 11, P _{3 to} P ₆ of rising and falling of the step-like signal are shown.
For, because after the circuit also passes p (i) is output P ₃ to P ₆ become equal level signal, never edge portion blurs.

In the above description, the noise reduction circuit is applied in the vertical direction in the configuration of the television circuit, but a similar circuit is configured in the horizontal direction or both the vertical and horizontal directions to reduce noise. You may

〔The invention's effect〕

As is apparent from the above description, the present invention can reduce the image sharpness even if the image sharpness is increased so as not to be influenced by the noise component. It is possible to provide an image quality improving device that is not lost.

[Brief description of drawings]

FIG. 1 is a frequency characteristic diagram of a gain for explaining an image quality improving operation, FIG. 2 is a circuit diagram showing an example of a conventional image quality improving apparatus, FIG. 3 is a circuit diagram showing the other example, and FIG. 5 is a circuit diagram showing an embodiment of an image quality improving device according to the present invention;
6 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a waveform diagram showing an example of a video signal waveform, FIG. 7 is an explanatory diagram showing step signal waveforms and samples thereof, and FIG. 8 is FIG. 5 is a diagram for explaining the operation of the noise reduction circuit in FIG. 5, FIG. 9 is a circuit diagram showing an example of a logical product circuit, FIG. 10 is a circuit diagram showing an example of a logical sum circuit, and FIG. It is a circuit diagram which shows the other example of a noise reduction circuit. 11 ... Input terminal, 12 ... Transversal filter, 1
3 ... Image quality adjusting volume, 14, 15, 21 ... Delay element, 16, 17, 18, 30 ... AND circuit, 19, 2
7, 28, 29 ... OR circuit, 20 ... Adder circuit, 22 ...
Inversion circuit, 23 ... Output terminal, 25 ... Image quality amplification circuit, 26
… Peaking circuit.

Claims (3)

[Claims] 1. An image quality improving means having an image quality adjusting operator, wherein the gain of a high frequency component of a video signal in a video signal transmission path can be controlled by operating the operator, and the image quality improving means. The input video signal from is input as a first signal, a second signal obtained by delaying the first signal by a first time, and a third signal obtained by further delaying the second signal by a first time. When the first means for outputting a signal and the first, second, and third signals sequentially shifted in time are supplied, and the second signal level is different from the first and third signal levels, Noise reducing means including logic means for outputting a signal from which pulse noise has been removed by bringing the second signal level closer to the first and third signal levels, and an output signal of the noise reducing means and the above-mentioned The time axis coincides with the output video signal from the image quality improving means. Added in the state, it takes out the added output as a video signal output, the image quality improving apparatus which addition rate of both the sum signal according to the operation of the image quality adjusting operator has and a controllable addition means. 2. The addition means is configured such that a level thereof changes in accordance with an operation of the image quality adjustment operator, and the addition ratio is controlled by a control signal for controlling a gain of a high frequency component of the video signal. The image quality improving apparatus according to claim 1, wherein the image quality improving apparatus is provided. 3. The adding means has a variable resistor whose resistance value changes in association with the operation of the image quality adjusting operator, and the addition ratio is controlled by the change of the resistance value of the variable resistor. The image quality improving apparatus according to claim 1, wherein the image quality improving apparatus is configured as follows.