JPH0654786B2 - Heterojunction semiconductor device - Google Patents

Description

The present invention relates to a heterojunction semiconductor device, and more particularly to InP / A
The present invention relates to a semiconductor device using an GaAsSb-based heterojunction.

(Prior art and its problems) The junction (heterojunction) of two different semiconductors has the function of forming an electron storage layer or confining carriers on the side of the conduction band having a low hetero interface due to the discontinuity of the bottom of the conduction band. It is used in high-speed devices and semiconductor lasers. The characteristics of the heterojunction differ significantly depending on the energy band structure (energy band gap, electron affinity) of the two semiconductors to be joined.

A typical heterojunction conventionally used for high-speed devices is a GaAs / AlGaAs system, which provides higher speed operation than GaAs MESFETs, but carriers in the GaAs of the operating layer are from the Γ valley (main band) to the L valley (subband). 3KV because it easily transitions to the band)
There was a problem in realizing ballistic devices and high-mobility active devices because valley scattering with negative differential mobility occurs in an electric field of / cm or more.

(Problems to be Solved by the Invention) Accordingly, the object of the present invention is to provide a GaAs / AlGaAs system and InGaAs.
An object of the present invention is to provide a high-speed device that solves the problems of the heterojunction-based device.
It is solved by a semiconductor device using a heterojunction of Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52).

(Means for Solving Problems) The present invention uses InP instead of GaAs. As shown in Fig. 2, the energy band structures of GaAs and InP are similar, but I
The ΔE _ΓL of nP is 0.53 eV, which is considerably larger than the 0.31 eV of GaAs. From this fact, the threshold electric field of InP where negative resistance appears is about three times larger than that of GaAs. Further, as shown in FIG. 3, it can be seen that the dependence of the electron velocity on the electric field strength is larger in InP than in GaAs in terms of peak electron velocity. In order to use InP as an operating layer, that is, a layer in which carriers actually travel, the other semiconductor that joins with InP has an electron affinity smaller than InP but a band gap larger than InP and lattice-matched to InP. Must.

Quaternary mixed crystal according to the present invention Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.5
2) is a material that satisfies these conditions.

(Examples) Specific examples of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a sectional structure of an embodiment of a modulation-doped Schottky gate field effect transistor (MESFET) according to the present invention. In FIG. 1, on a semi-insulating InP substrate 11, an undoped InP layer 12, 0-200 Å undoped Al _x Ga _1-x As.
ySb _1-y (y = 0.044x + 0.52) (x≈0.48) layer 13, 1 × 10 ¹⁸¹ / cm ³ n ⁺ type Al _x Ga of Si doped with a thickness of 500 to 1000 Å
_{The 1-x} AsySb _1-y (y = 0.044x + 0.52) layer 14 is sequentially grown by, for example, a molecular beam epitaxial method, and the n ⁺ -type Al _x Ga _1-x
Al Schottky gate electrode 15 on the AsySb _1-y layer 14 and AuGeNi ohmic electrodes 16 on both sides of the gate electrode 15;
7 is provided. As shown in Fig. 4, InP and A
Accumulation of electrons occurs on the InP side of the heterointerface due to the discontinuity at the bottom of the conduction band with l _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52). That is, since nP has a large electron affinity, n ⁺ -type Al _x Ga
Electrons supplied by the donor in the _1-x AsySb _1-y (y = 0.044x + 0.52) layer are attracted to the InP side to form an electron storage layer.

This electron storage layer contributes to the electrical conduction between the source and the drain, but since the InP layer is not doped with impurities, the ionized impurity scattering is reduced, especially at low temperatures where the ionized impurity scattering becomes dominant. The effect is large and high electron mobility can be obtained. The same principle as this, that is, as a FET in which a doped region in which carriers are generated and an undoped region in which carriers actually move around are spatially separated,
Those using a GaAs / AlGaAs heterojunction are known.
However, in the undoped GaAs operating layer, a negative differential mobility appears because the carriers transit from the Γ valley having a small effective mass to the L valley having a large effective mass. In _0.52 Al _0.48
As / In _0.53 Ga _0.47 As FETs using a hetero interface have been recently proposed, but in InGaAs, the threshold electric field where negative resistance appears as in GaAs is as low as 3 to 4 KV / cm, and low electric field mobility is obtained. Features cannot be used effectively at high electric fields. Also,
In _0.53 Ga _0.47 As The influence of alloy confusion in mixed crystals is also problematic for device application. In the FET according to the present invention, InP is used as the operating layer.
Since there is no problem of alloy confusion due to the use of InP, InP has a higher threshold electric field and a higher peak electron velocity than GaAs as described above, so that the applied voltage can be high and high output and high speed operation are possible. .

FIG. 5 shows a sectional structure of an embodiment of the real space transition type semiconductor device according to the present invention. In FIG. 5, semi-insulating InP
Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52) layer 22 on the substrate 21
And InP layer 23 are alternately grown. In this embodiment, a double-heterojunction is repeated to form a multi-layered structure, but a single heterojunction single-layered structure may be used. 24, 2
Reference numeral 5 is an ohmic electrode provided substantially perpendicular to the hetero interface. Similar to the above, an electron storage layer is formed on the InP side of each hetero interface. When an electric field is applied between the ohmic electrodes 24 and 25, the electrons in InP are accelerated and become hot electrons, but before the transition to the upper valley (L valley) in InP, Al _x
Scattered in Ga _1-x AsySb _1-y layer. Since the mobility of electrons in Al _x Ga _1-x AsySb _1-y is smaller than that in InP, negative differential resistance occurs. Since the transition time of electrons is determined by the lateral length, it can be expected to operate at a higher frequency than the Gunn diode. Conventionally, as this type of semiconductor element, one using a GaAs-AlGaAs hetero interface is known. However, in GaAs, since the energy difference ΔE _ΓL between the Γ valley and the L valley is relatively small at 0.31 eV, hot electrons are likely to transit to the L valley before being scattered in Al _x Ga _1-x As. Therefore, even if a negative differential resistance is obtained, it is due to the Gunn effect, and it is difficult to realize the phenomenon of negative differential resistance due to pure real space transition. In comparison to this, InP / Al _x Ga _1-x AsySb according to the present invention
For _{1-y (y = 0.044x +} 0.52) InP of Delta] E _GanmaL than those using a heterojunction is as large as 0.53 eV, before hot electrons in the InP is scattered in _{Al x Ga 1-x AsySb 1} -y The phenomenon of transition to the L valley is unlikely to occur, and a negative differential resistance due to pure real space transition can be obtained at a high electric field. The undoped InP layer 23 and the n ⁺ -type Al _x Ga _1-x AsySb were formed by the modulation doping method.
_It may be formed on the _1-y (y = 0.044x + 0.52) layer 22 to increase the electron mobility in InP.

FIG. 6 shows an embodiment of the bipolar heterojunction transistor according to the present invention. In FIG. 6, a 0.5 μm thick n ⁻ -type InP collector layer (1 × 10 ¹⁶ ₁ / cm ³ ) 32, 500 Å-thick on an n ⁺ -type InP substrate (n = 2 × 10 ¹⁸ ₁ / cm ³ ). p ⁺ type (1
× 10 ¹⁹ ₁ / cm ³ ) InP base layer 33, 0.2 μm thick n-type (2
× 10 ¹⁷ ₁ / cm ³ ) Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52) emitter layer 34, 0.2 μm thick n ⁺ type (1 × 10 ¹⁹ ₁ / cm ³ ) InP cap layer It is a structure provided with 35. The transistor of this structure has advantages that a large current density can be obtained in the base and collector operating layers, gm is large, fanout dependency is small, and operating amplitude is small. Further, if the thickness of the base layer can be reduced to sub-micron, a ballistic operation or an electron velocity overshoot effect is possible.

In the conventionally known GaAs / Al _x Ga _1-x As based bipolar heterojunction transistor, since GaAs is used for the base layer, the energy difference ΔE between the Γ valley and the L valley is as described above.
_ΓL is relatively small, and inter-band phonon scattering is likely to occur. On the other hand, since InP is used as the operation layer in the transistor according to the present invention and ΔE _ΓL is large, a varistic operation or an electron velocity overshoot operation is likely to occur without interband phonon scattering in the base region. Therefore, an ultra-high speed transistor can be realized.

(Effects of the Invention) As described above, InP / Al _x Ga _1-x AsySb _1-y (y
= 0.044x + 0.52) Various devices using heterojunction
Since the operation speed is higher than that of conventional devices, it is currently FE
It can be used in all fields where T, IC, Gunn diode, etc. are used, and its industrial utility value is extremely large, especially in fields requiring high-speed processing, such as computer CP.
Expected to be used in U, memory, image processing, etc. Also InP
Since a high threshold electric field is used, a high operating voltage can be obtained, and the heterojunction of the present invention can be applied as a high output microdevice.

[Brief description of drawings]

FIG. 1 shows InP / Al _x Ga _1-x AsySb _1-y (y = 0.0 according to the present invention.
FIG. 4 is a cross-sectional view of a modulation-doped field effect transistor using an interface of 44x + 0.52). 2 (a) and 2 (b) are energy band structure diagrams of GaAs and InP, respectively. FIG. 3 is a diagram showing the electric field strength dependence of the electron velocity of GaAs and InP. FIG. 4 is an energy band diagram at the InP / Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52) hetero interface. FIG. 5 shows InP / Al _x Ga _1-x AsySb _1-y (y = 0.0 according to the present invention.
44x + 0.52) is a cross-sectional structural diagram of a real-space transition type semiconductor device using a hetero interface. Figure 6 shows InP for the base layer and Al _x Ga _1-x AsySb for the emitter layer.
FIG. 3 is a cross-sectional structural diagram of a bipolar heterojunction transistor according to the present invention using _1-y (y = 0.044x + 0.52). 11 is a semi-insulating InP substrate 12 is an undoped InP layer 13 is an undoped Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52) layer of 50 Å to 100 Å 14 is Si-doped of 500 Å to 1000 Å (1 x 10 ¹⁸ ₁ / c
m ³ ) n ⁺ type Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52) layer 15 is an Al gate electrode 16 and 17, AuGeNi ohmic electrode 21 is a semi-insulating InP substrate 22 , Al _x Ga _1-x AsySb _1-y (y = 0.044x + 0.52) layer 23 is an InP layer 24, 25 is an ohmic electrode 31 is an n ⁺ type InP substrate (n = 2 × 10 ¹⁸ ₁ / cm 2 ³ ) 32 is a 0.5 μm thick n-type InP collector layer (1 × 10 ¹⁶ ₁ / c
m ³ ) 33 is a 500Å thick P ⁺ type InP base layer (1 × 10 ¹⁹ ₁ / cm ³ ) 34 is a 0.2 μm thick n-type Al _x Ga _1-x AsySb _1-y (y = 0.044x +
0.52) emitter layer (2 × 10 ¹⁷ ₁ / cm ³ ) 35 is a 0.2 μm thick n ⁺ type InP cap layer (1 × 10 ¹⁹ ₁ / c ³ ).
m ³ )

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/73 29/812

Claims (4)

[Claims] 1. A InP and _{Al x Ga 1-x As y} Sb 1-y (y
= 0.044x + 0.52) and a semiconductor device using a heterojunction. 2. Undoped InP on a semi-insulating InP substrate
A layer, on said InP layer n ⁺ -type _{Al x Ga 1-x As y} Sb 1-y
(Y = 0.044x + 0.52) layer, and ohmic electrodes for a source and a drain are respectively provided in two separated regions of the n ⁺ -type Al _x Ga _1-x As _y Sb _1-y layer,
A field effect transistor in which a Schottky electrode for a gate is provided between these electrodes. 3. Al _x Ga _1-x A on a semi-insulating InP substrate.
_{s y Sb 1-y (y} = 0.044x + 0.52) and InP
A semiconductor device having a single or multiple stacked layers of and ohmic electrodes provided on both side surfaces of the stacked layers. 4. An n ⁻ -type InP collector layer, a p ⁺ -type InP base layer, and an n-type Al _x G on the n ⁺ -type InP substrate.
A bipolar heterojunction transistor comprising an a _1-x As _y Sb _1-y (y = 0.044x + 0.52) emitter layer.