JPH0653809A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent power consumption from being increased by preventing the generation of a current path from an output terminal to a power supply terminal even when an integrated circuit with high power supply voltage and a bus wire are used in common. CONSTITUTION:A serial circuit consisting of a p-channel MOSFET 101, a depression type n-channel MOSFET 102a and an n-channel MOSFET 103 is connected between a power supply VDD and ground VSS, and even when voltage more than the VDD is impressed from an output terminal T, the MOSFET 102a is led into a non-conductive state by means of a back gate bias effect or the like. When the drain potential of the MOSFET 101 is suppressed less than about VDD, a parasitic diode between the drain of the MOSFET 101 and an n-type well can be prevented from being biased in the forward direction and a current path from the output terminal 0 to the power supply VDD can be interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit using a MOSFET, and more particularly to a three-state output circuit.

[0002]

2. Description of the Related Art With the progress of fine processing technology in recent years, MO
In order to ensure the reliability of SFET, the power supply voltage of semiconductor devices is being lowered. On the other hand, due to differences in the timing of semiconductor device development, the number of situations in which systems are configured using chips with different power supply voltages is increasing.

A conventional CMOS output circuit is shown in FIG.
As shown in (a), an N-type impurity diffusion layer 504 is formed as a source / drain on the surface of a P-type well 505 provided on the surface of a P-type substrate 506, and a gate insulating film made of a silicon oxide film is interposed. By providing a polysilicon gate electrode 503 to enhance the N channel MOS
An enhancement type N-channel MOSFET is formed by forming a P-type impurity diffusion layer 502 as a source / drain on the surface of the N well 501 and further providing a polysilicon gate electrode 503 via a gate insulating film made of a silicon oxide film. The source of the N-channel MOSFET is connected to the P-type well 505 by a metal wiring 507 containing aluminum as a main component and is also connected to a power supply terminal VSS which supplies 0 volt.
Drain of channel MOSFET and P-channel MOSF
The drain of ET is connected to the output terminal T, the source of the P-channel OMSFET is connected to the N-type well 501 by the metal wiring 507, and the power supply terminal V is connected.
It is connected to the DD.

At the gate electrode terminal A of the N-channel MOSFET and the gate electrode terminal B of the P-channel MOSFET, the P-channel MOSFET is made conductive by the operation result of the integrated circuit including this output circuit, and the output at the output terminal T is set to the high level. Yes, or N channel MOSFE
It is possible to realize a three-state in which T is made conductive and the output at the output terminal T is at a low level, or both N-channel MOSFET MOSFET and P-channel MOSFET are made non-conductive to make the output at the output terminal T high impedance. A control signal is input to each.

In a system using a microcomputer or the like, a plurality of integrated circuits arranged on a printed circuit board share a bus line and mutually transmit signals, so that each integrated circuit has a function of disconnecting an output from the bus line. Is usually used, and a stay-state output circuit that can make the output terminal high impedance is normally used.

[0006]

In this conventional output circuit, when the voltage of the power supply VDD is lower than the high level of the output of another integrated circuit which shares the bus wiring, the output circuit is in a high impedance state. Even if signals from the terminals A and B are given to the terminals, a current flows from the output terminal T to the VDD terminal, resulting in a rapid increase in power consumption.

The above problems will be described in detail with reference to FIG. The semiconductor chip 1 is an output portion of an integrated circuit including a conventional output circuit, and controls the output circuit including the enhancement-type P-channel MOSFET 601 and the enhancement-type N-channel MOSFET 604 already described with reference to FIG. CMOS2 for
Input NAND circuit 605 and CMOS 2-input NOR circuit 6
Contains 06. A signal which becomes a high level when a chip is selected is given to the terminal CT, and an inverted signal of CT is given to the terminal CB. That is, when CT is at high level, the input I
Is low level, the B point is high level and the P channel MOSFET 601 is non-conductive, while the A point is also high level, the N channel MOSFET 604 is conductive and, as a result, the output terminal T is low level first. When CT is at the high level and the input I is also at the high level, both points B and A are at the low level, the P-channel MOSFET 601 becomes conductive, and the N-channel MOSFET 601 becomes conductive.
604 becomes non-conductive, and the output terminal is in the high-level second state. Further, when the chip selection terminal CT is at the low level, the point A becomes the low level and the point B becomes the high level, regardless of the level of the input I, and the P channel MOSFE.
It is expected that the T601 and the N-channel MOSFET 604 are both non-conductive and the output terminal T has a high impedance.

However, the output terminal T has the bus wiring 60.
8 is connected to the output circuit of the semiconductor chip 2 using a power supply voltage (for example, 5 V) higher than the power supply VDD (for example, 3 V) of the semiconductor chip 1 through the semiconductor chip 2
P-channel MOSFET 601 and N-channel MOS
When low level signals are applied to the gates of the FETs 604, respectively, the CT of the semiconductor chip 1 is set to low level (CB is high level), and the output terminal T of the semiconductor chip 1 is set to a high impedance state. Even if the semiconductor chip 2 is connected to the 5V power supply,
Through the parasitic MOSFET 609 between the channel MOSFET 601, the bus wiring 608, the drain of the P-channel MOSFET 601 of the semiconductor chip 1 and the N-well (P-type impurity diffusion layer 502 and N-type well 501 of FIG. 5A), the power VDD A current flows to (3 V), and the P-channel MOSFET 601 of the semiconductor chip 1 is also conductive because a voltage higher than the threshold value is applied between the gate and the drain, which causes a rapid increase in power consumption. was there.

In order to prevent an increase in electric field and a decrease in reliability due to the increase in electric field due to the miniaturization of element size in the future, it is indispensable to lower the power supply voltage, and integrated circuits of different development periods also use different power supply voltages. As the number of cases increases, the above problems are becoming serious.

[0010]

A feature of the present invention is that an enhancement type P-channel MOSFET and a depletion type N-channel MOSF are provided between a first power source and a second power source.
A circuit in which the ET and the enhancement-type N-channel MOSFET are connected in series in the above-described order is provided, the connection point of the depletion-type N-channel MOSFET and the enhancement-type N-channel MOSFET is connected to the output terminal, and the gate of the enhancement-type P-channel MOSFET is connected. An enhancement-type N-channel MO for supplying a first input signal
A second input signal is supplied to the gate of the SFET, and the first input signal and the second input signal are both at a high level in a first state, and both are at a low level in a second state. One input signal is at a high level and a second input signal is at a low level in a third state.

Another feature of the present invention is that an enhancement type P channel MOSFE is provided between the first power supply and the second power supply.
T and depletion type N-channel MOSFET and first
A circuit in which the enhancement-type N-channel MOSFET and the second enhancement-type N-channel MOSFET are connected in series in the above-mentioned order, and the depletion-type N-channel MOSFET is output from the connection point of the first enhancement-type N-channel MOSFET. A first input signal to the gate of the enhancement-type P-channel MOSFET, the gate of the first enhancement-type N-channel MOSFET is connected to the first power supply, and the second enhancement-type N-channel is connected to the gate of the enhancement-type P-channel MOSFET. A second input signal is supplied to the gate of the channel MOSFET, and both the first input signal and the second input signal are at a high level in a first state and both are at a low level in a second state. And the first input signal is high level and the second input signal is low level. In the output circuit having a state.

[0012]

The present invention will be described below with reference to the drawings. FIG. 1A is a circuit diagram of the first embodiment of the present invention. An enhancement type P-channel MO is provided between both terminals of VDD (for example, 3 V) which is the first power source and VSS (usually 0 V) which is the second power source.
SFET101 and depletion type N channel MOS
FET 102a and enhancement type N-channel MOS
A series circuit of the FET 103 is installed, and a connection point between the depletion type N-channel MOSFET 102a and the enhancement type N-channel MOSFET 103 is an output terminal T.
It is connected to the.

Enhancement type P channel MOSFE
A CMOS 2-input NAN for inputting the signals of the chip selection signal terminal CT and the data input signal terminal I to the gate of T101.
The output of the D circuit 104 is connected, and similarly, the gate of the enhancement type N-channel MOSFET 103 is supplied with the signal of the signal terminal CB to which the inverted signal of the signal supplied to CT is supplied and the signal of the data input signal terminal I, which is a CMOS 2 input. The output of the NOR circuit 105 is connected. The gate of the depletion type N-channel MOSFET 102a is the depletion type N-channel MOSFET.
102a and enhancement type P-channel MOSFET
It is connected to the connection point 101.

When the input signal to the chip selection signal terminal CT is at high level, that is, when the input to the terminal CB is at low level, the input signal to the data input terminal I is at high level.
In this state, the enhancement type P channel MO
The gate potential of the SFET 101 and the gate potential of the enhancement type N-channel MOSFET 103 both become low level, and the depletion type N-channel MO
Since the SFET 102a is conducting, the potential of the output terminal T becomes high level, and in the second state where the input signal to the data input terminal I is low level, the potential of the gate of the enhancement P-channel MOSFET 101 and the enhancement N channel Since the potentials of the gates of the MOSFETs 103 are all at the high level, the potential of the output terminal T is at the low level, as in the case of FIG.

When the input signal to the chip select signal terminal CT is low level, that is, the input to the terminal CB is high level, the gate potential of the enhancement type P-channel MOSFET 101 is irrespective of the level of the input signal to the data input terminal I. At the high level, the gate of the enhancement-type N-channel MOSFET 103 becomes the low-level third state, and the depletion-type N-channel MOSFET 103
By setting the threshold voltage of 102a to an appropriate value, the depletion type N-channel MOSFET 10 is applied when a voltage of VDD or more is applied to T at the output terminal from the outside.
It is possible to prevent the current from the output terminal T to the power supply terminal VDD by making 2a non-conductive.

In the embodiment of FIG. 1A, as the threshold VTD of the depletion type N-channel MOSFET, the variation amount of the threshold when -VDD is applied to the substrate (N well) with respect to the source is ΔVTD. Then, (1) In the first state, the potential of the output terminal is the output standard value VOH.
VOH <VDD− (VTD + ΔVTD) (2) In order to prevent the parasitic diode 108 from being forward biased in the third state, VTD + ΔVTD> 0−ΔVTD <VTD <VDD -VOH-ΔVTD ΔVTD is determined by the gate insulating film thickness, P-type well concentration, and the like. Similar to FIG. 5, when the output circuit of the 3 volt power supply is connected to the integrated circuit of the 5 V power supply through the bus wiring, VDD = 3 volt, and VOH is 2.4 volt which is the standard TTL standard plus a margin. 2.6V, △ VTD
By substituting 0.5 V into the above equation, −0.5 (volt) <VTD <−0.1 (volt) is obtained as shown in FIG. 1 (a).
This is an appropriate range for the threshold of the ET 102a.

Further, the depletion type N shown in FIG.
A depletion type N in which the gate shown in FIG. 1B of the channel MOSFET 102a is connected to the power supply terminal VDD.
It may be replaced with the channel MOSFET 102b. In this case, the lower limit of VTD is that the potential at the connection point of the enhancement P-channel MOSFET 101 and the depletion type N-channel MOSFET 102b is approximately {(VDD potential) + (P- of the parasitic diode 108- Built-in potential VF with N-junction or enhancement type P
It is obtained from the condition that the depletion type N-channel MOSFET 102b becomes non-conductive when the absolute value of the threshold voltage VTP of the channel MOSFET (smaller value of absolute value)} is increased, and −ΔVTD−VF <VTD and −ΔVTD− (Absolute value of VTP) <VTD, but if VF = 0.7 V and VTP = −0.4 V, the upper limit of VTD is the same as in the case of FIG. 9V <VTD <-0.1V, and the allowable range of VTD increases.

Alternatively, the depletion type N-channel MOSFET 102a shown in FIG. 1 (a) is connected to the resistor 106 and the depletion type channel MOSFE shown in FIG. 1 (c).
A low voltage may be generated in the series circuit of T107 and replaced with a circuit that supplies the low voltage to the depletion type N-channel MOSFET 102c and the gate. In this case, the threshold voltage V of the depletion type N-channel MOSFET 102c is changed.
When TD is low, the gate voltage is also low, and the threshold VT
When D is high, the gate voltage also becomes high, so that the manufacturing variation of VTD can be compensated, and the depletion type M
The allowable range of the threshold VTD of the OSFET 102c can be further expanded.

In addition, the depletion type N shown in FIG.
The channel MOSFET 102a may be replaced with a depletion-type N-channel MOSFET 102d whose gate is connected to the chip selection signal CT terminal shown in FIG. 1D. In this case, in the third state, the depletion-type N-channel MOSFET 102d is used. Since the gate of the channel MOSFET 102d has a potential of 0 volt, the lower limit of VTD is further widened, and −ΔVTD− (absolute value of VTP) −VDD <VTD, and the upper limit is the same as in the case of FIG.
When D is 3 volts, -3.9 (volts) <VTD <-0.1 (volts), and the threshold variation during manufacturing does not affect the operation of the present invention even when mounted on an integrated circuit. Can be widely used.

Next, a second embodiment of the present invention will be described with reference to FIG. A series circuit of an enhancement type P-channel MOSFET 201, a depletion type N-channel MOSFET 202 and an enhancement type N-channel MOSFET 203 is installed between the power supply VDD and VSS.
The gate of the enhancement P-channel MOSFET 201 is connected to the output of the CMOS 2-input NAND circuit 204 having CT and I as inputs, the gate of the depletion N-channel MOSFET 202 is connected to CT, and the gate of the enhancement N-channel MOSFET 203 is CB. CMO with CMOS2 input with I and I as input
The fact that it is connected to the output of the S2 input NOR circuit 205 means that the depletion type N-channel MOS in FIG.
Although the FET 102a is the same as the one in which the depletion type N-channel MOSFET 102d in FIG. 1D is replaced, the gate insulating film thickness of the depletion type N-channel MOSFET 202 and the enhancement type N-channel MOSFET 203 in FIG. Is CMOS
N-channel MOSFET and P-channel MOSFET and enhancement-type P-channel MOS forming the 2-input NAND circuit 204 and the CMOS 2-input NOR circuit 205
It is thicker than the gate insulating film thickness of the FET 201.

That is, as shown in FIG. 2B, a P-type substrate 21
N-channel MOSFET 23a having a thin gate insulating film 25a and N-channel MOSFET having a thick gate insulating film 25b on the surface of the P-type well 22 formed on the surface of
23b to form a thin gate insulating film MOSFET 23
a in the NAND circuit 204 and NOR circuit 205
OSFET and enhancement type P channel MOSFE
In the case where a voltage of 5 V is externally applied to the output terminal T by applying the N-channel MOSFET 23b forming the T201 and having the thick gate insulating film to the depletion-type N-channel MOSFET 202 and the enhancement-type N-channel MOSFET 203. In addition, it is possible to prevent deterioration of the insulation property of the insulating film with time, while other MOS
Since a thin insulating film can be used for the FET, the current is large at the time of conduction even under a voltage of 3 V, so that high-speed operation is possible.
A gate insulating film thickness of about 10 nm (nanometer) is suitable for a power supply of 3 V, and a gate insulating film thickness of MOSFETs 202 and 203 connected to an output terminal T to which a voltage of 5 V is applied is about 15 nm (nanometer). Is appropriate. In FIG. 2B, 24 is a source,
An N-type impurity diffusion layer serving as a drain, and 26 denotes a polysilicon gate electrode.

FIG. 3 is a circuit diagram of the third embodiment of the present invention. VDD which is the first power supply (eg 3.3 volt)
And an enhancement type P-channel MOSFET 301 between both terminals of the second power source VSS (usually 0 volt)
And depletion type N-channel MOSFET 302a
And the first enhancement type N-channel MOSFET 3
03 and second enhancement type N channel MOSFE
Depletion type N with T304 series circuit installed
The connection point between the channel MOSFET 302a and the first enhancement type N-channel MOSFET 303 is connected to the output terminal T.

The gate of the enhancement-type P-channel 301 is connected to the chip selection signal terminal CT and the output of the CMOS 2-input NAND circuit 305 which receives the signal of the data input signal I, and similarly the second enhancement-type N-channel MOSFET 304. A CMOS 2-input NOR which receives signals from a signal terminal CB to which an inverted signal of a signal supplied to CT is supplied to a gate and a signal from a data input signal terminal I is input.
The output of the circuit 306 is connected. The gate of the depletion type N-channel MOSFET 302a is
This depletion type N-channel MOSFET 302
a and enhancement type P-channel MOSFET 301
Of the first enhancement-type N-channel MOSFET 303 is connected to the connection point of
It is connected to DD.

There are the following three conditions in use of this output circuit.
There are two states, each of which is explained below.

(1) First state: Chip selection signal terminal C
When both T and the input signal to the data terminal I are at the high level (the input to the terminal CB is at the low level).

Enhancement type P channel MOSFE
Gate potential of T301 and second enhancement type N
The gate potentials of the channel MOSFETs 304 are all at the low level, and the depletion type N-channel MOS
Since the FET 302a is conducting, the potential of the output terminal T becomes high level.

(2) Second state: Chip selection signal terminal C
When the input signal to T is high level (the input to the terminal CB is low level) and the input signal to the data terminal I is low level.

Enhancement type P channel MOSFE
Gate potential of T301 and second enhancement type N
The gate potentials of the channel MOSFETs 304 are all at a high level, and the depletion type N-channel MOS
Since the FET 302a is conducting, the potential of the output terminal T becomes low level.

(3) Third state: Chip selection signal terminal C
When the input signal to T is low level (the input to terminal CB is high level).

An enhancement type P channel MOSFET regardless of the level of the input signal to the data input terminal I.
The gate potential of 301 is at a high level, and the gate potential of the second enhancement type N-channel MOSFET 304 is at a low level. In this state, when a voltage higher than VDD is applied to the output terminal T from the outside, the depletion type N channel is set by setting the threshold voltage of the depletion type N channel MOSFET 302a to an appropriate value. The MOSFET 302a becomes non-conductive to prevent a current from the output terminal T to the power supply terminal VDD, and on the VSS side, the voltage applied between the gate and drain of the first enhancement type N-channel MOSFET 303 is 2V at most. Therefore, sufficient reliability is ensured even in the manufacturing process in which the gate oxide film thickness is in the vicinity of 10 nm (nanometer).

In the first embodiment of FIG. 1, as the threshold VTD of the depletion type N-channel MOSFET, the fluctuation of the threshold when -VDD is applied to the substrate (N well) with respect to the source. If the amount is ΔVTD, (A): In the first state, the potential of the output terminal is the output standard value VO.
Since it has to be larger than H, VOH <VDD− (VTD−ΔVTD) (B): VTD + ΔVTD> 0−ΔVTD <in order that the parasitic diode 309 does not become forward bias in the third state. VTD <VDD-VOH-ΔVTD. ΔVTD is determined by the gate insulating film thickness, P-type well concentration and the like. Similar to FIG. 5, when the output circuit of the 3V power supply is connected to the integrated circuit of the 5V power supply via the bus wiring, VDD = 3V, and VOH is 2.4V which is the standard TTL standard + 2.6V with a margin. And ΔVTD is 0.
By introducing 5 V into the above equation, -0.5 (volt) <VTD <-0.1 (volt) becomes the depletion type N-channel MOSFET 3 of FIG.
This is an appropriate range of the threshold value of 02a.

Here, the depletion type N-channel MOSFET 302a of FIG. 3A may be replaced with the depletion type N-channel MOSFET 302b shown in FIG. 3B in which the gate is connected to the power supply terminal VDD.
The lower limit of VTD in this case is that the potential at the connection point between the enhancement-type P-channel MOSFET 301 and the depletion-type N-channel MOSFET 302b is approximately (VDD potential) + (the built-in potential VF of the P-N junction of the parasitic diode 309 or the enhancement type VF). It is obtained from the condition that the depletion type N-tunnel MOSFET 302b becomes non-conductive when the threshold voltage VTP of the P-channel MOSFET 301 rises to the smaller one), -ΔVTD-VF <VTD and − △ VTD- (VTP
However, if VF = 0.7V and VTD = −0.4V, then considering that the upper limit of VTD is the same as in the case of FIG. (Volts) <VTD <-0.1 (Volts), and the allowable range of VTD increases.

Further, the depletion type N shown in FIG.
The channel MOSFET 302a is composed of the resistor 307 and the depletion type N-channel MOSFET shown in FIG.
It may be replaced with a circuit that generates a low voltage in the series circuit of 308 and supplies this to the gate of the depletion type N-channel MOSFET 302c. In this case, the threshold VTD of the depletion type N-channel MOSFET 302c is When the threshold voltage VTD is low, the gate voltage is low, and when the threshold voltage VTD is high, the gate voltage is also high. Therefore, it is possible to compensate the manufacturing variation of the VTD, and the allowable range of the threshold VTD of the depletion type N-channel MOSFET 302c. Can be further expanded.

Further, the depletion type N shown in FIG.
The channel MOSFET 302a may be replaced with a depletion type N-channel MOSFET 302d whose gate shown in FIG. 3D is connected to the chip selection signal CT terminal. In this case, in the third state, the gate of the depletion type N-channel MOSFET 302d has a potential of 0 volt, so that the lower limit of VTD further widens, and −ΔVTD− (absolute value of VTP) −VDD <VTD, Since the upper limit is the same as in the case of FIG.
When DD is 3 V, -3.9 (V) <VTD <-0.1 (V), and even when mounted on an integrated circuit, the variation in the threshold does not affect the operation of the present invention at all. Can be as wide as possible.

FIG. 4A is a circuit diagram showing an output circuit of the fourth embodiment of the present invention, and FIG. 4B is a sectional view showing the first and second enhancement type N-channel MOSFETs. is there.

In FIG. 4, parts that are the same as or similar to those in FIG. 3 are denoted by the same reference numerals, and the same description will be omitted.
The fourth embodiment shown in FIG. 4 differs from the third embodiment shown in FIG. 3 in that the first enhancement type N is used in the third embodiment.
Both the channel MOSFET 303 and the second enhancement type N-channel MOSFET 304 are P wells (see FIG. 3).
However, in the fourth embodiment, an N-type is formed on the P-type substrate 406 having an impurity concentration lower than that of the P-well.
Of the first enhancement type N-channel MOSFET 4 by forming the type impurity diffusion layer 404 as a source and a drain.
01, and the N-type impurity diffusion layer 404 formed in the P-well 405 having a higher impurity concentration than the P-type substrate is used as a source,
Second enhancement type N channel M as drain
The OSFET 402 is formed.

Generally, the threshold voltage VT of the MOSFET
Is then given by equation (1).

[0038]

Differentiating this equation (1) by VB gives the following equation (2).

[0040]

Now, in the fourth embodiment, the impurity concentration of the P-type substrate 406 in which the first enhancement type N-channel MOSFET 401 is formed and the impurity concentration of the P-type well 405 in which the second enhancement type N-channel MOSFET 402 is formed. If it is one digit lower than the first enhancement type N channel M,
The substrate bias dependence of VT of the OSFET 401 is the second
Enhancement type N-channel MOSFET 304,
It can be seen that it can be suppressed to approximately 0.32 times the reciprocal of 402 (the reciprocal of the square root of 10).

In the fourth embodiment of FIG. 4 also, instead of the depletion type N-channel MOSFET 302a whose gate is connected to the P-channel MOSFET 301, the depletion type N-type whose gate is connected to the power supply terminal VDD is used.
It may be replaced with a channel MOSFET 302b (FIG. 3B), or a depletion type N-channel MOSFET 302c having a gate connected to a power supply terminal VDD and a depletion type N-channel MOSFET connected to a terminal generating a low voltage. (FIG. 3C), or a depletion-type N-channel MOSFET 3 whose gate is connected to the chip selection signal CT
02d (FIG. 3 (d)).

[0043]

As described above, according to the present invention, by installing the depletion type N-channel MOSFET between the P-channel MOSFET and the output terminal in the conventional output circuit, the power supply voltage from the outside to the output terminal is increased. Even when a high voltage is applied, the current path from the output terminal to the power supply terminal can be cut off, so power consumption is reduced even when connected to other integrated circuits that use a high power supply voltage via bus wiring. It has the effect of preventing a sudden increase.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output circuit of a first embodiment of the present invention.

FIG. 2 is a circuit diagram and a partial sectional view showing an output circuit of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an output circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram and a partial sectional view showing an output circuit of a fourth embodiment of the present invention.

5A and 5B are a partial cross-sectional view showing a conventional output circuit and a circuit diagram for explaining problems.

[Explanation of symbols]

21, 406, 506 P-type substrate 22, 103, 405, 505 P-type well 604 Enhancement-type N-channel MOSFET 23a Thin gate insulating film MOSFET 23b Thick gate insulating film MOSFET 24, 404, 504 N-type impurity diffusion layer 25a Thin Gate insulating film 25b Thick gate insulating film 26,403,503 Gate polysilicon 101,201,301,601 Enhancement type P channel MOSFET 102a, 102b, 102c, 102d, 107,3
02a, 302b, 302c, 302d, 308 Depletion type N-channel MOSFET 104, 204, 305, 605 CMOS 2-input N
AND circuit 105, 205, 306, 606 CMOS 2 input N
OR circuit 108, 309, 609 Parasitic diode 202 Depletion-type N-channel MOSFET 203 with thick gate film 203 Enhancement-type N-channel MOSFET 303 with thick gate film 1st enhancement-type N-channel MOS transistor
FET 304 Second enhancement type N-channel MOS
FETs 106, 307 Resistors 401 First enhancement type N-channel MOSFET 402 formed on P-type substrate 402 Second enhancement type N-channel MOSFET 501 N-type well 502 P-type impurity diffusion layer 507 Metal wiring 608 bus formed on P-type well wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (16)

[Claims] 1. A circuit in which an enhancement type P-channel MOSFET, a depletion type N-channel MOSFET and an enhancement type N-channel MOSFET are connected in series in the above order between a first power source and a second power source, A connection point between the depletion-type N-channel MOSFET and the enhancement-type N-channel MOSFET is connected to an output terminal, a first input signal is supplied to the gate of the enhancement-type P-channel MOSFET, and the enhancement-type N-channel MOSFET is connected. A second input signal is supplied to the gate of the first input signal, and the first input signal and the second input signal are both in a high level first state, and both are in a low level second state, A third state in which the first input signal is high level and the second input signal is low level Output circuit characterized by. 2. The output circuit according to claim 1, wherein a gate of the depletion type N-channel MOSFET is connected to a connection point of the enhancement type P-channel MOSFET and the depletion type N-channel MOSFET. Output circuit to do. 3. The output circuit according to claim 1, wherein the gate of the depletion type N-channel MOSFET is connected to a first power supply. 4. The output circuit according to claim 1, wherein the gate of the depletion type N-channel MOSFET is connected to a constant voltage generating circuit that generates a voltage of a lower potential than the first power supply. Output circuit. 5. The output circuit according to claim 1, wherein the gate of the depletion-type N-channel MOSFET has a third input which is at a high level in the second state and is at a low level in the third state. An output circuit characterized by supplying a signal. 6. The output circuit according to claim 5, wherein the depletion type N-channel MOSFET and the enhancement type N-channel MOSFET have a gate insulating film thicker than a gate insulating film of the enhancement type P-channel MOSFET. An output circuit using a MOS transistor. 7. An enhancement-type P-channel MOSFET, a depletion-type N-channel MOSFET, a first enhancement-type N-channel MOSFET and a second enhancement-type N-channel MOSFET are provided between the first power supply and the second power supply. The depletion-type N-channel MOSF is provided with the circuits connected in series in the above order.
ET and the first enhancement type N channel MOS
A connection point of the FET is connected to an output terminal, a first input signal is supplied to the gate of the enhancement type P-channel MOSFET, a gate of the first enhancement type N-channel MOSFET is connected to a first power source, and Second
A second input signal is supplied to the gate of the enhancement-type N-channel MOSFET, and the first input signal and the second input signal are both at a high level in a first state, and both are at a low level. An output circuit having a second state and a third state in which a first input signal is a bilevel and a second input signal is a low level. 8. The output circuit according to claim 7, wherein the gate of the depletion type N-channel MOSFET is connected to the connection point of the enhancement type P-channel MOSFET and the depletion type N-channel MOSFET. Characteristic output circuit. 9. The output circuit according to claim 7, wherein the gate of the depletion type N-channel MOSFET is connected to the first power supply. 10. The output circuit according to claim 7, wherein the gate of the depletion type N-channel MOSFET is connected to a constant voltage generating circuit for generating a voltage lower than the first power source. Output circuit. 11. The output circuit according to claim 7, wherein the gate of the depletion-type N-channel MOSFET has a third input signal which is at a high level in the second state and is at a low level in the third state. An output circuit characterized in that 12. An enhancement-type P-channel MOSFET, a depletion-type N-channel MOSFET, a first enhancement-type N-channel MOSFET, and a second enhancement-type N-channel MOSFET are provided between the first power supply and the second power supply. A circuit in which the substrate impurity concentration of the first enhancement-type N-channel MOSFET is lower than that of the second enhancement-type N-channel MOSFET. Of the first enhancement-type N-channel MOSFET and the first enhancement-type N-channel MOSFET by connecting a connection point between the first enhancement-type N-channel MOSFET and the output terminal to a gate of the enhancement-type P-channel MOSFE. Channel MOSFET The gate of the second enhancement-type N-channel MOSF is connected to the first power supply.
A second input signal is supplied to the gate of ET, and a first state in which both the first input signal and the second input signal are at a high level and a second state in which both are at a low level An output circuit having a third state in which the first input signal is at a high level and the second input signal is at a low level. 13. The output circuit according to claim 12, wherein:
A gate of the depletion type N-channel MOSFET is connected to the enhancement type P-channel MOSFET.
And an output circuit connected to a connection point of the depletion type N-channel MOSFET. 14. The output circuit according to claim 12, wherein:
An output circuit in which the gate of the depletion type N-channel MOSFET is connected to the first power supply. 15. The output circuit according to claim 12,
An output circuit characterized in that the gate of the depletion type N-channel MOSFET is connected to a constant voltage generating circuit for generating a voltage of a lower potential than the first power supply. 16. The output circuit according to claim 12,
An output circuit, wherein a third input signal, which is at a high level in the second state and is at a low level in the third state, is supplied to the gate of the depletion type N-channel MOSFET.