JPH065074A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enhance a user's operating convenience by a method wherein it is not required to concern an automatic refresh operation which had to be performed surely by the control on the side of a system after a self-refresh operation has been finished. CONSTITUTION:A refresh block 23 and a timer circuit 24 are installed as control blocks used to change over the following according to a condition given from the outside of a semiconductor memory device: a self-refresh control mode whose cycle is comparatively long; and a self-refresh control mode whose cycle is comparatively short. Thereby, when the finish of a self-refresh operation whose cycle is comparatively long is sensed and a refresh operation whose cycle is comparatively short is performed automatically, it is not required to perform an automatic refresh operation by the control on the side of a system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a refresh control technique therefor, and more particularly to a technique effectively applied to a dynamic RAM (random access memory).

[0002]

2. Description of the Related Art A conventional dynamic RAM (hereinafter referred to as DR
(Abbreviated as AM), the RAS only refresh operation basically performed in synchronization with a RAS (row address strobe) signal indicating the validity of a row address, and RA
CBR initiated by asserting CAS (Column Address Strobe) before S is asserted
Auto refresh operation by refresh is performed,
Information stored in the dynamic memory cell is retained by such a refresh operation.

In recent years, in a byte wide DRAM, for example, as shown in FIG. 8, a period during which a RAS * (* indicates low active or signal inversion) signal is asserted to a low level during CBR refresh is predetermined. By shifting the self-refreshing operation mode to the self-refreshing operation mode, the refreshing operation is repeated at a preset timer cycle by the operation of the refresh timer mounted in the memory LSI.
In such a self-refresh operation, the timer cycle for refresh is set as long as possible by considering the device characteristics (junction leakage etc.) and circuit technology (LSI chip temperature etc. determined by current design technology). Therefore, it is general to reduce the current during the cell refresh operation. In other words, the self-refresh operation is aimed at retaining memory cell information, especially at the time of battery backup.

As an example of the document describing the self-refresh, "LSI Handbook (No. 4), issued from Ohmsha Co., Ltd. on November 30, 1984.
Page 86) ".

[0005]

In the above self-refresh operation, the information holding capacity of the oldest self-refreshed memory cell in the self-refresh cycle realized by the refresh timer is limited, and the subsequent read / write operation is limited. Unless the refresh operation is performed again immediately before the write operation, the memory information may be destroyed. Therefore, in a system including a memory LSI having such a self-refresh operation mode, as shown in FIG. 8, after the self-refresh operation (Long CBR) is completed, an auto-refresh with a relatively short cycle (Autorefresh by CBR is performed.
It was necessary to design the system so that h) is always performed.

The object of the present invention is to improve the usability of the user by eliminating the need to consider the auto-refresh operation, which has always been performed by the control of the system after the self-refresh operation is completed. An object is to provide an improved semiconductor memory device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a control block is included for switching between a first self-refresh control mode having a relatively long cycle and a second self-refresh control mode having a relatively short cycle according to a condition given from the outside of the semiconductor memory device. It constitutes a semiconductor memory device. At this time, the control block can be configured to switch between the first self-refresh control mode and the second self-refresh control mode based on the state of the row address strobe signal supplied from the outside. In a more specific aspect, a first timer for determining the refresh cycle in the first self-refresh mode, a second timer for determining the refresh cycle in the second self-refresh mode, and the timer output are set to low. The control block can be configured to include a selection circuit for selectively participating in refresh control based on the address strobe signal.

[0010]

According to the above means, the control block is
By implementing two types of self-refresh control with mutually different cycles, this eliminates the need for consideration of the auto-refresh operation, which has always been required by the control on the system side after the self-refresh operation is completed, and eliminates the need for the user. Achieve improved usability.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS For example, in an application of 4 Mbit DRAM, 1024 refresh cycles must be executed every 16 msec. However, since the current consumption of the memory LSI is proportional to the refresh cycle time, the self refresh operation is performed. The refresh operation for realizing the above is set from a period longer than 15.6 μsec to a period shorter than the limit of the information holding ability of the memory cell, thereby reducing the current consumption during self refresh as much as possible. Designed to be. Further, the refresh operation having a relatively short cycle is set to a cycle close to the minimum cycle time of a normal read / write operation, for example, 110 nsec. In view of this, in the present embodiment, by incorporating in the semiconductor memory device a means for realizing two types of refresh operations having different periods as cell full refresh as described above, the control on the system side after the self-refresh operation is completed. By doing so, it is not necessary to consider the auto-refresh operation, which has always been necessary to do so, and the user-friendliness is improved.

That is, since the conventional self-refresh operation is used for holding the information of the memory cell, it is used when the memory LSI is in the standby state, for example, when the memory system is in the OFF state, and at this time, the system is backed up by the battery. In many cases, the power consumption must be minimized. The reason why the cycle of the refresh timer during the self-refresh operation is made as long as possible is as described above. On the other hand, the refresh operation after self-refresh has a short cycle (for example, 110
nsec), for example, assuming that the refresh cycle is repeated 1024 times, even for the oldest refreshed memory cell, at least about 62 msec,
This is because it is not necessary to perform the refresh operation thereafter.

FIG. 1 shows the overall structure of a DRAM according to an embodiment of the present invention.

Although not particularly limited, the DRAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, reference numeral 32 denotes a memory cell array portion in which a plurality of dynamic memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction, and data terminals of the memory cells are column columns. Each direction is coupled to a complementary data line. Then, each complementary data line is commonly connected to the complementary common data line via a column selection circuit 29 including a plurality of column selection switches coupled to the complementary data line in a one-to-one relationship. The column selection circuit 29 is coupled to the data external terminal via the input / output circuit 31 to enable data exchange with the outside. A row address input from the outside is input to the row decoder 30 via the row address buffer 26 and decoded by the row decoder 30. The word line in the memory cell array section 32 is selectively driven based on the decoded output. Further, the column address input from the outside is input to the column decoder 28 via the column address buffer 27 and is decoded here. The decoded output is input to the column selection circuit 29, and the operation of the column selection switch is controlled based on the decoded output.

Reference numeral 21 is a RAS block, and 22 is a CAS block, which generates operation timing signals for the respective parts of this embodiment by adjusting the timings of the RAS * signal and the CAS * signal which are externally applied. Reference numeral 23 is a refresh block. This refresh block 23 senses the timing of CBR from the states of the RAS * signal and the CAS * signal and generates various signals for refresh control. The timer circuit 24 including the two timers 24A and 24B is for determining the cycle of the refresh operation, and its operation is started by asserting the refresh control signal output from the refresh block 23. In other words, the two timers 24A and 24B generate two kinds of clocks having different cycles, and by selectively causing such a clock to participate in the refresh operation, a relatively long cycle is obtained. The first self-refresh control mode and the second self-refresh control mode having a relatively short cycle are realized. Address counter circuit 25
Is a so-called binary counter, and the timer 24A,
The refresh address is counted up in accordance with the cycle of 24B. The refresh address from the address counter circuit 25 is input to the row decoder 30 via the row address buffer 26, and the decoded output from the row decoder 30 causes the memory cell array section 32 to be supplied.
The self-refreshing operation is repeated at a predetermined cycle by sequentially driving the word lines in.

Although not shown, only the read or write operation can be performed during one memory cycle (one cycle of the RAS * clock). Therefore, the row address is set to CAS at the falling edge of the RAS * clock. * The column address is taken into the internal circuit at the falling edge of the clock, and it is possible to judge whether the relevant cycle is a write cycle or a read cycle depending on the state of the write enable signal WE *.

Next, the detailed structure of each block will be described.

FIG. 2 shows a configuration example of the RAS block 21, FIG. 3 shows a configuration example of the refresh block 23, FIG. 4 shows a configuration example of the timer circuit 24, and FIG. Shows a configuration example of the counter circuit 25. Further, FIG. 6 shows the operation timing of the main part.

In FIG. 2, the RAS input from the outside
* Signal is transmitted through p-channel MOS transistor 38 and n-channel MOS through inverters 35 and 36.
It is input to the gate of the transistor 39. Inverter 3
The output of 6 is refresh block 2 as R0 * signal.
Input to 3. p-channel type MOS transistor 3
7, 38, n-channel type MOS transistors 39, 4
By serially connecting 0s, a clocked inverter 46 whose operation is controlled by the complementary RF signal and RF * signal from the refresh block 23 is formed.
In addition, p-channel type MOS transistors 41, 42,
By connecting the n-channel type MOS transistors 43 and 44 in series, a clocked inverter 47 whose operation is controlled by the complementary RF signal and RF * signal from the refresh block 23 is configured, and the timer circuit 2
Main signal RCC * from 4 is p-channel type MOS
It is input to the gates of the transistor 42 and the n-channel type MOS transistor 43. The clocked inverters 46 and 47 are complementarily turned on so that the RAS RO * signal and the main signal RCC * are selectively transmitted to the subsequent circuit including the inverter 45. Has become. By turning on the clocked inverter 47, when the main signal main signal RCC * from the timer circuit 83 is input, the self-refresh operation determined by the cycle of the main signal RCC * at that time is performed.

As shown in FIG. 3, the refresh block 23 has a CBR cycle (CBR Cycle).
It includes a CBR detection circuit 50 for detecting e). The CBR detection circuit 50 includes p-channel type MOS transistors 51 and 52 and an n-channel type MOS transistor 5.
A clocked inverter formed by connecting 3, 54 in series,
Similarly, p-channel MOS transistors 55, 56,
A clocked inverter formed by connecting n-channel type MOS transistors 57 and 58 in series is coupled, and the control signal thereof is the output R0 * signal of the inverter 36 in the RAS block 21 and the signal obtained by inverting it in the inverter 59. It is said that The output of the clocked inverter is transmitted to one input terminal of the 2-input NAND gate 61 and is also input to the gates of the MOS transistors 56 and 57 via the inverter 60. Further, the CAS * signal is inverted in the CAS block 22. The C1 signal obtained by doing so is input to the gates of the MOS transistors 52 and 53 via the inverter 50.

Further, the R0 * signal is supplied to the inverter 62.
Is transmitted to the other input terminal of the 2-input NAND gate 61 to obtain the NAND logic thereof. The output of the NAND gate 61 is RFM *, and the low level period of RFM * is the CBR cycle. In other words, the R0 * signal, which is a RAS system signal,
Based on C1 which is a signal of the CAS system, CBR in which the CAS * signal is asserted before the RAS * signal is detected.

The RFM * signal is a flip-flop FF formed by connecting two-input NAND gates 66 and 67.
By being input to 1 and being transmitted to one input terminal of the 2-input NAND gate 64, NAND logic with the output of the delay circuit 63 for delaying the output RC1 * of the timer 24A for a predetermined time can be obtained. There is. This NAND logic is inverted by the inverter 65 at the subsequent stage, so that T
An EX signal is obtained and transmitted to the timer circuit 24.

C which is the output of the address counter circuit 25
0 is the above flip-flop FF via the inverter 68
1, the flip-flop FF1 is reset by the C0 signal. The output of the flip-flop FF1 is inverted by the inverter 69 in the subsequent stage to be an RF * signal, and further inverted by the inverter 70 in the subsequent stage to be an RF signal. The RF signal and the RF * signal are transmitted to the RAS block 21 shown in FIG.

The timer circuit 24, as shown in FIG.
Inverter 65 in the refresh block 23
24A for generating a timing signal RC1 * having a relatively long cycle by using the output TXE signal of
NAND gate 7 for obtaining NAND logic between the X signal and the RF signal
4 and a timer 24B for generating a timing signal RC2 * having a relatively short cycle by using the output of the NAND gate 74 as a trigger, and the outputs of the two timers 24A, 24B. It includes two clocked inverters 72, 73 and an inverter 83 for inverting the output selected by the clocked inverters 72, 73. This inverter 8
3 is the output main signal RCC * of the timer circuit 24.
Is input to the clocked inverter 47 in the RAS block 21 (see FIG. 2). The clocked inverter 72 is a p-channel MOS transistor 7
5,76, n-channel type MOS transistors 77,7
8 are connected in series, and the clocked inverter 73 is a p-channel type MOS transistor 79, 8
0 and n channel type MOS transistors 81 and 82 are connected in series. The TEX signal is input to the gates of the p-channel MOS transistor 75 and the n-channel MOS transistor 82, and the TEX * signal is input to the gates of the n-channel MOS transistor 78 and the p-channel MOS transistor 79. The clocked inverters 72 and 73 are complementarily turned on, and by such an operation, the two timers 24
It is possible to select the outputs of A and 24B, and the selected output is the RAS block 21 or the address counter circuit 2
5 is transmitted.

As shown in FIG. 5, the address counter circuit 25 has a function of generating a refresh address, and has a counting unit 104, a reset unit 103 for initializing the counting unit, and a final address detecting unit. 105 and. The counting unit 104 includes n (n is a positive integer) address counters 94-1 to 94-n, which are connected so as to carry in order. CR0 to Ci-1 in the figure are carry signals for carry.
The final address detection unit 105 outputs the address outputs ar0 to ar of the address counters 94-1 to 94-n.
a NAND gate 96 for obtaining the NAND logic of i, and an inverter 97 for inverting the output of the NAND gate 96,
A NAND gate 98 for obtaining the output of the inverter 97 and the TEX signal NAND logic, two NAND gates 99 and 100 forming a flip-flop FF2, and an inverter 101 for inverting the output of the flip-flop FF2.
The output CO of the inverter 101 is transmitted to the inverter 68 in the refresh block 23 as a final address detection signal. When the final address of the memory cell array section 32 is formed in the address counter circuit 25, the final address detection signal CO is asserted to the high level as shown in FIG. .

According to the above embodiment, the following operational effects can be obtained.

At the CBR cycle, the refresh block 23 asserts the RFM * signal, which asserts the TEX, CO, RF, and RF * signals to start the operation of the timer 24A. In the RAS block 21, the main signal RCC * is taken in by the RF signal and the RF * signal, whereby the refresh operation determined by the timer cycle is repeated. In the address counter circuit 25, the refresh address is counted up in accordance with the cycle of the main signal RCC *, and the information of the memory cells connected to the word line designated by the address counter is sequentially refreshed. The refresh timer 24
If the external RAS * signal is negated to a high level while the refresh operation by A is repeated,
Since the output logic state of the inverter 68 in the refresh block 23 becomes low level, the RFM
* The signal is negated to high level. RF like this
When M * is high level and the output RC1 * signal of the refresh timer 24A is high level, the TEX signal is reset. That is, even if the internal refresh operation is forcibly interrupted by the external RAS * signal, the high level of the RAS * signal is not accepted until the precharge operation (reset operation) by the internal refresh operation is completed. To do.

When the TEX signal is asserted to the high level, the operation of the timer 24B is started and the delay circuit 9
When the reset signal RST is asserted to the high level with a delay time of 0, the address counters 94-1 to 94-n in the address counter circuit 25 are asserted.
Is reset. The main signal RCC * is the timer 24
The operation is performed in the cycle determined by B, whereby the refresh operation having a relatively short cycle is performed. When all the word lines are selected by the address counter and the refresh operation of the memory cell information is completed, the final address detection signal CO is asserted to the high level in the address counter circuit 25, thereby completing the series of self-refresh operations. .

As described above, in the present embodiment, the control block for switching between the self-refresh control mode having a relatively long cycle and the self-refresh control mode having a relatively short cycle according to a condition given from the outside of the semiconductor memory device. As a result, by including the refresh block 23 and the timer circuit 24, when the end of the self-refresh operation of a relatively long cycle is detected, the memory L
Since the refresh operation with a relatively short cycle is automatically performed inside the SI, the automatic refresh operation, which has always been required by the system control after the self-refresh operation, is unnecessary. Therefore, the usability for the user is improved.

Although the present invention has been described based on the above embodiments, it is needless to say that the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. For example, the timer circuit may share the oscillator part as shown in FIG. 7 and generate a required cycle by a frequency divider.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, as shown in FIG. 7, the timer circuit 24 may be configured so that the oscillator 110 is shared and a desired period is obtained by the frequency divider. That is, the frequency divider 11 that divides the oscillation output of the oscillator 110
1 and a frequency divider 112 that further divides the frequency-divided output. The output of the frequency divider 111 in the front stage corresponds to the RC2 * signal, and the output of the frequency divider circuit 112 in the rear stage corresponds to the RC1 * signal. Even in this case, since two types of clocks having different periods can be obtained, the configuration of FIG. 7 can be applied instead of the configuration of FIG.

In the above description, the invention made mainly by the present inventor is the field of application behind which DRA is applied.
However, the present invention is not limited to this, and various semiconductor memory devices that require a refresh operation, and a data processing device such as a microcomputer including such a semiconductor memory device. Can be widely applied to.

The present invention can be applied under the condition that at least the refresh operation is performed.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a control block is provided for switching between the first self-refresh control mode having a relatively long cycle and the second self-refresh control mode having a relatively short cycle according to a condition given from the outside of the semiconductor memory device. As a result, after the self-refresh operation is completed, it is not necessary to consider the auto-refresh operation, which has always been required to be controlled by the system, and the usability for the user is improved.

[Brief description of drawings]

FIG. 1 is an overall configuration block diagram of a DRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a RAS block in the DRAM.

FIG. 3 is a circuit diagram of a refresh block in the DRAM.

FIG. 4 is an electrical connection diagram of a timer circuit in the DRAM.

FIG. 5 is an electrical connection diagram of an address counter circuit in the DRAM.

FIG. 6 is an operation timing chart of a main part of the DRAM.

FIG. 7 is another block diagram of the timer circuit in the DRAM.

FIG. 8 is a timing diagram for explaining a conventional refresh operation.

[Explanation of symbols]

 21 RAS Block 22 CAS Block 23 Refresh Block 24 Timer Circuit 24A Timer 24B Timer 25 Address Counter 26 Row Address Buffer 27 Column Address Buffer 28 Column Decoder 29 Column Selection Circuit 30 Row Decoder 31 Input / Output Circuit 32 Memory Cell Array Section

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Nozoe 2326 Imai, Ome-shi, Tokyo, Hitachi Device Development Center (72) Inventor Kazuyoshi Oshima 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Shinichi Suga 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (3)

[Claims] 1. A memory cell array portion comprising a plurality of memory cells arranged in a matrix, and internal address control,
In a semiconductor memory device including a self-refresh control unit for refreshing the stored contents of the memory cell array unit at a predetermined cycle, the self-refresh control means includes a first self-refresh control mode having a relatively long cycle and a relatively self-refresh control mode. A semiconductor memory device including a control block for switching between a second self-refresh control mode of a short cycle according to a condition given from the outside of the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the control block switches between the first self-refresh control mode and the second self-refresh control mode based on a state of a row address strobe signal externally applied. . 3. The control block includes a first timer for determining a refresh cycle in the first self-refresh mode, a second timer for determining a refresh cycle in the second self-refresh mode, and this timer. 3. The semiconductor memory device according to claim 1, further comprising a selection circuit for selectively causing an output to participate in refresh control based on a row address strobe signal.