JPH0644385A - Z buffer control circuit - Google Patents

Abstract

PURPOSE:To provide high-speed plotting by simultaneously calculating a Z value for plural picture elements at the time of plotting a horizontal line concerning the acceleration of Z buffer processing in the field of three-dimensional graphics. CONSTITUTION:A three-dimensional image display device is provided with a frame memory 4 for simultaneously writing the plural horizontal picture elements and for permitting the write of the individually designated picture element among them, Z buffer memory 3 for simultaneously reading/writing plural values corresponding to thise picture elements and for permitting the write of the respectively designated picture element among them, plotting mode designation flag 27 to distinguish whether plotting is a horizontal line or a straight line at any arbitrary angle, and plural Z value arithmetic circuits 30 and when the plotting mode designation flag 27 designates the plotting of the horizontal line, the plural bits of the Z buffer memory 3 are simultaneously processed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to speeding up Z buffer processing in the field of three-dimensional graphics. In three-dimensional graphics, speeding up of surface painting processing is required to speed up drawing processing. One of the means is to speed up the Z buffer processing.

[0002]

2. Description of the Related Art FIG. 4 is a conceptual diagram of the configuration of a conventional system. In FIG. 4A, the three-dimensional image display device includes a Z buffer 1, a frame memory 4, and a CRT (Cathode Ray Tu).
be) 5, a processor 6, and a main memory 7.
The Z buffer 1 also includes a Z buffer memory 3 and a Z buffer control circuit 2.

The processor 6 creates drawing data on the main memory 7. The drawing data is configured as, for example, a collection of line segments (straight lines), and when this is written in the frame memory 4, an image is displayed on the CRT 5.

The Z-buffer method is generally used for drawing processing in three-dimensional graphics. The Z buffer is a storage device that holds the depth information of each pixel corresponding to the pixel in the frame memory 4, and when drawing a pixel, the depth information (Z value) of the pixel.
And the Z of the pixel already drawn at that position (XY coordinates)
This is for comparing with the value and controlling so as to leave the one with a shallow depth (small Z value). As a result, when a three-dimensional object is drawn as a two-dimensional image, it is possible to draw a natural image in which the part in the back is hidden by the surface or the ridge line in the foreground.

FIG. 5A is a diagram for explaining the Z value when drawing an arbitrary vector (straight line). When a straight line is drawn from the coordinate (Xs, Ys) to the coordinate (Xe, Ye), the coordinate and the Z value are calculated for each pixel forming the straight line.

The Z value is calculated by giving a value (Zs = initial value) at the starting point coordinates (Xs, Ys) and an increment (Zi) by the processor, and ending point coordinates (Xe, Ye) for each point forming a straight line. Is done until.

Further, if it is smaller than the Z value of the pixel originally at that coordinate, the operation result is written to the Z buffer memory, and the writing of the pixel to the frame memory is allowed (that is, the pixel by new drawing is written). , If large, Z
Both the buffer memory and the frame memory are left as they are (that is, the original pixels remain).

FIG. 4B shows Z centering on the Z value calculation circuit.
The principal part of the buffer control circuit 2 is shown. Reference numeral 22 is an adder, and 23 is an output register, which calculates an initial value Zs and an increment Zi of the Z value given from the processor 6. The output of the output register 23, that is, the new Z value is sent to the Z buffer memory 3 through the signal line 20.

Reference numeral 24 denotes a comparator, which compares the output of the output register 23, that is, the new Z value Zw with the original Z value Zr read from the Z buffer memory 3, and if Zw <Zr, the write enable signal 21. Z buffer memory 3 and frame memory 4
Send to.

The coordinates (addresses) of the Z buffer memory 3 and the frame memory 4 are designated by the X address register 29 and the Y address register 28 as the starting point (Xs, Ys) and the ending point (Xe, Ye).

Generally, these processes are performed for each pixel because the coordinates (X, Y) of pixels forming a straight line are different from each other, or a complicated hardware is usually used for simultaneously processing a plurality of processes. It was

The coordinates of each point on the straight line can be calculated by DDA (Dig
Ital Differencial Analyzer) etc.
Since it is not directly related to the present invention, its explanation is omitted. Similarly, the description of the calculation of the pixel value to be written in the frame memory will be omitted.

In three-dimensional graphics, when an object is drawn as a solid model, surface painting processing is often used.
Since the surface is processed as a group of a large number of horizontal lines in the surface painting processing as shown in FIG. 5B, the calculation of the Z value performed for each pixel as described above greatly affects the processing time.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to realize high-speed drawing by simultaneously performing Z value calculation on a plurality of pixels when drawing a horizontal line.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. A frame memory 4 configured such that a plurality of pixels in the horizontal direction can be simultaneously written, and individually designated pixels among them can be written, and a plurality of values corresponding to the plurality of pixels of the frame memory 4 can be simultaneously read / written. And a Z-buffer memory 3 configured to allow writing of individually designated pixels, a drawing mode designation flag 27 for distinguishing whether the drawing is a horizontal line or a straight line with an arbitrary angle, and a plurality of Z value calculation circuit 30 of FIG.

[0016]

When the drawing mode specifying flag specifies drawing a horizontal line (when the drawing mode specifying flag is "1"), a plurality of pixels in the Z buffer memory 3 are simultaneously processed.

That is, Z values (Zw0 to Zwm) corresponding to a plurality of pixels forming a part of the horizontal line are obtained by a plurality of Z value calculation circuits, and a plurality of corresponding original Z values (Zr0 to Zrm) are obtained. It is read from the Z buffer memory and compared with this. If the Z value of the calculation result is smaller than the original Z value, the corresponding write enable signal (WE0 to WEm) is set to "1", and otherwise it is set to "0". The write enable signal controls the writing of the corresponding pixels in the Z buffer memory and the frame memory. If it is "1", the writing of a new value is permitted, and if it is "0", the writing is not permitted. The original value remains in the frame memory 4.

With this arrangement, when drawing a straight line having an arbitrary angle, the speed is the same as that of the conventional method in which processing is performed in pixel units, but when drawing a horizontal line, it can be made very fast.

[0019]

EXAMPLE A frame memory 4 and a Z buffer memory 1 are
There is no problem with the above processing method if it is configured to allow simultaneous access from a specified address for a certain length,
In order to simplify the configuration, a normal memory configuration method is to access in units of blocks each of which is a power of two.

Further, in the drawing of the horizontal line, there is no problem if the coordinates of the starting point pixel (and the ending point pixel) match the address boundary of the frame memory 4 and the Z buffer memory 3, but since they are generally different, the processing in that case is different. is necessary.

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram of the Z buffer control circuit according to the embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, 25 is a register for holding the initial value of the Z value, 26 is a register for holding the increment of the Z value, 27 is a drawing mode designation flag, and 28 and 29 are the coordinates of the start and end points of the straight line. These registers are set by processor 6.

Reference numeral 30 is a Z value calculation circuit, 31 is a multiple selection circuit for increment Zi, 32 is a write enable signal generation circuit, and 33 is a multiple circuit for increment Zi. The present embodiment is an example of simultaneous 4-bit processing, and four sets of Z value calculation circuits 30 and the like are provided.

FIG. 3 is an explanatory diagram when the address boundary of the memory should be taken into consideration. FIG. 3A shows the relationship between the starting point pixel and the address boundary when the triangle is painted.

In the figure, a triangle is drawn as a group of horizontal lines such as a straight line () at Y = 1. A straight line requires three accesses as shown in the figure when the memory is accessed in units of 4 pixels. At the time of the first access and the last access, it is necessary to leave the original value without writing some pixels by the value of the lower 2 bits of the X coordinate. Further, the contents of calculation of the four pixels that are simultaneously processed are also different.

FIG. 3B is a summary of the contents of the above processing. When the value of the lower 2 bits of X is 0, it corresponds to that of FIG. 3A, and when it is 1, it corresponds to 2 and when it is 3.

The Zi multiple circuit 33 of FIG. 2 is a circuit for producing -3Zi to 4Zi, and can be easily constructed as a combinational logic circuit.
The Zi multiple selection circuit 31 and the write enable signal generation circuit (EN circuit) 32 can also be easily configured according to FIG.

When a straight line having an arbitrary angle is drawn (when the drawing mode designation flag is "0"), the Z value is calculated as it is, and only the write enable signal having the designated address is ". It suffices to configure the circuit so that it is 1 ″, which can be easily realized.

[0029]

EFFECTS OF THE INVENTION In three-dimensional graphics, surface painting processing occupies most, that is, drawing of horizontal lines occupies most. Simultaneous reading and writing of a plurality of memories is easy if limited to the horizontal direction, and according to the present invention, high-speed drawing can be realized as a whole with a relatively simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of a Z buffer control circuit according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a case where an address boundary of a memory should be taken into consideration.

FIG. 4 is a conceptual diagram of a configuration of a conventional system.

FIG. 5 is an explanatory diagram of Z value calculation.

[Explanation of symbols]

 1 Z buffer 2 Z buffer control circuit 3 Z buffer memory 4 Frame memory 5 CRT 6 Processor 7 Main memory 20 Z value signal line 21 Write enable signal 22 Adder 23 Output register 24 Comparator 25 Register holding initial value of Z value 26 Register for holding increment of Z value 27 Drawing mode designation flag 28 Y coordinate register 29 X coordinate register 30 Z value calculation circuit 31 Zi multiple selection circuit 32 Write enable signal creation circuit (EN circuit) 33 Zi multiple circuit

Claims (1)

[Claims] 1. In a three-dimensional image display device, a frame memory (4) configured so that a plurality of pixels in the horizontal direction can be simultaneously written, and individually designated pixels among them can be written, and the frame memory (4) 4) A Z buffer memory (3) configured so that a plurality of values corresponding to a plurality of pixels can be simultaneously read and written, and individually designated pixels of the Z buffer memory (3) can be written, and whether the drawing is a horizontal line or an arbitrary line. A drawing mode designation flag (27) for distinguishing whether the line is an angle and a plurality of Z value calculation circuits (30) are provided. When the drawing mode designation flag (27) specifies drawing a horizontal line, Z A Z-buffer control circuit characterized in that a plurality of bits of a buffer memory (3) are simultaneously processed.