JPH0636601B2 - Digital convergence correction device - Google Patents

Description

The present invention relates to a cathode ray tube (CR) of a raster scan system.
The present invention relates to a convergence correction device in a display using T), and more particularly to a digital convergence correction device that can be suitably used when high-precision correction is required or when the number of scanning lines is expected to change.

[Background of the Invention]

A conventional digital convergence correction device corrects at an arbitrary point between a cross point (hereinafter referred to as an adjustment point) and a cross point (hereinafter referred to as an adjustment point) in a lattice pattern composed of a combination of horizontal and vertical lines assumed on a CRT screen. Data is stored in the memory All correction value memory storage method, only the correction data at the adjustment point is stored, and the correction data at any point between the adjustment points is synchronized with the raster scan of the screen. It is roughly classified into an interpolation calculation method that is obtained by interpolation calculation from the correction data at the adjustment point.

The former requires a large-scale memory device sufficient to store all correction data, and the latter requires a correction data storage capacity for the adjustment points, so a small-scale memory is sufficient, but a real-time interpolation calculation circuit is required. And Therefore, if the interpolation calculation circuit is composed of a digital circuit, the power consumption of the circuit becomes large and the circuit scale becomes large.

In order to solve such a problem in the case of using an interpolation calculation circuit, JP-A-57-2166 and JP-A-59-239.
In No. 88, etc., interpolation calculation is performed by multiplying digital /
An example is shown in which an analog converter (DAC) is used.

Such a conventional example is an example in which a big problem in the past, such as circuit scale and power consumption, has been solved by a very simple means, and can be said to be an excellent method. However, the linear interpolation (linear interpolation) method is used to create the correction data at any point between the adjustment points, and when the correction amount is large or very high correction accuracy is required. However, the above-mentioned conventional technique cannot be said to be sufficiently considered for high-precision correction, because it cannot be dealt with due to the problem of the limit of the linear interpolation method.

Further, in the case of changing the number of raster scanning lines in the display, in the conventional technique as described above, since the memory data is stored corresponding to the scanning lines, it is necessary to rewrite all the correction data in the memory. First, no consideration was given to the fact that the same convergence correction device can be used regardless of the change in the number of scanning lines.

[Object of the Invention]

An object of the present invention is to enable high-precision convergence correction in consideration of the inherent convergence characteristic that the amount of misconvergence becomes large in the peripheral area of the screen of the CRT display, and to reduce the number of raster scanning lines of the display screen. It is an object of the present invention to provide a convenient digital convergence correction device that does not require correction of the convergence correction data even if it is changed.

[Outline of Invention]

The present invention basically belongs to the interpolation calculation method. In the present invention, the basic pattern of the convergence correction amount on the CRT screen was examined, and it was found that highly accurate correction can be performed by replacing the sawtooth wave used in the interpolation calculation with the cubic function curve in the past. This is realized by using a waveform synthesizing circuit and a multiplying circuit capable of analog input. Further, by superimposing the cubic curve of the H cycle for each horizontal (H) cycle of the cubic curve of the vertical (V) cycle used for the interpolation calculation, it is possible to perform the highly accurate correction.

Hereinafter, the above description will be specifically described with reference to the drawings.

FIG. 5 is an explanatory diagram showing a general misconvergence pattern on an in-line array electron gun color CRT screen.

In the figure, K is an in-line array electron gun (three), and R, G, and B show misconvergence patterns of red, green, and blue, respectively.

As is clear from FIG. 5, the amount of misconvergence of the horizontal line becomes maximum at the screen corner, and the central part of the screen, 12 o'clock, 3 o'clock, 6 o'clock when the screen is regarded as a clock face,
It becomes zero in the 9 o'clock direction.

FIG. 6 is an explanatory diagram showing adjustment points for convergence adjustment (correction) on the CRT screen.

In the figure, an example is shown in which _seven adjustment points (V ₁ , V ₂ , ... V ₇ ) in the vertical direction and 13 adjustment points (H ₁ , H ₂ , ... H ₁₃ ) in the horizontal direction are taken.

The number of adjustment points can be set appropriately according to the correction accuracy and operability.

Now, for these 7 points in the vertical direction (V ₁ , V ₂ , ... V ₇ )
FIG. 7 shows the magnitude of the misconvergence amount calculated from the basic form of the misconvergence amount shown in the figure.

FIG. 7 shows the magnitude of the misconvergence amount in one vertical period as is already clear, and FIG. 8 shows one horizontal period among them. 7 and 8 both show the values calculated from the basic form of the misconvergence amount shown in FIG. 5, but in both cases, the shape of the curve shows a cubic function.

As described above, in the conventional interpolation calculation method, since the place where the cubic function should originally be approximated by the polygonal linear function as described above, it is not possible to expect high-precision approximation especially in the corner portion. Is.

In the present invention, it is possible to perform interpolation calculation using a cubic function curve in this respect, so that highly accurate approximation can be desired.

Furthermore, in order to change the number of scanning lines in raster scanning, in the prior art, the memory address at the adjustment point corresponded to the scanning line, so it was necessary to rewrite the memory contents. However, in the present invention, the position of the CRT screen is changed. Since it corresponds to (time position of deflection current), rewriting of memory contents is not required.

That is, a horizontal and vertical blanking signal is used as a reference signal for generating a memory address, and the correction data output time from the memory and the scanning time are completely synchronized.

Example of Invention

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 indicates a frame memory. This frame memory has only to have a memory capacity that is determined by the number of adjustment points and resolution on the CRT screen, and is significantly smaller than the memory of the total memory system that stores all correction value data for each scanning line. Good on scale. Reference numeral 2 denotes a delay circuit having a delay amount corresponding to one horizontal line on the CRT screen, which is a multiplication type digital-analog converter (DA).
C) The data to be input to 3 and the multiplication type digital
The time difference of one row from the data input to the analog converter (DAC) 3A (for example, in FIG. 6, assuming that H ₁ (V ₁ ) is the data input to one multiplication DAC 3 Data is input to the multiplying DAC 3A of V ₂ such that the time difference existing between both input data corresponds to one row). Four
Is an adder circuit, 5 is a low-pass filter, 7 is a waveform synthesis circuit which will be described in detail later, and 8 is horizontal blanking (H-BL).
K) A multiplier for multiplying the pulse to the number of adjustment points in the horizontal direction on the CRT screen and outputting the same, more specifically, using a PLL (face locked loop circuit) and a prescaler. Reference numeral 9 is an H address setting circuit for generating an H address for the frame memory 1 from the output pulse of the multiplier 8, and 10 is a vertical blanking (V-B
LK) pulse is a multiplier for multiplying the number of adjustment points in the vertical direction on the CRT screen and outputting it, and 11 is a V address setting circuit for generating a V address for the frame memory 1 from the output pulse of the multiplier 10. Reference numerals 12 and 13 denote reset pulse generation circuits for the H and V address setting circuits 9 and 11, respectively, and the address setting circuits are generated by reset pulses (generated by the arrival of H-BLK pulse and V-BLK pulse) from these circuits. Reset 9 and 11.

Reference numeral 14 denotes a cross hatch generation circuit, which is H-BL.
CR using K, V-BLK pulse as reference pulse
Set the position of the adjustment point on the T screen.

Here, one of the major features of the present invention, that is, the reason why the correction data stored in the memory 1 does not have to be changed regardless of the number of scanning lines is that the video signal that has been conventionally used as the reference signal is used. The H-BLK and V-BLK pulses on the CRT screen are used in place of the horizontal and vertical sync signals.

That is, the adjustment point on the CRT screen is not fixed depending on the number of scanning lines but is fixed depending on the temporal position of the deflection current, so that the scanning line between the adjustment points is not fixed. The book is irrelevant to the convergence correction operation.
This also applies to the address generation for the memory 1. Since the address where the correction data is stored in the memory 1 corresponds only to the temporal position of the deflection current, even if the number of scanning lines is changed. , That does not affect the validity of the correction data.

That is, if the change circuit on the CRT display side can cope with the change in the number of scanning lines, there is no problem as a convergence correction device.

Next, the basic circuit operation of the embodiment shown in FIG. 1 will be described.

That is, the H, V-BLK pulse signal in FIG. 1 not only serves as a reference signal for the crosshatch generation circuit 14 displayed on the screen at the time of convergence adjustment, but also corresponds to the crosshatch intersection point. It is multiplied by several times the adjustment point, and also serves as a reference signal when the address setting circuits 9 and 11 create an address signal for the frame memory 1.

With this address signal, the CR from the frame memory 1
The correction data at the adjustment point on the T screen is output in synchronization with the changed current. One of the output correction data is input straight to the multiplication type DAC 3A, and the other is input to C.
The signal is input to the other multiplication DAC 3 through the delay circuit 2 which is shifted by one adjustment point in the vertical direction on the RT screen (corresponding to one horizontal line).

By this processing, CR is applied to each DAC3, 3A.
The correction data of the upper and lower adjustment points adjacent to each other on the T screen are input.

At this time, in the DACs 3 and 3A, the interpolation coefficients (C) and (C) 'created in the waveform synthesizing circuit 7 are multiplied, and the respective outputs of the DACs 3 and 3A are added in the adding circuit 4 to adjust the distance between the vertical adjustment points. Interpolation calculation is performed and the result is output through the low-pass filter 5.

The above is the description of the basic operation of the present embodiment.

Here, if the setting of the memory addresses in the setting circuits 9 and 11 is performed so that two sets of correction data corresponding to a shift of one adjustment point in the vertical direction on the CRT screen can be read out, the delay circuit 2 becomes unnecessary.

Figures 2A and 2B show that
It is a block diagram which shows the detail of the waveform synthesizing circuit 7 in the figure.

FIG. 2A shows a circuit configuration in which H-BLK and V-BLK pulses are applied and a necessary function waveform is generated from these pulses. 4A to 4C are adder circuits, 15 and 15A are sawtooth wave generation circuits, and 16, 16A to 16C are integrating circuits, 1
Reference numerals 7, 17A and 17B represent amplitude adjusting circuits.

First, the V system using the V-BLK pulse will be described. The sawtooth wave generation circuit 15 receives a V-BLK pulse and generates a sawtooth wave. The integrating circuit 16 receives the sawtooth wave and generates a parabola as a quadratic curve (since it belongs to the V system, it is called a V parabola).
A receives this V parabola and generates a cubic curve. The amplitude of the cubic curve is finely adjusted by the amplitude adjusting circuit 17, and then added by the adding circuit 4A to the basic sawtooth wave (the basic sawtooth wave of V cycle) from the sawtooth wave generating circuit 15.

On the other hand, the H system using the H-BLK pulse is exactly the same,
The integrating circuit 16B generates an H parabola, and the integrating circuit 16C
Generates a cubic curve, and its amplitude is finely adjusted by the amplitude adjusting circuit 17A, and then is added by the adding circuit 4C to generate the sawtooth wave generating circuit 1.
Added to the H basic sawtooth wave from 5A.

Further, in the adder circuit 4B, the H-cycle curve from the adder circuit 4C is amplitude-adjusted by the amplitude adjuster circuit 17B to the V-cycle fundamental wave from the adder circuit 4A, and then the combined function of H and V ( get a).

In addition, the parabolic wave of H and V and the sawtooth wave are CRT here.
If one in the display is substituted, part of the sawtooth wave generating circuit and the integrating circuit can be omitted.

As described above, the curve necessary for convergence correction, that is, the above-mentioned combining function (a) is combined. Next, the following operation is performed in order to use this waveform for interpolation.

That is, in the multiplication type DACs 3 and 3A in FIG. 1, in order to obtain the correction data by performing the multiplication with the correction data from the frame memory 1, it is necessary to obtain the difference of the V direction adjustment point of the basic correction waveform.

Hereinafter, this will be described with reference to FIGS. 2B and 3. However, FIG. 3 is a waveform diagram of signals at respective portions in FIG. 2B.

First, FIG. 3 (a) is a composite function obtained by the circuit of FIG. 2A.
(a) is shown. In FIG. 3 (a), V ₁ , V ₂ , ...
V ₇ indicates the adjustment point position for convergence correction.

FIG. 3 (b) shows the difference between the adjustment points, and FIG. 3 (c)
Is obtained by aligning the peak-peak values of the waveform in (b) (as shown in p, and applying a peak clamp (position ↑ in the figure) for normalization).

The waveform of FIG. 3 (c) is input to the multiplying DAC 3 in FIG. 1 and is multiplied by the correction data output from the memory 1 to form a misconvergence correction waveform. Fig. 3
Compared with the linear waveform in the conventional linear interpolation method, the waveform in (c) reproduces the curvature of the change in the correction data necessary for precise correction.
When the waveforms of (a) are compared, it will be easily recognized because they are very similar. Therefore, the interpolated data between the adjustment points approaches a true value, which enables highly accurate interpolation.

The other multiplication type DAC 3A in FIG.
The waveform in Fig. (C) 'has been input.
Normalized level E (actually D
It is also clear that the absolute amount when input to the AC is 1, that is, the input value variable range is 0 to 1).

In other words, the waveform of (c) 'is obtained by subtracting the waveform of (c) from the regulation level E as seen in FIG. 3 (p)'.

Next, the synthetic function (a) shown in FIG.
A circuit for outputting the waveforms (C) and (C) 'shown in FIGS. 3C and 3C will be described with reference to FIG. 2B.

In FIG. 2B, 26 is an adjustment point position setting signal input terminal, 27 is a delay circuit for realizing a time delay of one adjustment point in the V direction, and 28 is a reset pulse generation circuit. A sampling circuit 18 samples the value of the adjustment point of the input waveform of FIG. 3 (a) for each adjustment point of V.

Next, this value is held by the hold circuit 19 up to the next adjustment point. This value is subjected to subtraction processing with the waveform of FIG. 3 (a) in the subtraction circuit 24, and the difference between the adjustment points shown in FIG. 3 (b) is obtained. Then, to normalize this difference value,
The variable gain amplifier 20, the reference voltage 22 of the error amplification amplifier 21, the peak value detection circuit 23, the clamp circuit 25 and the like in FIG. 2B are used.

That is, the peak value of the difference (absolute peak value) of FIG. 3 (b) is detected by the peak value detection circuit 23 of FIG. 2B, and the hold circuit 19 holds the time until the next adjustment point comes, Compare with voltage 22.

If the peak value of the difference does not reach the reference voltage, the differential input signal (waveform in FIG. 3 (b)) is amplified by the variable gain amplifier 20 and the error amplification amplifier 21, and the peak / peak value is set to (p).
Align as shown in.

Next, this waveform is input to the clamp circuit 25 to perform peak value clamping (the position indicated by ↑ in FIG. 3 (c)).

The waveform (c) obtained by this processing becomes a multiplication waveform used in the multiplication type DAC 3 in FIG. 1 and has a great effect in producing accurate interpolation data.

The signal input to the other multiplication DAC 3A
The means for creating (c) ′ will be briefly described. To obtain (c) ', the subtraction circuit 24 shown in FIG.
It is sufficient to subtract the waveform of (c) from. If (c) and (c) 'are added here, the condition returns to the reference level E, and the condition for enabling the interpolation calculation shown in FIG. 1 is satisfied.

With the above operation, in the present invention, the interpolation at any point between the adjustment points becomes closer to the true value, and as a result, the smooth interpolation can be performed and the convergence correction can be performed with higher accuracy.

In the embodiments described above, the multiplication type DAC is used. However, it is needless to say that the same function can be realized by using a serial connection of a general DAC (digital-analog converter) and an analog multiplier. However, as a precaution, a specific example thereof is shown in FIG.

In FIG. 4, only the portion that needs to be changed is shown in FIG. 29 is a general digital-to-analog converter, 30
Indicates an analog multiplier.

The circuit of FIG. 4 performs the multiplication operation, which is performed by the multiplication DAC in FIG. 1, by the analog multiplier 30,
The basic operation is the same as that shown in FIG.

〔The invention's effect〕

According to the present invention, since it is possible to perform correction with higher accuracy as compared with the conventional linear interpolation method, it is possible to reduce the number of adjustment points. A reduction in the number of adjustment points directly leads to a reduction in memory capacity, which not only makes it possible to reduce costs, but also
The adjustment time can be greatly reduced. In addition, since the number of adjustment points is reduced, the set value of the address is reduced, the logic configuration can be simplified, and the cost can be reduced.

Further, even if the number of scanning lines for raster scan is changed in the CRT display, it is not necessary to rewrite the correction data stored in the memory, so that there is an advantage that the trouble can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
2 and FIG. 2B are block diagrams showing the details of the waveform synthesizing circuit 7 in FIG. 1 by combining them, and FIG.
FIG. 4 is a waveform diagram showing a signal waveform in each part of FIG. B, FIG. 4 is a block diagram showing a main part of another embodiment of the present invention, and FIG. 5 is a general misconvergence pattern in an in-line array electron gun color CRT. Explanatory drawing showing, CR is CR
Explanatory drawing showing adjustment points for convergence adjustment (correction) on T screen, FIG. 7 is a graph showing the magnitude of misconvergence obtained for seven points in the vertical direction, and FIG.
The figure is a similar graph obtained by obtaining 13 points in the horizontal direction. DESCRIPTION OF SYMBOLS 1 ... Memory, 2 ... Delay circuit, 3, 3A ... Multiplying DAC,
4 ... Adder circuit, 5 ... Low-pass filter, 7 ... Waveform synthesis circuit, 8, 10 ... Multiplier, 9 ... H address setting circuit, 11
... V address setting circuit, 12, 13 ... reset pulse generating circuit, 14 ... crosshatch generating circuit, 29, 29A ...
D / A converter, 30, 30A ... Analog multiplier

Claims (1)

[Claims] 1. A digital convergence correction device for a display using a cathode ray tube (hereinafter abbreviated as CRT) of a raster scan system, wherein m units (horizontal direction in the screen) are assumed on the CRT screen.
A memory device (1) for storing xn (in the vertical direction of the screen) grid points (m and n are integers) as adjustment points and storing a convergence correction amount at the adjustment points, and a horizontal and a vertical line in the CRT screen scanning. An address setting circuit (9, 11) for multiplying a blanking pulse to generate an address of the memory device in synchronization with screen scanning, and an address generated by the address setting circuit as a read address on the CRT screen. The respective convergence correction amounts of two adjustment points adjacent to each other along the scanning direction (hereinafter, one of them is referred to as a first adjustment point and the other is referred to as a second adjustment point) are read out from the memory device. , The first adjustment point convergence correction amount and the second adjustment point convergence correction amount that are adjacent to each other, and are adjacent to each other. And an interpolation calculation means for obtaining and outputting a convergence correction amount at an arbitrary position between the adjustment points by an interpolation calculation, and the interpolation calculation means includes: a first interpolation coefficient output from an interpolation coefficient generation circuit described later; First multiplication means (3) for multiplying the first adjustment point convergence correction amount read from the memory device, a second interpolation coefficient output from an interpolation coefficient generating circuit described later, and the memory. A second multiplication means (3A) for performing multiplication with the second adjustment point convergence correction amount read out from the apparatus and the outputs of the first and second multiplication means are combined to obtain a required value. The interpolation coefficient generating circuit comprises a vertical sawtooth wave, a parabolic wave, and a horizontal sawtooth wave.
A waveform synthesizing circuit (FIG. 2A) for synthesizing parabolic waves to obtain a function waveform having a curvature required for interpolation, and the waveform thus obtained is time-divided by the number of intervals between vertical adjustment points. , A normalization circuit that normalizes the values of the respective divided waveforms and outputs them as a waveform representing the first interpolation coefficient, and an inverse function of the normalized waveforms. Inverse function circuit (24) for generating a corresponding waveform and outputting it as a waveform representing the second interpolation coefficient
And a digital convergence correction device.