JPH06349791A - Thin film-forming method - Google Patents

Abstract

PURPOSE:To remove water and impurities adhering to the surface of a substrate by heating the substrate before cleaning the substrate through plasma etching using a chlorine system gas. CONSTITUTION:After a resist pattern is formed by the use of an exposure apparatus, a via hole 50 is formed in a layer insulation film 40 by RIE using a fluorine system gas. Subsequently, Si substrate 10 with the via hole 50 formed therein is heated in vacuum, after the removal of a resist, by the application of the heat at about 400 deg.C for about 60 minutes. Water and impurities are removed by this heat treatment. This heat treatment may be performed in any of RIE chamber, CVD chamber or carrier chamber. When water and impurities are removed in this manner, it is possible to suppress the generation of chloride, etc., occurring at the time of performing the RIE and to stabilize the RIE to be performed thereafter.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a chemical vapor deposition method (CV).
The present invention relates to a method for forming a wiring structure using the D method), and particularly to wiring used in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have changed from LSI to VLS.
The degree of integration has been improved to I and further to ULSI, and along with this, the miniaturization of the width of wiring and the diameter of connection holes such as via holes has been remarkably advanced. Along with the higher density and higher integration of such semiconductor devices, there has been a demand for a multilayer wiring technique and a technique for miniaturizing metal wiring.

[0003] Such miniaturization cannot be coped with by the technique using the conventional sputtering method.
A CVD method using an organic metal material such as an Al organic compound has been proposed. This CVD method is particularly effective as a technique for sufficiently filling fine holes. The outline of the process of forming the via plug in the via hole by using the CVD method is as follows.

First, a lower metal wiring made of an Al alloy or the like is formed on a base insulating film formed on a Si substrate. Next, after forming an interlayer insulating film on the base insulating film, a via hole is formed in the interlayer insulating film. Next, a metal such as Al is deposited and embedded only in the via hole by the CVD method to form a via plug.

Here, prior to depositing a metal such as Al in the via hole, the lower metal wiring exposed on the bottom surface of the via hole is cleaned by plasma etching using a chlorine-based gas. This is because a metal native oxide film or the like is formed on the lower layer metal wiring exposed on the bottom surface of the via hole. Therefore, if the via plug is formed as it is without removing this natural oxide film, the lower layer metal wiring and the via plug will be formed. This is because there is a problem such as an increase in contact resistance at the interface of the.

[0006]

However, when the cleaning treatment is performed by plasma etching using a chlorine-based gas, chlorine remains on the substrate surface or a compound such as Al chloride is generated, which causes In some cases, the atoms may adhere to the surface, or some of the atoms may be replaced with chlorine atoms on the surface of the insulating film to mix impurities such as chlorine and chlorine compounds. If such a large amount of residual chlorine or compound is present, good selectivity cannot be obtained in the subsequent metal deposition by the CVD method, and the metal cannot be sufficiently embedded in the via hole. Further, these compounds cause an increase in the wiring resistance due to an increase in the contact resistance between the lower layer metal wiring and the via plug, and further cause corrosion of the Al metal wiring etc. due to residual chlorine, thereby lowering the reliability of the metal wiring. Will be done.

Therefore, an object of the present invention is to provide a semiconductor device having a multi-layer wiring structure which solves the above problems.

[0008]

In order to solve the above problems, the present invention is a cleaning method for cleaning a desired region of a substrate on which metal is to be deposited by plasma etching using chlorine-based gas. In a thin film forming method having a chemical treatment step and a metal film deposition step in which a source gas is supplied and a metal is deposited in a desired region by a chemical vapor deposition method to form a metal film, before the cleaning treatment step. The method further includes a heat treatment step of heat treating the substrate.

In order to solve the above problems, the present invention provides
A cleaning treatment step in which a desired region on the substrate where metal is to be deposited is cleaned by plasma etching using a chlorine-based gas, and a source gas is supplied, and a desired region is subjected to chemical vapor deposition to form a metal. A metal film deposition step of depositing a metal film to form a metal film, further comprising a plasma treatment step of exposing the substrate to plasma discharge in an inert gas atmosphere or a hydrogen gas atmosphere before the cleaning treatment step. It is characterized by having.

In order to solve the above problems, the present invention provides
A cleaning treatment step in which a desired region on the substrate where metal is to be deposited is cleaned by plasma etching using a chlorine-based gas, and a source gas is supplied, and a desired region is subjected to chemical vapor deposition to form a metal. And a metal film deposition step of depositing a metal film to form a metal film, the method further comprising a heat treatment step of heat treating the substrate in a hydrogen atmosphere after the cleaning treatment step.

In order to solve the above problems, the present invention provides
A cleaning treatment step in which a desired region on the substrate where metal is to be deposited is cleaned by plasma etching using a chlorine-based gas, and a source gas is supplied, and a desired region is subjected to chemical vapor deposition to form a metal. And a plasma treatment step of exposing the substrate to a plasma discharge in an inert gas atmosphere or a hydrogen gas atmosphere after the cleaning treatment step. It is characterized by

[0012]

According to the above method of the present invention, since the heat treatment is performed before the substrate is cleaned by the plasma etching using the chlorine-based gas, it is possible to remove water and impurities attached to the substrate surface. You can Therefore, impurities such as chloride are hardly generated during plasma etching.

According to the above method of the present invention, the substrate surface is exposed to plasma discharge in an inert gas or hydrogen gas atmosphere before cleaning the substrate by plasma etching using a chlorine-based gas. The attached water and impurities can be removed. Therefore, impurities such as chloride are hardly generated during plasma etching.

According to the above method of claim 3, the substrate is cleaned by plasma etching using a chlorine-based gas, and then the heat treatment is performed. Therefore, when the plasma etching for cleaning is performed, it occurs. Impurities such as chloride can be removed by sublimation.

According to the above method of claim 4, the substrate is exposed to plasma discharge in an inert gas or hydrogen gas atmosphere before the substrate is cleaned by plasma etching using a chlorine-based gas. Impurities such as chlorides generated during the plasma etching for removing the impurities can be removed.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 1A, a base insulating film 20 is formed on the surface of a Si substrate 10, and an Al alloy is deposited to a thickness of 300 to 800 nm on the base insulating film 20 by a sputtering method. The alloy film 31 is formed. Next, the Al alloy film 3
1 is processed into a predetermined wiring pattern to form the lower layer metal wiring 30. The wiring pattern is formed by RIE (reactive ion etching) which is plasma etching using a chlorine-based gas after forming a resist pattern using an exposure device. Next, as shown in FIG. 1B, an interlayer insulating film 40 having a film thickness of 1 μm is formed on the base insulating film 20 on which the lower metal wiring 30 is formed. The interlayer insulating film 40 is formed of SiO ₂ by plasma CVD method.
Is deposited to form a SiO ₂ film, and SOG (Spin
on glass) to form an SOG film, and heat treatment is performed at a necessary temperature. After that, SiO ₂ is deposited again by the plasma CVD method to form a SiO ₂ film.

Next, a photomask is set on the interlayer insulating film 40, a resist pattern is formed using an exposure device, and then RIE using a fluorine-based gas is performed.
As shown in (c), a via hole 50 is formed in the interlayer insulating film 40. Next, after removing the resist, the Si substrate 10 in which the via holes 50 are formed is heated by applying heat at 400 ° C. for 60 minutes in vacuum. This heat treatment removes water and impurities. This heat treatment may be performed in any of the RIE room, the CVD room and the transfer room. By removing water and impurities in this way, it is possible to suppress the generation of chlorides and the like that occur during RIE, and RIE that is performed after this is performed.
Can be stabilized. Although this heat treatment is carried out in vacuum in this embodiment, it may be carried out in a hydrogen gas atmosphere, a nitrogen gas atmosphere, or an inert gas atmosphere such as argon gas instead of being carried out in a vacuum. Also,
At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or in a hydrogen gas atmosphere instead of the heat treatment.

Next, the Si substrate 10 is vacuum transferred to the RIE chamber so as not to be exposed to the atmosphere. In this RIE chamber, the lower metal wiring 30 (Al alloy film) exposed at the bottom of the via hole 50 is cleaned by RIE using a chlorine-based gas.
At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas. Also, the condition for performing RIE is BC
The partial pressure ratio between l ₃ and Ar is 1: 1 and the atmospheric pressure is 100 mTorr and the plasma power is 0.05 W / cm.
^{About 3} , the time required for etching is 10 minutes. Here, it is desirable that the partial pressure of BCl ₃ is 70 mTorr or more and the partial pressure of Ar is 100 mTorr or less. Performing RIE under such conditions is important for enabling selective deposition by the CVD method to be performed thereafter. This cleaning process is performed on the surface of the lower layer metal wiring 30 exposed at the bottom of the via hole 50, when performing fluorine-based RIE performed when forming the via hole, and when performing RI.
When exposed to the atmosphere after E, deposits or alumina film adheres to the deposits or alumina film.
This is because it needs to be removed to prevent the deposition.

Next, the Si substrate thus treated was transported in vacuum and loaded into the CVD chamber. The vacuum condition when the Si substrate is transported is preferably atmospheric pressure of 5 × 10 ⁻⁷ Torr or less. Then, in the CVD chamber, DMAH (AlH (CH ₃ ) ₂ : Dimethyl
1-aluminum-hydride) gas and hydrogen are used as the raw materials to selectively deposit Al from the bottom surface only in the via hole 50 by the thermal CVD method.
As shown in (d), the via plug 5 is placed in the via hole 50.
1 is formed. The conditions for performing the CVD at this time are that the flow rate of hydrogen gas is 500 sccm, and the partial pressure of DMAH is 0.15 To.
It is carried out at rr and a bubbling temperature of 50 ° C. The total pressure in the CVD reaction vessel for forming this film was 2.0 Torr, and the substrate temperature was 210 ° C.

In this way, all the via holes 50 have A
The Al thin film was deposited until 1 was completely filled. Then, when the surface of the insulating film was inspected thereafter, Al deposition was not observed at all.

Next, 400 to 1000 n of Al is sputtered on the upper surface of the via plug 51 and the interlayer insulating film 40.
The upper layer metal wiring 60 is formed as shown in FIG. 1E by using the same method as that for forming the lower layer metal wiring 30 described above by depositing the Al alloy film to a thickness of m. ,
A semiconductor device having a multilayer wiring structure is manufactured.

By the time the semiconductor device using the via structure of the present invention is completed, the surface protection film is formed after the via plug 51 is formed, and heat treatment for removing process damage is performed.

Further, structures necessary for a semiconductor device such as a diffusion layer and a gate electrode are formed in and on the surface of the Si substrate 10. A contact hole exists at a required position of the base insulating film 20, and a contact structure for connecting the lower metal wiring 30 and the diffusion layer or the gate electrode or other structure is formed. If necessary, an antireflection film using W or the like and a barrier metal using TiN or the like are formed between the metal wiring and the insulating film. Further, one or more new interlayer insulating film 40 and metal wiring can be laminated on the upper metal wiring 60. Next, a method of manufacturing the semiconductor device according to the second embodiment of the present invention will be described. First, a base insulating film is formed on the surface of a Si substrate, and an Al alloy is deposited to a film thickness of 300 to 800 nm on the base insulating film by a sputtering method to form an Al alloy film. Next, the Al alloy film is processed into a predetermined wiring pattern to form a lower layer metal wiring. The wiring pattern is formed by RIE using a chlorine-based gas after forming a resist pattern using an exposure device. Next, a film thickness of 1 μm is formed on the underlying insulating film on which the lower metal wiring is formed
An interlayer insulating film of m is formed. This interlayer insulating film is formed in the same manner as in the first embodiment. Next, a photomask is set on the interlayer insulating film, a resist pattern is formed using an exposure device, and then RI using a fluorine-based gas is used.
Via E forms a via hole in the interlayer insulating film. next,
After removing the resist, the Si substrate is vacuum transported to the RIE chamber so as not to be exposed to the atmosphere. In this RIE chamber, the lower metal wiring (Al alloy film) exposed at the bottom of the via hole is cleaned by RIE using chlorine gas. At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas.
The conditions for performing RIE are the same as in the first embodiment. The reason for performing this cleaning process is the same as in the first embodiment.

Next, a hydrogen gas atmosphere (5 × 10 ⁻⁵ Tor)
Heat in r) at 400 ° C. for 30 minutes. By this heat treatment, impurities such as chlorides generated during RIE are sublimated and removed. This heat treatment is performed in the RIE room, CVD
It may be carried out in either a chamber or a transfer chamber. However, since the impurities are sublimated by the heat treatment, it is desirable to provide a heat treatment chamber separately from these chambers. By providing the heat treatment chambers in this way, each chamber is not contaminated by contaminants such as sublimated residual chlorine. At this time, the temperature for heat treatment is preferably 300 ° C. or higher. At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or hydrogen gas instead of the heat treatment.

Next, the Si substrate thus treated was transported in vacuum and loaded into the CVD chamber. The vacuum condition when the Si substrate is transported is preferably atmospheric pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, thermal CVD using a gas of AlH source DMAH and hydrogen as raw materials.
By selectively depositing Al from the bottom surface only in the via hole by the method, a via plug is formed in the via hole. The conditions for performing the CVD at this time are the same as those in the first embodiment.

In this manner, Al thin films were deposited until all the via holes were completely filled with Al. Then, when the surface of the insulating film was inspected thereafter, Al deposition was not observed at all.

Then, Al is deposited to a thickness of 400 to 1000 nm on the interlayer insulating film covering the upper surface of the via plug by a sputtering method to form an Al alloy film, and the same method as that for forming the lower layer metal wiring is performed. An upper metal wiring is formed by using the semiconductor device to manufacture a semiconductor device having a multilayer wiring structure.

The point that a structure required for a semiconductor device is formed in and on the Si substrate is the same as in the case of the first embodiment.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described. First, a base insulating film is formed on the surface of a Si substrate, and an Al alloy is deposited to a film thickness of 300 to 800 nm on the base insulating film by a sputtering method to form an Al alloy film. Next, the Al alloy film is processed into a predetermined wiring pattern to form a lower layer metal wiring. The wiring pattern is formed by RIE using a chlorine-based gas after forming a resist pattern using an exposure device. Next, an interlayer insulating film having a film thickness of 1 μm is formed on the base insulating film on which the lower metal wiring is formed. This interlayer insulating film is formed in the same manner as in the first embodiment. Next, a photomask is set on the interlayer insulating film, a resist pattern is formed using an exposure device, and then a via hole is formed in the interlayer insulating film by RIE using a fluorine-based gas. Next, after removing the resist, the Si in which the via hole is formed is formed.
The substrate is heated by applying 400 ° C. heat in vacuum for 60 minutes. This heat treatment removes water and impurities.
By removing water and impurities in this way, it is possible to suppress the generation of impurities such as chlorides that occur when RIE is performed, and it is possible to stabilize RIE performed thereafter. Although this heat treatment is carried out in vacuum in this embodiment, it may be carried out in a hydrogen gas atmosphere, a nitrogen gas atmosphere, or an inert gas atmosphere such as argon gas instead of being carried out in a vacuum. At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or hydrogen gas instead of the heat treatment.

Next, the Si substrate is vacuum transported to the RIE chamber so as not to be exposed to the atmosphere. In this RIE chamber, the lower metal wiring (Al alloy film) exposed at the bottom of the via hole is cleaned by RIE using chlorine gas. At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas. The conditions for performing RIE are the same as in the first embodiment. Regarding the reason for performing this cleaning process,
This is the same as the first embodiment.

Next, heat at 400 ° C. is applied for 60 minutes in a hydrogen gas atmosphere (5 × 10 ^-5 Torr) without exposing to the atmosphere, and heating is performed. By this heat treatment, impurities such as chlorides generated during RIE are sublimated and removed. At this time, the temperature for heat treatment is preferably 300 ° C. or higher. At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or hydrogen gas instead of the heat treatment.

Next, the Si substrate thus treated was transported in vacuum and loaded into the CVD chamber. The vacuum condition when the Si substrate is transported is preferably atmospheric pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, thermal CVD using a gas of AlH source DMAH and hydrogen as raw materials.
By selectively depositing Al from the bottom surface only in the via hole by the method, a via plug is formed in the via hole. The conditions for performing the CVD at this time are the same as those in the first embodiment.

In this way, Al thin films were deposited until all the via holes were completely filled with Al. Then, when the surface of the insulating film was inspected thereafter, Al deposition was not observed at all.

Then, Al is deposited to a film thickness of 400 to 1000 nm on the interlayer insulating film covering the upper surface of the via plug by a sputtering method to form an Al alloy film, and the same method as that for forming the lower layer metal wiring is performed. The upper layer metal wiring is formed by using the above to manufacture a semiconductor device having a multilayer wiring structure.

The point that the structure required for the semiconductor device is formed in and on the Si substrate is the same as in the case of the first embodiment.

Next, a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described. First, a base insulating film is formed on the surface of a Si substrate, and an Al alloy is deposited to a film thickness of 300 to 800 nm on the base insulating film by a sputtering method to form an Al alloy film. Next, the Al alloy film is processed into a predetermined wiring pattern to form a lower layer metal wiring. The wiring pattern is formed by RIE using a chlorine-based gas after forming a resist pattern using an exposure device. Next, an interlayer insulating film having a film thickness of 1 μm is formed on the base insulating film on which the lower metal wiring is formed. This interlayer insulating film is formed in the same manner as in the first embodiment. Next, a photomask is set on the interlayer insulating film, a resist pattern is formed using an exposure device, and then a via hole is formed in the interlayer insulating film by RIE using a fluorine-based gas. Next, after removing the resist, the Si in which the via hole is formed is formed.
The substrate is exposed to plasma discharge in an argon gas atmosphere.
Note that this plasma treatment may be performed in an atmosphere of another inert gas or hydrogen gas instead of the argon gas.

Next, the plasma-etched Si substrate is heated in vacuum by applying heat at 400 ° C. for 60 minutes.
Although this heat treatment is performed in vacuum in this embodiment, it may be performed in a hydrogen gas atmosphere or an inert gas atmosphere such as nitrogen gas instead of in a vacuum. Water and impurities are removed by this plasma treatment and heat treatment. If moisture and impurities are removed in this way, RIE
It is also possible to suppress the generation of impurities such as chlorides that occur when the above step is performed, and the RIE performed thereafter can be stabilized and performed.

Next, the Si substrate is vacuum transferred to the RIE chamber so as not to be exposed to the atmosphere. In this RIE chamber, the lower metal wiring (Al alloy film) exposed at the bottom of the via hole is cleaned by RIE using chlorine gas. At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas. The conditions for performing RIE are the same as in the first embodiment. Regarding the reason for performing this cleaning process,
This is the same as the first embodiment.

Next, it is exposed to plasma discharge in a hydrogen gas atmosphere without being exposed to the atmosphere. In this plasma treatment, an inert gas such as argon may be used instead of hydrogen gas.

Next, a hydrogen gas atmosphere (5 × 10 ⁻⁵ Tor)
Heat in r) at 400 ° C. for 60 minutes. At this time, the temperature for heat treatment is preferably 300 ° C. or higher. Note that when performing plasma treatment using hydrogen gas, heating at 400 ° C. may be performed at the same time.

By this plasma treatment and heat treatment, impurities such as chlorides generated by chlorine-based RIE when the via holes are formed are removed by sublimation.

Next, the Si substrate thus treated was transported in vacuum and loaded into the CVD chamber. The vacuum condition when the Si substrate is transported is preferably atmospheric pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, thermal CVD using a gas of AlH source DMAH and hydrogen as raw materials.
By selectively depositing Al from the bottom surface only in the via hole by the method, a via plug is formed in the via hole. The conditions for performing the CVD at this time are the same as those in the first embodiment.

Thus, Al thin films were deposited until all the via holes were completely filled with Al. Then, when the surface of the insulating film was inspected thereafter, Al deposition was not observed at all.

Then, Al is deposited to a thickness of 400 to 1000 nm on the interlayer insulating film covering the upper surface of the via plug by a sputtering method to form an Al alloy film, and the same method as the above-mentioned lower metal wiring is formed. The upper layer metal wiring is formed by using the above to manufacture a semiconductor device having a multilayer wiring structure.

The point that the structure required for the semiconductor device is formed in and on the Si substrate is the same as in the case of the first embodiment.

As described above, the first to fourth embodiments of the present invention
In any of the semiconductor devices obtained by the methods up to the examples, the via resistance of the via hole having a diameter of 0.5 μm is 0.3 Ω or less, which is a very low value. It can be seen that high wiring is formed.

In addition to the Al wiring structure shown in this embodiment, for example, a laminated wiring or an antireflection film such as TiN is formed of Al.
It goes without saying that the present invention can be effectively applied even when it is formed on the wiring.

[0049]

As described above in detail, according to the present invention, the heat treatment or the plasma treatment is performed before the cleaning treatment of the substrate by the plasma etching using the chlorine-based gas. The attached water and impurities can be removed. Therefore, impurities such as chloride are hardly generated during plasma etching, and thus plasma etching for cleaning can be stably performed.

Further, according to the present invention, since the heat treatment or the plasma treatment is performed after the substrate is cleaned by the plasma etching using the chlorine-based gas, it is generated when the plasma etching for the cleaning is performed. Impurities such as chloride can be removed by sublimation.

Therefore, since there is almost no residual chlorine or impurities, good selectivity can be obtained in the subsequent metal deposition by the CVD method, and the metal can be sufficiently embedded in the via hole.

Further, since there is almost no residual chlorine, wiring resistance does not increase, and wiring corrosion due to residual chlorine does not occur, so that the reliability of metal wiring is improved.

[Brief description of drawings]

FIG. 1 is an explanatory view showing each manufacturing process of a semiconductor device according to a first embodiment of the invention.

[Explanation of symbols]

10 ... Si substrate, 20 ... Base insulating film, 30 ... Lower layer metal wiring, 40 ... Interlayer insulating film, 50 ... Via hole, 51 ... Via plug, 60 ... Upper layer metal wiring

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Yamamoto 1 Kawasaki-cho, Chuo-ku, Chiba, Chiba Prefecture Technical Research Division, Kawasaki Steel Corporation (72) Inventor Eiichi Kondo 1 Kawasaki-cho, Chuo-ku, Chiba Address Kawasaki Steel Co., Ltd. Technical Research Division (72) Inventor Yoyo Ota 1 Kawasaki-cho, Chuo-ku, Chiba-shi, Chiba Kawasaki Steel Co., Ltd. Technical Research Division

Claims (4)

[Claims] 1. A cleaning process step of cleaning a desired region on a substrate where metal is to be deposited by plasma etching using chlorine-based gas, and supplying a source gas,
A thin film forming method comprising a metal film depositing step of depositing a metal by a chemical vapor deposition method to form a metal film in the desired region, wherein a heat treatment of heat treating the substrate before the cleaning treatment step A method for forming a thin film, which further comprises steps. 2. A cleaning process for cleaning a desired region on a substrate where a metal is to be deposited by plasma etching using chlorine-based gas, and supplying a source gas,
A thin film forming method comprising a metal film deposition step of depositing a metal by a chemical vapor deposition method to form a metal film in the desired region, wherein the substrate is treated with an inert gas atmosphere or before the cleaning treatment step. A method of forming a thin film, further comprising a plasma treatment step of exposing to plasma discharge in a hydrogen gas atmosphere. 3. A cleaning processing step of cleaning a desired region on the substrate where a metal is to be deposited by plasma etching using a chlorine-based gas, and supplying a source gas,
A thin film forming method comprising a metal film deposition step of depositing a metal in the desired region by chemical vapor deposition to form a metal film, wherein the substrate is heat-treated in a hydrogen atmosphere after the cleaning treatment step. A method of forming a thin film, further comprising a heat treatment step of: 4. A cleaning process for cleaning a desired region on the substrate where metal is to be deposited by plasma etching using a chlorine-based gas, and supplying a source gas,
A thin film forming method comprising a metal film depositing step of depositing a metal by a chemical vapor deposition method to form a metal film in the desired region, wherein the substrate is treated with an inert gas atmosphere or hydrogen after the cleaning treatment step. A method of forming a thin film, further comprising a plasma treatment step of exposing to plasma discharge in a gas atmosphere.