JPH0628281B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method suitable for use in manufacturing a MOS IC in which an insulating layer is selectively and finely formed.

BACKGROUND ART AND ITS PROBLEMS Conventionally, in a semiconductor integrated circuit such as a MOS IC, as a device isolation technique for electrically isolating a plurality of circuit devices formed on a common silicon substrate, a so-called CVD method is used for silicon nitride Si ₃ N. _The selective oxidation method using _four layers as a mask has been widely used. In this selective oxidation method, when thermal oxidation is selectively performed on a silicon substrate to form an oxide insulating layer, a Si ₃ N ₄ layer serving as a silicon nitride serving as an oxidation mask is formed on the surface of the semiconductor substrate. It has been generally performed to selectively oxidize a semiconductor substrate through an opening formed therein. In this case, if the Si ₃ N ₄ layer is directly formed on the silicon substrate as an oxidation mask layer, the intrinsic stress in the Si ₃ N ₄ layer causes a strain at the Si-SiN ₄ interface, which causes a subsequent heat treatment. Instability was caused by causing crystal defects.

Therefore, when using an oxidation mask made of a Si ₃ N ₄ layer, first, as shown in FIG. 1, several hundred Å is formed on the surface of the silicon substrate (1).
A pad layer (2) consisting of a thin SiO ₂ film was formed, and a nitride Si ₃ N ₄ layer (3) as an oxidation mask was deposited thereon. Then, an opening (4) is formed in a portion of the Si ₃ N ₄ layer (3) which is to be thermally oxidized by photoetching or the like, and the surface of the silicon substrate (1) is thermally oxidized through the opening (4). Then, as shown in FIG. 2, the oxide layer (5) is selectively formed on the silicon substrate (1). However, in the case where the SiO ₂ pad layer (2) having no oxidation masking effect is interposed between the substrate (1) under the Si ₃ N ₄ layer (3) as an oxidation mask. Due to the substantial gap of the SiO ₂ layer (2), a beak-like shape extends around the obtained oxide layer (5) under the edge of the opening (4) of the mask layer (3). The so-called bird's beak part (6) is formed and this is the oxide layer (5)
However, it was difficult to improve the degree of integration of circuit elements in an integrated circuit, for example.

Another drawback of the manufacturing method using the Si ₃ N ₄ layer as an oxidation mask is that the film thickness ratio between the Si layer consumed by thermal oxidation and the SiO ₂ layer formed is about 0.4: 1. Therefore, a step is formed on the surface, which makes fine processing and multilayer wiring difficult. In order to solve this drawback, it has been proposed that the Si ₃ N ₄ layer is processed and etched by the lithographic technique, and then the silicon substrate is further etched and then oxidized, but in this case, more bird's beak parts (6) occur At the same time, a bird's-head portion (7) having a protruding shape was formed and the surface was not flat. Since the bird's beak portion (6) and the bird's head portion (7) are formed, the conventional semiconductor device manufacturing method is not suitable for manufacturing a miniaturized MOS IC having a channel width or the like. Therefore, the SWAMI method has recently been proposed as a new selective oxidation method that can be used for manufacturing miniaturized MOS ICs. The process of the SWAMI method will be described with reference to FIG. In FIG. 4, parts corresponding to those in FIGS. 1, 2, and 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

On the surface of the silicon substrate (1), a pad layer (2) made of a thin SiO ₂ layer having a thickness of several hundred Å is formed. Next, a nitride Si ₃ N ₄ layer (3) as an oxidation mask is deposited on the pad layer (2) by, for example, a so-called CVD method. Next, the pad layer (2), Si
_{After the} recesses (8a) and (8b) are formed in the ₃ N ₄ layer (3) and the silicon substrate (1) by the reactive ion etching method, the channel stopper layer (9) is ion-implanted in a predetermined range. After forming, the used resist (not shown) is peeled off. Next, as shown in FIG. 4C, the Si ₃ N ₄ layer (1
0), SiO ₂ layer (11) is laminated. Next, as shown in FIG. 4D, the SiO ₂ layer (1
1) The Si ₃ N ₄ layer (10) is removed, and the etching is stopped at the lowermost SiO ₂ layer (11). Next, the SiO ₂ layer (1
1) is removed by etching (Fig. 4E). Then Si
_As shown in FIG. 4F, a SiO ₂ layer (12) is formed by a selective oxidation method using the ₃ N ₄ layer (10) as a mask, for example, the LOCOS method. Then, Si ₃ N ₄ layer (10) SiO ₂ layer formed during the selective oxidation by LOCOS method on, Si ₃ N ₄ layer (10) and the recess (8a) of the silicon substrate (1) (8b) The SiO ₂ layer (12a) on the convex portion between and is removed by etching to obtain the final shape of FIG. 4G. Although the SWAMI method can be applied to the manufacture of miniaturized MOS ICs, it has a drawback in that the number of semiconductor substrate manufacturing steps is increased as compared with the usual selective oxidation method.

Object of the Invention The method of manufacturing a semiconductor substrate of the present invention aims to solve the above-mentioned drawbacks and to obtain a fine semiconductor device with stable quality in a simple process.

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor substrate according to the present invention comprises a step of forming an amorphous layer containing silicon on one main surface of a silicon substrate, and a step of implanting nitrogen ions into the silicon substrate through the amorphous layer. , A step of annealing a silicon substrate to form a nitride layer having a thickness of 200 to 1000Å in contact with the amorphous layer under a predetermined pattern in a predetermined pattern, and leaving a predetermined portion of the nitride layer on the silicon substrate. The step of forming the recess and the SiO _{2 in the} recess
Since it has a step of forming a layer, the energy at the time of the above-mentioned ion implantation is ▲ N ⁺ ₂ ▼ 10 to 50 KeV (N ^{+ 5 to} 25K
eV) and the dose amount is 5 × 10 ^{16 to} 3 × 10 ¹⁷ cm
^-2 (N ⁺ 1 × 10 ^{17 to} 6 × 10 ¹⁷ cm ^-2 ), which is intended to obtain a fine semiconductor device with stable quality in a simple process.

Embodiment An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIG. In FIG. 5,
Parts corresponding to those in FIGS. 1, 2, 3, and 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

First, as the silicon substrate (1), for example, n of [100] plane orientation
Prepare a mold of 2-3 Ω-cm. Then, 100 Å of the thermal oxidation layer (2 ') which is an amorphous layer is attached to the silicon substrate (1), and N ₂ ions are ion-implanted at a dose amount of, for example, 20 KeV and 1.0 × 10 ¹⁷ cm ^-2 (fifth). (Figure A). After such implantation, annealing is performed in a nitrogen atmosphere at 900 ° C for 20 minutes, and then in an oxygen atmosphere at 900 ° C for 60 minutes to obtain a SiO ₂ layer (2) of about 200 Å on the surface and the lower layer. About 300Å of homogeneous Si
_{A 3} N ₄ layer (3) is formed. Next, after removing the SiO ₂ layer and the Si ₃ N ₄ layer of the portion to be selectively oxidized by the photolithography technique by solution etching or reactive ion etching, about 2500 Å of the silicon substrate (1) is further removed by reactive ion etching. (Fig. 5C). In this case, etching removal is performed by a thickness of 0.2 to 0.5 times the desired selective oxide layer. After this, after performing low temperature annealing or chemical treatment for recovering the chemical and physical damage caused by reactive ion etching, 90 ° C. under high pressure of 5 kg / cm ^2.
Oxidation is performed at 0 ° C. for 60 minutes to grow a SiO ₂ layer (5) of about 6000Å (FIG. 5D). In the semiconductor substrate (1) after selective oxidation obtained in this example, a cross-sectional view of a main part (5th embodiment)
As is clear from Figure E), there is no bird's beak and Si
The thickness of the bird's head was less than 1000 Å and the surface was flat against the O ₂ selective oxidation layer (5) of 6000 Å. In this embodiment, the energy of N ₂ ion implantation is ▲ N
⁺ ₂ ▼ 10KeV (N ^{+ 5 to} 25KeV) range, dose amount is ▲ N ⁺ ₂
▼ 5 x 10 ^{16 to} 3.0 x 10 ¹⁷ cm ^-2 (N ⁺ 1 x 10 ^{17 to} 3.0 x 10 ¹⁷
cm ^-2 ) can be selected. Further, the annealing and oxidation temperatures can be selected within the range of 800 to 1100 ° C. Further, even if the SiO ₂ layer after had row summer selective oxidation such as SiO ₂ layer 0.5 to 1.2 times the thickness can be obtained of the SiO ₂ layer (5) as a desired selective oxidation layer to be etched is removed Good. In addition, the surface of the surface after the selective oxidation obtained in this Example
Although a 1000 Å bird's head could be produced, it could be removed by a well-known method in which a photoresist having high viscosity was applied and then flattened by reactive ion etching.

As described above, according to this embodiment, the silicon substrate (1)
After nitrogen to form a Si ₃ N ₄ layer in close contact with Yotsute silicon substrate (1) in that the ion implantation annealing (3), were etched removed Si ₃ N ₄ layers of (3) the portion of the selective oxidation, the Further, since the silicon substrate (1) is etched and removed by a thickness of 0.2 to 0.5 times the desired selective oxidation layer and then the selective oxidation is performed, there is an advantage that flat element separation with no steps or few steps on the wafer surface can be achieved. Moreover, unlike the Si ₃ N ₄ layer formed by the conventional CVD method, the adhesion between the Si ₃ N ₄ layer and the silicon substrate is very good, so bird's beaks hardly occur, and for the same reason, the ion implantation energy is N ⁺ ₂ ▼ 10KeV ~ 50KeV (N
^{+ 5~25KeV)} the Yotsute Si ₃ N ₄ layer thickness to be selected in the 200-1000
It can be selected as thin as Å, so the stress that acts during selective oxidation can be reduced, which has the advantage of not introducing crystal defects.
Therefore, there is an advantage that a fine semiconductor device such as a MOS IC can be obtained with stable quality by a simple process.

FIG. 6 shows another embodiment of the present invention. In FIG. 6, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

Photoresist (14
After covering with a) and (14b), the same nitrogen ion implantation as in the above method is performed (Fig. 6B), after resist removal, annealing is performed in a nitrogen atmosphere at 900 ° C for 20 minutes, and at 900 ° C under a high pressure of 5 kg / cm ² . A 6000Å SiO ₂ film is grown by oxidizing for about 60 minutes. At this time, the area implanted with nitrogen ions is 200Å
It consists of a SiO ₂ film (2) and a 300 Å Si ₃ N ₄ layer (3). NH
After etching and removing the SiO ₂ layer (2) with a solution of ₄ F: HF = 100: 12, high pressure oxidation at 900 ° C. and 5 kg / cm ^{2 was performed} again to obtain 6000.
Å Selective oxide layers (5a) and (5b) are grown. It can be easily understood that the same effects as in the above-described embodiment can be obtained in this example as well.

According to the method of manufacturing a semiconductor device of the present invention, a recess is formed in a silicon substrate while leaving a predetermined portion of the nitride material, and the recess is formed with SiO 2.
_{Since the two} layers are formed, there is an advantage that a fine semiconductor device can be obtained with stable quality in a simple process because element isolation having a flat surface without bird's beaks can be performed.

[Brief description of drawings]

1 and 2 are sectional views showing an example of a conventional method for manufacturing a semiconductor device, FIG. 3 is a sectional view showing an essential part of another example of a method for manufacturing a conventional semiconductor device, and FIG. 5 is a sectional view showing a manufacturing process of still another example of the method for manufacturing a semiconductor device, FIG. 5 is a sectional view showing a manufacturing process of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 6 is a semiconductor device of the present invention. FIG. 9 is a cross-sectional view showing the manufacturing process of another embodiment of the manufacturing method of FIG. (1) is a silicon substrate, (2) is a SiO ₂ layer, (3) is a silicon nitride layer, (5a) and (5b) are SiO ₂ layers, and (8a) and (8b) are concave portions.

Front page continued (72) Inventor Takashi Shimada 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) Reference JP-A-57-54347 (JP, A) JP-A-58-151057 (JP, A) JP-A-51-53488 (JP, A) JP-A-55-162235 (JP, A) JP-A-59-191350 (JP, A)

Claims (3)

[Claims] 1. A step of forming an amorphous layer containing silicon on one main surface of a silicon substrate, and nitrogen ions of N ₂ ⁺¹⁰ keV or more 50 on the silicon substrate through the amorphous layer.
a step of implanting with an energy of less than keV (N ^{+ 5} keV or more and less than 25 keV), annealing the silicon substrate, and contacting the amorphous layer in the silicon substrate under the amorphous layer, and having a thickness of 200 to 1000Å A step of forming a nitride layer in a predetermined pattern, a step of forming a recess in the silicon substrate leaving a predetermined portion of the nitride layer, and SiO _{2 in} the recess.
And a step of forming a layer. 2. A dose amount during the ion implantation is 5 × 10 5.
^{16 ~3x10 17 cm -2 (N +} 1x10 17 ~6x10 17 c
m ⁻² ). The method for manufacturing a semiconductor device according to claim 1, wherein 3. The amorphous layer containing silicon is a silicon oxide layer.
A method of manufacturing a semiconductor device according to the item.